JP2002151525A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materialize a TFT capable of high-speed operation by manufacturing a semiconductor film excellent in crystallinity and using the above semiconductor film. SOLUTION: An insulating film is made on a semiconductor layer, and a gate electrode is made on the above insulating film, and then impurity elements are introduced into the above semiconductor layer, using the above gate electrode as a mask, and further metallic elements to selectively accelerate crystallization are introduced into the above semiconductor layer. Then, a heat treatment is performed for activation of the above impurity elements and crystallization of the semiconductor layer. But in this stage, a amorphous region exists in the semiconductor layer or many defects exist within crystal grains. Therefore, a laser beam is applied to it for crystallization and improvement of crystallinity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to an electro-optical device represented by a liquid crystal display device and a configuration of an electric device including the electro-optical device as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and the above-described electro-optical device and electric device are also included in the category.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (TFT) has been constructed using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface, and a large-area integrated circuit formed by the TFT has been developed. The development of a semiconductor device having the same is progressing. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. In particular, a TFT using a crystalline semiconductor film (typically, a crystalline silicon film) as an active region has high field-effect mobility; therefore, various functional circuits can be formed.

[0003] The crystallinity of the crystalline semiconductor film has a great influence on the electrical characteristics when a TFT is manufactured. At present, the amorphous semiconductor film is often crystallized to form a crystalline semiconductor film. Crystallinity refers to the degree of regularity of atomic arrangement in a crystal. When a TFT is manufactured using a crystalline semiconductor film with good crystallinity, its electrical characteristics are considered to be good. Become.

[0004] A doping process is one of the processes that particularly affect the crystallinity of a semiconductor film. In the doping process, the energy of ions implanted into the semiconductor film is much higher than the binding energy of elements forming the semiconductor film. Therefore, ions implanted into the semiconductor film repel elements forming the semiconductor film from lattice points, causing defects in the crystal. Therefore, after the doping process, a heating process is often performed to recover the defect and activate the implanted ions at the same time.

As described above, the crystallinity of a semiconductor film is variously affected in the process of manufacturing a TFT, and attempts have been made to manufacture a crystalline semiconductor film having good crystallinity.

For example, “High-Performance Low-Tempera
ture Poly-Silicon Thin Film Transistors Fabricated
by New Metal-Induced Lateral Crystallization Proc
ess; Jpn. J. Appl. Phys. Vol. 37 (1998) pp. 4244-42
47 ”will be described. After an amorphous silicon layer having a desired shape is formed over a substrate, a gate insulating film and a gate electrode are formed. Next, nickel (Ni)
, Followed by a doping treatment of an impurity element. Here, since the gate electrode is formed over the semiconductor layer, nickel is added to the source region and the drain region, but is not added to the channel formation region. Thereafter, crystallization of the amorphous silicon layer and activation of the impurity element are simultaneously performed by heat treatment. As described above, nickel is not added to the channel formation region. (FIG. 3A) However, crystal growth occurs in the lateral direction with nickel added to the source region and the drain region as a nucleus, so that the channel formation region also crystallizes. (FIG. 3
(B) In order to avoid that crystal grains grown laterally from the source and drain regions collide with the channel formation region and form a large crystal grain boundary, FIG.
As described in JP-A-2003-129, a method has been reported in which a mask is partially provided, nickel is added, the mask is removed, and then crystallization is performed. (FIG. 3 (D))

[0007]

However, a TFT manufactured by the above-described method does not have good electrical characteristics. In particular, the sub-threshold coefficient (S value), which is an important parameter for judging the performance of the TFT, and the characteristics of the field-effect mobility are not good.

The present invention is a technique for solving such a problem. In an electro-optical device and a semiconductor device represented by an active matrix type liquid crystal display device manufactured using a TFT, the operation characteristics of the semiconductor device are described. And to improve reliability.

[0009]

According to the present invention, a semiconductor layer to which a metal element is selectively added is crystallized by heat treatment and then irradiated with a laser beam to further improve the crystallinity of the semiconductor layer. It is characterized by improving.
By the heat treatment, crystal growth is performed in a lateral direction from the region where the metal element is added to the region where the metal element is not added. Therefore, in a semiconductor layer to which the metal element is not added, an amorphous region may remain without being crystallized. Further, the semiconductor layer after the heat treatment has many defects in crystal grains. Therefore, it is characterized in that the remaining amorphous region is crystallized by irradiating a laser beam after the heat treatment, and the crystal defect is compensated.

[0010] A semi-structure of the present invention disclosed in this specification is that a semiconductor layer is formed on a substrate, an insulating film is formed on the semiconductor layer, a gate electrode is formed on the insulating film, Is used as a mask to introduce an impurity element into the semiconductor layer, selectively introduce a metal element into the semiconductor layer into which the impurity element is introduced, crystallize the semiconductor layer by heat treatment, and activate the impurity element. Irradiating a laser beam.

In the above structure, it is desirable to use a substrate through which a part of the laser beam passes. But,
Even the same substrate has different transmittance depending on the wavelength. As an example,
FIG. 2 shows the transmittance of the 1737 substrate manufactured by Corning and the synthetic quartz glass substrate manufactured by Asahi Glass Co. with respect to the wavelength. FIG.
It can be seen from the graph that the transmittance changes depending on the wavelength. In this specification, the surface of the substrate is defined as a surface on which a film is formed, and the back surface of the substrate is defined as a surface opposite to the surface on which a film is formed.

In the above structure, the metal element is F
e, Co, Ni, Ru, Rh, Pd, Os, Ir, P
t, Cu, Ag, Au, Al, In, Sn, Pb, P,
One or a plurality of elements selected from As and Sb may be used, and details of the crystallization method using the metal element are described in JP-A-7-183540.
Here, the contents of the publication will be briefly described. First, a small amount of a metal element such as nickel, palladium, or lead is added to an amorphous semiconductor film. As a method of addition, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. When heat treatment is performed after the addition, a crystalline semiconductor film having good crystallinity can be obtained. The optimal heating temperature and heating time for crystallization depend on the amount of the metal element added and the state of the amorphous semiconductor film.

In the above structure, the impurity element is n
It is assumed that the impurity element is an impurity element imparting a pattern or an impurity element imparting a p-type.

In the above structure, the laser beam may be a pulsed or continuous wave gas laser or a laser beam oscillated from a solid-state laser. For example, a gas laser, there are an excimer laser, Ar laser, Kr laser and the like, as a solid-state laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, a glass laser, ruby laser, alexandrite laser, Ti: sapphire laser Etc. can be used. Further, a harmonic converted by a nonlinear optical element may be used.

In the above structure, the laser beam is emitted from the front side or the back side of the substrate, or from both the front side and the back side. The channel formation region below the gate electrode needs to have particularly good crystallinity among the semiconductor layers. However, a gate electrode exists above the channel formation region, and the gate electrode does not reach the semiconductor layer unless the gate electrode is transparent to a laser beam. Therefore, depending on the material of the gate electrode, it is necessary to irradiate the laser beam on the front side or the back side of the substrate, or on both the front side and the back side. Of course, when the laser beam is irradiated from the front side, it is necessary to use a gate electrode having transparency to the laser beam. When irradiating the laser beam from the back side,
It is necessary to use a substrate having transparency to the laser beam. When the laser beam is irradiated from the front surface side and the back surface side, it is necessary to use a substrate having transparency to the laser beam and to form a gate electrode having transparency to the laser beam.

Further, a semiconductor device represented by a liquid crystal display device or an EL display device is manufactured by using the TFT manufactured by the above structure.

[0017]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to the sectional view of FIG.

In FIG. 1A, a glass substrate such as a non-alkali glass such as a synthetic quartz glass substrate or a barium borosilicate glass aluminoborosilicate glass may be used as the substrate 11. For example, Corning 7059
Glass, 1737 glass, or the like can be preferably used. However, if the laser beam is irradiated from the back side, or the front side and the back side of the substrate at the time of the laser beam irradiation in the subsequent step, the substrate 11 needs to have transparency to the wavelength of the laser beam.

A base insulating film 12 is formed of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like on the substrate 11 by a known means (LPCVD, plasma CVD, or the like). Note that the base insulating film 12 needs to have transparency with respect to the wavelength of a laser oscillator used in a later step.

Next, the semiconductor layer 12 is formed to a thickness of 10 to 200 nm (preferably 30 to 100 nm) by a known means such as a plasma CVD method or a sputtering method, and then patterned into a desired shape to form the semiconductor layer 13. , 14 are formed. Here, it is assumed that the semiconductor layer 13 is an n-channel TFT and the semiconductor layer 14 is a p-channel TFT. The semiconductor film 12 includes an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.

Next, a gate insulating film 15 covering the semiconductor layers 13 and 14 is formed. The gate insulating film 15 is made of plasma C
Using the VD method or the sputtering method, the thickness is 40 to 150 n
m is formed of an insulating film containing silicon.

Next, as shown in FIG. 1B, a conductive film 16 having a thickness of 100 to 500 nm is formed on the gate insulating film 15. Ta, W, Ti, Mo, C
It may be formed of an element selected from u, Cr, and Nd, an alloy material or a compound material containing the element as a main component, or a semiconductor film typified by a polycrystalline silicon film. Further, an AgPdCu alloy may be used. In addition, an oxide conductive film transparent to visible light (typically, ITO
Film).

Next, a mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed to form conductive layers 17 and 18.

Next, using the conductive layers 17 and 18 as a mask, the gate insulating film 15 is selectively removed to remove the insulating layer 1.
9 and 20 are formed. (Fig. 1 (C))

Then, first and second doping processes are performed to add an impurity element to the semiconductor layer. (Figure 1
(C) Doping treatment may be performed by an ion doping method or an ion implantation method. The ion doping method is performed under the conditions of a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 5 to 100 keV. In this case, the conductive layer 1
7 and 18 serve as masks for impurity elements, and impurity regions 21 and 22 are formed in a self-aligned manner. First, an impurity element imparting n-type is added, and subsequently, an impurity element imparting p-type is added to form impurity regions 26 and 27. However, as shown in FIGS. 1C and 1D, when an impurity element imparting n-type is added,
The semiconductor layer forming the channel TFT is covered with a mask 23 made of resist, and when adding an impurity element imparting p-type, the semiconductor layer forming the n-channel TFT is covered with a mask 25 made of resist.

Next, a metal-containing layer 28 is formed by adding a metal element. The metal elements include Fe, C
o, Ni, Ru, Rh, Pd, Os, Ir, Pt, C
u, Ag, Au, Al, In, Sn, Pb, P, As,
One or a plurality of elements selected from Sb may be used, and the addition method may be a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like. At this time, as shown in FIG. 3C, a mask is partially formed, and a crystal grain boundary formed when the semiconductor layer is crystallized by heat treatment is formed not in a channel formation region but in a source region or a source region. There is also a method of forming it in the drain region.

Next, as shown in FIG. 1E, crystallization of the semiconductor layer and activation of impurity elements are performed by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace or a rapid thermal annealing method (R
TA method). In the crystallization, crystal growth is performed using a metal element selectively added to the semiconductor layer as a nucleus, and crystal growth is performed in a lateral direction also in a channel formation region where the metal element is not added.

FIG. 1F is a view for explaining a process of irradiating a laser beam from the back surface side of the substrate to improve the crystallinity of the semiconductor layer. In this case, the case where the laser beam is irradiated from the back side is shown here, but the conductive layer 1
If the laser beams 7 and 18 are formed of a material having transparency to the laser beam, the laser beam can be irradiated from the front side or the front side and the back side of the substrate. The optimum conditions vary depending on the substrate used, the thickness of the base insulating film, and the like.

First, a laser oscillator used in the laser annealing method will be described. For example, an excimer laser has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. Further, not only a pulse oscillation excimer laser but also a continuous oscillation excimer laser or other pulse oscillation or continuous oscillation gas laser or solid laser can be used. For example, gas lasers include an Ar laser and a Kr laser, and solid lasers such as a YAG laser and a YV laser.
O ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, T
i: A sapphire laser or the like can also be used. Of course, a harmonic converted by the nonlinear element may be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, when irradiating a laser beam, the substrate may be heated to about 500 degrees. By doing so, a decrease in the outflow rate of heat in the semiconductor film is expected, and the grain size of the crystal grains can be increased.

Using any one of the laser oscillators described above and irradiating a laser beam in any atmosphere,
The semiconductor layer is crystallized.

The crystalline semiconductor film formed by irradiating a laser beam is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or an atmosphere containing hydrogen generated by plasma. 200 ~ 450 ℃
The remaining heat can be reduced by the heat treatment.

It is known that when a TFT is manufactured using a semiconductor layer in which the metal element remains in the channel formation region, the off-current value of its electrical characteristics increases.
For this reason, the present applicant has developed a technique for removing a metal element from a semiconductor layer (a gettering technique),
No. 0363. The gettering technique means that the semiconductor layer in which the metal element remains
Heat treatment by selectively introducing elements belonging to the group
By capturing the metal element in a region (a gettering region) into which an element belonging to Group 15 is introduced, the metal element is transferred to a region (an area to be gettered) into which an element belonging to Group 15 is not introduced. It can be eliminated or reduced.

In the present invention, the above-mentioned gettering technique may be used after irradiating a laser beam. That is, with the use of the gate electrode as a mask, an element belonging to Group 15 may be selectively introduced into the semiconductor layer and heat treatment may be performed to remove or reduce the metal element from the channel formation region.

By manufacturing a TFT using the crystalline semiconductor layer manufactured as described above, the electrical characteristics of the TFT can be improved.

[0035]

[Embodiment 1] An embodiment of the present invention will be described with reference to the sectional view of FIG.

In FIG. 1A, a glass substrate such as a non-alkali glass such as a synthetic quartz glass substrate and a barium borosilicate glass aluminoborosilicate glass may be used as the substrate 11. For example, Corning 7059
Glass, 1737 glass, or the like can be preferably used. In this example, a 1737 glass substrate was used.

A base insulating film 12 is formed on the substrate 11 by a known means (LPCVD, plasma CVD, or the like) using a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like. In this embodiment, a 50-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 27%, N = 24%, H = 17)
%).

Next, the semiconductor layer 12 is formed to a thickness of 10 to 200 nm (preferably 30 to 100 nm) by a known means such as a plasma CVD method or a sputtering method, and then patterned into a desired shape to form the semiconductor layer 13. , 14 are formed. Here, it is assumed that the semiconductor layer 13 is an n-channel TFT and the semiconductor layer 14 is a p-channel TFT. The semiconductor film 12 includes an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. In this embodiment, the plasma CVD method is used to
nm of an amorphous silicon film was formed.

Next, a gate insulating film 15 covering the semiconductor layers 13 and 14 is formed. The gate insulating film 15 is made of plasma C
Using the VD method or the sputtering method, the thickness is 40 to 150 n
m is formed of an insulating film containing silicon. In this embodiment,
A silicon oxynitride film having a thickness of 110 nm (composition ratio: Si = 32%, O = 59%, N = 7%, H
= 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 1B, a conductive film 16 having a thickness of 100 to 500 nm is formed on the gate insulating film 15. In this example, a conductive film made of a TaN film having a thickness of 30 nm was formed. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. As the conductive film, Ta, W, Ti,
It may be formed of an element selected from Mo, Cu, Cr, and Nd, an alloy material or a compound material containing the element as a main component, or a semiconductor film typified by a polycrystalline silicon film. Further, an AgPdCu alloy may be used.
Further, an oxide conductive film (typically, an ITO film) transparent to visible light may be used.

Next, a mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed to form conductive layers 17 and 18.

Next, using the conductive layers 17 and 18 as a mask, the gate insulating film 15 is selectively removed to remove the insulating layer 1.
9 and 20 are formed. (Fig. 1 (C))

Then, first and second doping processes are performed to add an impurity element to the semiconductor layer. (Figure 1
(C) Doping treatment may be performed by an ion doping method or an ion implantation method. The ion doping method is performed under the conditions of a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 5 to 100 keV. In this case, the conductive layer 1
7 and 18 serve as masks for impurity elements, and impurity regions 21 to 24 are formed in a self-aligned manner. In this embodiment, as a first doping process, phosphorus (P) is added as an impurity element for imparting n-type, and impurity regions 21 to 21 are added.
The concentration of phosphorus was adjusted to 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ . Subsequently, a second doping process is performed, and boron (B) is added as an impurity element for imparting p-type, so that the boron concentration of the impurity regions 26 and 27 becomes 1 × 10
^{It was} adjusted to ²⁰ to 1 × 10 ²² / cm ³ . However, as shown in FIG. 1D, in the second doping process, the semiconductor layer forming the n-channel TFT is covered with a resist mask 25.

Next, a metal element is added to form a metal-containing layer 28. As the metal element, there is a metal element such as nickel, palladium, or lead,
As a method of addition, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. In this example, a solution containing nickel was held in the semiconductor layer and the conductive layer.

Next, as shown in FIG. 1E, crystallization of the semiconductor layer and activation of impurity elements are performed by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace or a rapid thermal annealing method (R
TA method). In the crystallization, crystal growth is performed using a metal element selectively added to the semiconductor layer as a nucleus, and crystal growth is performed in a lateral direction also in a channel formation region where the metal element is not added. In this embodiment, the heat treatment was performed at a temperature of 550 degrees for 4 hours.

FIG. 1F is a view for explaining a step of irradiating a laser beam to improve the crystallinity of the semiconductor layer.
The optimum conditions vary depending on the substrate used, the thickness of the base insulating film, and the like. First, a laser oscillator used in the laser annealing method will be described. For example, an excimer laser has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. Further, not only a pulse oscillation excimer laser but also a continuous oscillation excimer laser or other pulse oscillation or continuous oscillation gas laser or solid laser can be used. For example, as a gas laser, an Ar laser, Kr
There are lasers and the like.
VO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, T
i: A sapphire laser or the like can also be used. Of course, a harmonic converted by the nonlinear element may be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, when irradiating a laser beam, the substrate may be heated to about 500 degrees. By doing so, a decrease in the outflow rate of heat in the semiconductor film is expected, and the grain size of the crystal grains can be increased.

In this embodiment, the laser beam was irradiated in the atmosphere using the second harmonic (wavelength: 532 nm) of the YAG laser. In this embodiment, 1737 is used as the substrate.
A glass substrate is used, and from FIG. 2B, the transmittance of the YAG laser to the second harmonic is 90% or more. Therefore, the second harmonic of the YAG laser sufficiently passes through the substrate. Further, in the present embodiment, TaN is used for the conductive layers 17 and 18, and has no transparency to the second harmonic of the YAG laser. Therefore, in this embodiment, the semiconductor film was crystallized by irradiating a laser beam from the back surface side of the substrate.

The crystalline semiconductor layer formed by irradiating a laser beam is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% of hydrogen, or an atmosphere containing hydrogen generated by plasma. 200 ~ 450 ℃
The remaining heat can be reduced by the heat treatment.

By manufacturing a TFT using the crystalline semiconductor layer manufactured as described above, the electrical characteristics of the TFT can be improved.

Embodiment 2 In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

In FIG. 1A, a glass substrate such as a non-alkali glass such as a synthetic quartz glass substrate and a barium borosilicate glass aluminoborosilicate glass may be used as the substrate 300. For example, Corning 705
Nine glass, 1737 glass, or the like can be preferably used. In this example, a 1737 glass substrate was used.

Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, SiH ₄ , N 2
The silicon oxynitride film 301a formed by using H ₃ and N ₂ O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 10 nm).
0 nm). In this embodiment, a 50 nm-thick silicon oxynitride film 301a (composition ratio: Si = 32%, O = 27%,
N = 24%, H = 17%). Next, as a second layer of the base film 301, a plasma CVD
A silicon oxynitride film 301b formed by using iH ₄ and N ₂ O as a reaction gas has a thickness of 50 to 200 nm (preferably 100 nm).
(About 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 401b (composition ratio Si =
32%, O = 59%, N = 7%, H = 2%).

Next, a semiconductor film 302 is formed on the base film by a known means (sputtering, LPCVD, plasma C
10 to 200 nm (preferably 30 to
After forming a film with a thickness of 100 nm), the semiconductor layers 402 to 406 are formed by patterning into a desired shape. Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or a silicon germanium (SiGe) alloy. In this embodiment, after forming an amorphous silicon film with a thickness of 55 nm using a plasma CVD method, the semiconductor layers 402 to 406 are formed by patterning using a photolithography method.

After the formation of the semiconductor layers 402 to 406, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, as shown in FIG. 4B, a first conductive film 408 having a thickness of 20 to 100 nm and a second conductive film 40 having a thickness of 100 to 400 nm are formed on the gate insulating film 407.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 408 made of an aN film and a film thickness of 370 nm
A second conductive film 409 made of a W film was laminated. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking into consideration that impurities from the gas phase are not mixed during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408 is used.
Is TaN, and the second conductive film 409 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Cu, Cr,
It may be formed of an element selected from Nd, or an alloy material or a compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. AgPdCu
An alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; Are combined with a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. Alternatively, a combination of the second conductive film and the Cu film may be used.

Next, masks 410 to 415 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow ratio was 2
At 5:25:10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Thereafter, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30:30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first-shaped conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422) formed of the first conductive layer and the second conductive layer by the first etching process.
2b) is formed. 416 is a gate insulating film,
The region not covered by the conductive layers 417 to 422 having the
A region that is etched and thinned by about 50 nm is formed.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type is added to the semiconductor layer. (FIG. 5A) Doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ^{13 to} 5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 60 to ¹
The operation is performed at 00 keV. In this embodiment, the dose is set to 1.
The test was performed at 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 417 to 421 serve as a mask for the impurity element imparting n-type, and are self-aligned in the first high-concentration impurity region 3.
06 to 310 are formed. First high concentration impurity region 3
An impurity element imparting n-type is added to the layers 06 to 310 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Next, a second etching process is performed without removing the resist mask. Here, the W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as} an etching gas. At this time, second conductive layers 428b to 433b are formed by a second etching process. on the other hand,
The first conductive layers 417a to 422a are hardly etched to form second shape conductive layers 428 to 433.

Next, as shown in FIG. 5C, a second doping process is performed without removing the resist mask. In this case, the dose is lower than that of the first doping process, and at a high acceleration voltage of 70 to 120 keV,
An impurity element imparting n-type is introduced. In this embodiment, the dose is 1.5 × 10 ¹⁴ / cm ² and the acceleration voltage is 90
The operation is performed at keV, and a new impurity region is formed in the semiconductor layer inside the first high-concentration impurity regions 306 to 310 formed in FIG. The second doping process uses the second shape conductive layers 428 to 433 as a mask,
The impurity element is also introduced into the semiconductor layer below the second conductive layers 428b to 433b, and the second high concentration impurity regions 423a to 427a and the low concentration impurity regions 42 are newly added.
3b to 427b are formed.

Next, after removing the resist mask, new masks 434a and 434a are formed.
34b is formed, and a third etching process is performed as shown in FIG. SF ₆ and Cl ₂ were used as etching gases, and the gas flow ratio was 50/10 (scc
m) and a pressure of 1.3 Pa and 500
An RF (13.56 MHz) power of W is applied to generate plasma, and an etching process is performed for about 30 seconds. 10 W RF (13.56 MH) on the substrate side (data stage)
z) Turn on the power and apply a substantially non-self bias voltage. Thus, the p-channel type TFT and the TFT (pixel T
The TaN film (FT) is etched to form third shape conductive layers 435 to 438.

Next, after removing the resist mask, the gate insulating film 416 is selectively removed using the second shape conductive layers 428 and 430 and the second shape conductive layers 435 to 438 as masks. Insulating layers 439-44
4 is formed. (FIG. 6 (B))

Next, a mask 4 made of a new resist
45a to 445c are formed and a third doping process is performed. By the third doping treatment, the impurity region 4 in which the impurity element imparting the conductivity type opposite to the one conductivity type is added to the semiconductor layer serving as the active layer of the p-channel TFT.
46 and 447 are formed. Second conductive layers 435a, 43
8a is used as a mask for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 446 and 447 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 6C) In the third doping process, the semiconductor layers forming the n-channel TFT are covered with resist masks 445a to 445c. Phosphorus is added at different concentrations to the impurity regions 446 and 447 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is set to 2 × in each of the regions. 10 ^{20 to} 2 ×
By performing the doping treatment so that the concentration becomes 10 ²¹ atoms / cm ³ , no problem arises because the p-channel TFT functions as a source region and a drain region. In this embodiment, since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, a mask 445a made of resist is used.
445c are removed and a metal element is added to form a metal-containing layer 361. Examples of the metal element include metal elements such as nickel, palladium, and lead, and the method of addition may be a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like. In this example, a solution containing nickel was held in the semiconductor layer and the conductive layer.

Next, as shown in FIG. 7A, crystallization of the semiconductor layer and activation of impurity elements are performed by heat treatment. This activation step is performed by a thermal annealing method using a furnace annealing furnace or a rapid thermal annealing method (RTA method). As the thermal annealing method, an oxygen concentration of 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 55 ° C.
The activation may be performed at 0 ° C., and in this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours.

FIG. 7B is a view for explaining a step of irradiating a laser beam to improve the crystallinity of the semiconductor layer.
The optimum conditions vary depending on the substrate used, the thickness of the base insulating film, and the like. First, a laser oscillator used in the laser annealing method will be described. For example, an excimer laser has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to the pulsed excimer laser,
A continuous wave excimer laser or another pulsed or continuous wave gas laser or solid laser can be used. For example, gas lasers include an Ar laser and a Kr laser, and solid-state lasers include a YAG laser and a YVO laser.
₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti:
A sapphire laser or the like can also be used. of course,
A harmonic converted by a nonlinear element may be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, when irradiating a laser beam, the substrate may be heated to about 500 degrees.
By doing so, a decrease in the outflow rate of heat in the semiconductor film is expected, and the grain size of the crystal grains can be increased.

In this embodiment, laser beam irradiation was performed in the air using the second harmonic (wavelength 532 nm) of the YAG laser. In this embodiment, 1737 is used as the substrate.
A glass substrate is used, and from FIG. 2B, the transmittance of the YAG laser to the second harmonic is 90% or more. Therefore, the second harmonic of the YAG laser sufficiently passes through the substrate. In this embodiment, the conductive layers 428, 430, 43
5, 436, 437, and 438 are made of TaN and W, and have no transparency to the second harmonic of the YAG laser. Therefore, in this embodiment, the semiconductor film was crystallized by irradiating a laser beam from the back surface side of the substrate.

Next, a first interlayer insulating film 461 is formed. As the first interlayer insulating film 461, plasma C
Using a VD method or a sputtering method, a thickness of 100 to 200
The insulating film containing silicon is formed as nm. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 461
Is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Then, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to perform a step of hydrogenating the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a second interlayer insulating film 462 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm
Was formed, but the viscosity was 10 to 1000
cp, preferably 40 to 200 cp, and those having irregularities on the surface were used.

In this embodiment, in order to prevent specular reflection, irregularities are formed on the surface of the pixel electrode by forming a second interlayer insulating film having irregularities on the surface. In addition, a projection may be formed in a region below the pixel electrode in order to obtain light scattering by providing unevenness on the surface of the pixel electrode. In that case, the projection can be formed using the same photomask as that for forming the TFT, so that the projection can be formed without increasing the number of steps. Note that the protrusions may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, irregularities are formed on the surface of the pixel electrode along irregularities formed on the surface of the insulating film covering the convex portions.

A film whose surface is flattened may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, the surface is made uneven by adding a process such as a known sand blasting method or an etching method to prevent specular reflection and increase whiteness by scattering reflected light. Is preferred.

In the drive circuit 506, wirings 463 to 467 electrically connected to the respective impurity regions.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 7B) With this connection electrode 468, the source wiring (the lamination of 443b and 449) is electrically connected to the pixel TFT. Further, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. The pixel electrode 470 is connected to the drain region 44 of the pixel TFT.
2 and an electrical connection is formed with the semiconductor layer 458 functioning as one electrode forming a storage capacitor. The pixel electrode 471 has A
It is desirable to use a material having excellent reflectivity, such as a film containing l or Ag as a main component or a laminated film thereof.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
And driving circuit 506 having n-channel TFT 503
And a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the driving circuit 506
1 includes a channel formation region 423c, a low-concentration impurity region 423b (a GOLD region) overlapping with a first conductive layer 428a which forms part of a gate electrode, and a high-concentration impurity region 423a functioning as a source or drain region. ing. A p-channel TFT 5 connected to the n-channel TFT 501 via an electrode 466 to form a CMOS circuit
02 has a channel formation region 446d, impurity regions 446b and 446c formed outside the gate electrode, and a high-concentration impurity region 446a functioning as a source region or a drain region. Also, an n-channel TFT 50
3 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) overlapping with the first conductive layer 430a which forms part of the gate electrode, and a high-concentration impurity region 425a functioning as a source or drain region. are doing.

The pixel TFT 504 in the pixel portion has a channel forming region 426c, a low concentration impurity region 426b (LDD region) formed outside the gate electrode, and a high concentration impurity region 426a functioning as a source or drain region.
have. The semiconductor layers 447a and 447b functioning as one electrode of the storage capacitor 505 are each doped with an impurity element imparting p-type. The storage capacitor 505 includes an electrode (438) using the insulating film 444 as a dielectric.
a and 438b), and the semiconductor layers 447a to 447c.
And formed.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 8 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. FIG.
7 are denoted by the same reference numerals. FIG.
The chain line AA ′ in FIG. 8 corresponds to the cross-sectional view taken along the line AA ′ in FIG. 7 corresponds to a cross-sectional view taken along a dashed line BB ′ in FIG.

[Embodiment 3] In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 2 will be described below. FIG. 9 is used for the description.

First, after obtaining the active matrix substrate in the state shown in FIG. 7 according to the second embodiment, the alignment film 4 is formed on at least the pixel electrode 470 on the active matrix substrate shown in FIG.
A rubbing process is performed after forming 71. In this embodiment, before forming the alignment film 471, a columnar spacer (not shown) for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 471 is prepared. Next, coloring layers 472 and 473 and a planarizing film 474 are formed over the counter substrate 471. The red coloring layer 472 and the blue coloring layer 473 are overlapped to form a light-shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in the second embodiment is used. Therefore, FIG. 8 shows a top view of the pixel portion of the second embodiment.
Then, at least a gap between the gate wiring 469 and the pixel electrode 470, a gap between the gate wiring 469 and the connection electrode 468,
It is necessary to shield the gap between the connection electrode 468 and the pixel electrode 470 from light. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion composed of the stacked colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 475 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 474, an alignment film 476 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 477.
Paste in. A filler is mixed in the sealing material 477, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 478 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 478. Thus, the reflection type liquid crystal display device shown in FIG. 9 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display unit of various electronic devices.

This embodiment corresponds to the first embodiment or the second embodiment.
And can be freely combined.

[Embodiment 4] In this embodiment, a TFT for manufacturing the active matrix substrate shown in Embodiment 2 is used.
EL (Electroluminescence)
An example in which a display device is manufactured will be described. Note that FIG.
1 is a cross-sectional view of an EL display device according to the present invention.

In this specification, an EL display device refers to a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which a TFT is mounted on the display panel. It is a generic term. In addition,
The light-emitting element has a layer (light-emitting layer) containing an organic compound capable of obtaining luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. Also,
Luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state. Light emission.

In FIG. 10, the switching TFT 603 provided on the substrate 700 is an n-channel type TFT shown in FIG.
It is formed using FT503. Therefore, for the description of the structure, the description of the n-channel TFT 503 may be referred to.

Although the present embodiment has a double gate structure in which two channel forming regions are formed, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed. good.

The driving circuit provided on the substrate 700 is shown in FIG.
0 CMOS circuit. Therefore, the description of the structure is made of the n-channel TFT 501 and the p-channel TFT
Reference may be made to the description of 502. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of a CMOS circuit, and the wiring 702 functions as a drain wiring.
The wiring 704 is connected to the source wiring 708 and the switching T
The wiring 705 functions as a wiring for electrically connecting the source region of the FT to the source region.
It functions as a wiring for electrically connecting the drain region of the FT.

The current control TFT 604 corresponds to p
It is formed using a channel type TFT 502. Therefore,
For the description of the structure, the description of the p-channel TFT 502 can be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and 707 is an electrode which is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Reference numeral 710 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, carbon particles or metal particles are added to the insulating film that is a material of the bank 712 to lower the resistivity and suppress generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

On the pixel electrode 710, an EL layer 713 is formed. Although only one pixel is shown in FIG. 10, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic EL material that can be used as the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials. However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example is shown in which a low-molecular organic EL material is used as the EL layer, but a medium-molecular organic EL material or a high-molecular organic EL material may be used. Note that in this specification, an organic EL material having no sublimability and having a molecular number of 20 or less or a chain of molecules having a length of 10 μm or less is defined as a medium molecular organic EL material. As an example using a polymer organic EL material, a 20 nm polythiophene (PEDOT) film is provided as a hole injection layer by a spin coating method, and a 100 nm paraphenylene vinylene (PPV) film is provided thereon as an EL layer. A stacked structure may be used. When a π-conjugated polymer of PPV is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, the EL
The element 715 is completed. Note that the EL element 71 here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (anode) 710, the EL layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, in particular, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the EL layer 713
Can be suppressed. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.

Furthermore, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, an EL display device having a structure as shown in FIG. 10 is completed. After forming the bank 712,
It is effective to perform a process up to the formation of the passivation film 716 continuously without exposing to the atmosphere using a multi-chamber (or in-line) film forming apparatus. Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601, 602,
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
The number is smaller than that of a general active matrix type EL display device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG.
By providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, n is resistant to deterioration caused by the hot carrier effect.
A channel type TFT can be formed. for that reason,
A highly reliable EL display device can be realized.

In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, and a gamma correction circuit are also provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the EL light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the EL element will be described with reference to FIG. It should be noted that the reference numerals used in FIG.

FIG. 11A is a top view showing a state in which the process up to the sealing of the EL element has been performed, and FIG.
It is sectional drawing cut | disconnected by CC '. 801 shown by dotted line
Denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material, 902 denotes a first seal material, and 903 denotes a second seal material. A sealing material 907 is provided inside the first seal material 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side driving circuit 801 and the gate-side driving circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The EL display device in this specification includes not only the EL display device main body but also a state in which an FPC or a PWB is attached thereto.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 14) in which T601 and p-channel TFT 602 are combined.

The pixel electrode 710 functions as an anode of the EL element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and an EL layer 713 and a cathode 714 of an EL element are formed on the pixel electrode 710.

The cathode 714 also functions as a common wiring for all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, a cover member 901 is attached by a first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the EL element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0124] The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

Further, the cover material 90 is formed by using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the EL element is sealed with the sealing material 90.
By encapsulating the EL element in the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes the deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable EL display device can be obtained.

This embodiment corresponds to the first embodiment or the second embodiment.
And can be freely combined.

[Embodiment 5] A CMOS circuit and a pixel portion formed by carrying out the present invention can be used for various semiconductor devices (active matrix type liquid crystal display, active matrix type EC display, active matrix type EL display). I can do it. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 12, 13 and 14.

FIG. 12A shows a personal computer, which includes a main body 3001, an image input section 3002, and a display section 30.
03, a keyboard 3004 and the like. The present invention can be applied to the image input unit 3002, the display unit 3003, and other signal control circuits.

FIG. 12B shows a video camera, which includes a main body 3101, a display portion 3102, a voice input portion 3103, operation switches 3104, a battery 3105, and an image receiving portion 310.
6 and so on. The present invention can be applied to the display portion 3102 and other signal control circuits.

FIG. 12C shows a mobile computer (mobile computer) including a main body 3201, a camera section 3202, an image receiving section 3203, operation switches 3204, a display section 3205, and the like. The present invention can be applied to the display portion 3205 and other signal control circuits.

FIG. 12D shows a goggle type display, which comprises a main body 3301, a display section 3302, and an arm section 330.
3 and so on. The present invention can be applied to the display portion 3302 and other signal control circuits.

FIG. 12E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, and a speaker portion 340.
3, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402 and other signal control circuits.

FIG. 12F shows a digital camera, which includes a main body 3501, a display section 3502, an eyepiece section 3503, operation switches 3504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 3502 and other signal control circuits.

FIG. 13A shows a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 3601 and other signal control circuits.

FIG. 13B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3, including a screen 3704 and the like. The present invention provides a projection device 3
The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the signal control circuit 702 and other signal control circuits.

FIG. 13C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 13A and 13B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 13D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 13C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 13D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 13, a case where a transmission type electro-optical device is used is shown, and an example of application to a reflection type electro-optical device is not shown.

FIG. 14A shows a portable telephone, and the main body 39 is shown.
01, audio output unit 3902, audio input unit 3903, display unit 3904, operation switch 3905, antenna 3906
And so on. The present invention is applied to the audio output unit 3902 and the audio input unit 3
903, the display portion 3904, and other signal control circuits.

FIG. 14B shows a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, and an antenna 4006.
And so on. The present invention can be applied to the display portions 4002 and 4003 and other signal circuits.

FIG. 14C shows a display, which includes a main body 4101, a support 4102, a display portion 4103, and the like.
The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the configurations of the first to fourth embodiments.

[0145]

By adopting the configuration of the present invention, the following basic significance can be obtained. (A) A simple structure suitable for a conventional TFT manufacturing process. (B) For positioning the slits and the like, the laser irradiation device does not require a special precise positioning technique on the order of microns, and an ordinary laser irradiation device can be used as it is. (C) This is a method capable of manufacturing a semiconductor layer with good crystallinity while satisfying the above advantages.

[Brief description of the drawings]

FIG. 1 illustrates an example of a method for manufacturing a TFT disclosed in the present invention.

FIG. 2 is a diagram showing an example of transmittance of a substrate with respect to wavelength.

FIG. 3 is a diagram showing an example of a conventional technique.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a top view illustrating a configuration of a pixel TFT.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 10 is a cross-sectional structural view of a driver circuit and a pixel portion of an EL display device.

FIG. 11A is a top view of an EL display device. FIG. 2B is a cross-sectional structural view of a driver circuit and a pixel portion of an EL display device.

FIG. 12 illustrates an example of a semiconductor device.

FIG. 13 illustrates an example of a semiconductor device.

FIG. 14 illustrates an example of a semiconductor device.

Continued on the front page F term (reference) 2H092 JA25 JA28 JA34 JA37 MA30 NA05 5C094 AA43 AA45 BA03 BA29 BA43 CA19 DA14 DA15 DB01 DB04 EA04 EA07 5F052 AA02 AA11 AA17 AA24 BA07 BB01 BB02 BB03 BB05 FA01 DB01 FA03 BB02 BB04 BB05 CC02 DD01 DD02 DD03 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE07 EE09 EE14 EE23 EE44 EE45 FF02 FF04 FF09 FF28 FF30 NN01 NN02 GG23 GG43 GG01 NN73 PP01 PP02 PP03 PP04 PP10 PP13 PP24 PP27 PP29 PP34 PP40 QQ04 QQ10 QQ11 QQ19 QQ24 QQ25 QQ28

Claims (13)

[Claims] 1. A semiconductor layer is formed on a surface of a substrate, an insulating film is formed on the semiconductor layer, a gate electrode is formed on the insulating film, and an impurity element is formed on the semiconductor layer using the gate electrode as a mask. Is introduced, a metal element is selectively introduced into the semiconductor layer into which the impurity element is introduced, crystallization of the semiconductor layer and activation of the impurity element are performed by heat treatment, and a laser beam is applied to the semiconductor layer. A method for manufacturing a semiconductor device, which includes irradiation. 2. A semiconductor layer is formed on a surface of a substrate, an insulating film is formed on the semiconductor layer, a gate electrode is formed on the insulating film, and an impurity element is formed on the semiconductor layer using the gate electrode as a mask. Is introduced, a metal element is selectively introduced into the semiconductor layer into which the impurity element has been introduced, and crystallization of the semiconductor layer and activation of the impurity element are performed by a first heat treatment. The semiconductor layer is irradiated with a laser beam using the gate electrode as a mask.
A method for manufacturing a semiconductor device, comprising introducing an element belonging to Group 15 and performing a second heat treatment to getter the metal element to a region where the element belonging to Group 15 is introduced. 3. The method according to claim 1, wherein the metal element is Fe, Co, Ni, Ru, Rh, Pd, O
s, Ir, Pt, Cu, Ag, Au, Al, In, S
A method for manufacturing a semiconductor device, which is one or more elements selected from n, Pb, P, As, and Sb. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element is an n-type impurity element or a p-type impurity element. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the laser beam is a laser beam oscillated from a pulsed or continuous oscillation gas laser or solid laser. 6. The method according to claim 1, wherein said first or second means is selected.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the laser beam is a laser beam oscillated from one selected from a pulse oscillation or a continuous oscillation excimer laser, an Ar laser, and a Kr laser. 7. The method according to claim 1, wherein the first and second steps are performed.
In the above, the laser beam may be a pulse oscillation or continuous oscillation YAG laser, a YVO ₄ laser, a YLF laser,
A method for manufacturing a semiconductor device, comprising a laser beam oscillated from one selected from a YAlO ₃ laser, a glass laser, a ruby laser, an alexandrite laser, and Ti: sapphire laser. 8. The first, second and fifth aspects
The laser beam according to any one of claims 1 to 7,
A method for manufacturing a semiconductor device, wherein irradiation is performed from a front surface side of a substrate. 9. The method according to claim 1, 2 or 5, wherein
The laser beam according to any one of claims 1 to 7,
A method for manufacturing a semiconductor device, wherein irradiation is performed from the back side of a substrate. 10. The semiconductor device according to claim 1, wherein the laser beam is emitted from both the front surface side and the back surface side of the substrate. Production method. 11. The method for manufacturing a semiconductor device according to claim 1, wherein a part of the laser beam is transmitted through the gate electrode. 12. The semiconductor device according to claim 1, wherein a part of the laser beam is transmitted through the substrate. Production method. 13. The method according to claim 1, wherein a part of the laser beam is transmitted through the substrate or the gate electrode. Of manufacturing a semiconductor device.