JP2010177668A - Flat display, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flat display and a manufacturing method of the display. <P>SOLUTION: The flat display includes a substrate; a TFT active layer; a first lower electrode of a capacitor; a first upper electrode of the capacitor formed on the first lower electrode; a first insulating layer; a gate lower and upper layers formed on the region, corresponding to a channel region sequentially; a second lower electrode and an upper electrode of a capacitor which are formed sequentially in the region corresponding to a first upper electrode of the capacitor; a pixel lower electrode; a pixel upper electrode disposed in the upper portion of a pixel lower-electrode edge so as to expose the lower pixel electrode; contact holes for exposing source and drain regions of an active layer; a second insulating layer pierced by a via hole for exposing a portion of an pixel upper-electrode edge; and source and drain electrodes formed on the second insulating layer which are connected with source and drain regions and the pixel upper-electrode via the contact holes and the via hole. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a flat panel display device and a manufacturing method thereof, and more particularly, to a flat panel display device having a simplified manufacturing process and excellent display quality, and a manufacturing method thereof.

  2. Description of the Related Art A flat panel display device such as an organic light emitting display (OLED) or a liquid crystal display (LCD) includes a thin film transistor (TFT), a capacitor, and a pattern including a wiring connecting the capacitors. Are fabricated on the substrate formed.

  In general, a substrate on which a flat panel display device is manufactured uses a mask on which a fine pattern is drawn to transfer a pattern to the array substrate in order to form a fine pattern having TFTs. .

  Thus, the process of transferring a pattern using a mask generally uses a photolithography process. According to the photolithography process, a photoresist is uniformly applied on a substrate on which a pattern is to be formed, and the photoresist is exposed with an exposure device such as a stepper, and then the exposed photoresist is applied (in the case of a positive photoresist). Through the process of developing. Further, after developing the photoresist, a pattern is etched using the remaining photoresist as a mask, and a series of processes for removing unnecessary photoresist is performed.

  Thus, in the process of transferring a pattern using a mask, first, a mask having a necessary pattern must be prepared. Therefore, as the number of processes using a mask increases, the manufacturing cost for mask preparation increases. . In addition, since the above-described complicated process must be performed, the manufacturing process is complicated, and there is a problem that the manufacturing time is extended and the manufacturing cost is increased.

  The problem to be solved by the present invention is to provide a flat panel display device excellent in display quality and a manufacturing method thereof by reducing a patterning process using a mask.

  In order to achieve the above object, the present invention includes a substrate, a TFT active layer having a channel region, a source and a drain region formed in the same layer on the substrate, and the same material as the active layer, A first lower electrode of the capacitor formed on the same layer as the active layer and spaced apart by a predetermined distance, a first upper electrode of the capacitor formed on the first lower electrode, the substrate, the active layer, and the first upper electrode A first insulating layer formed thereon, a gate lower electrode and a gate upper electrode formed on the first insulating layer and sequentially formed in a region corresponding to the channel region; and on the first insulating layer. A second lower electrode and an upper electrode of the capacitor, which are formed of the same material as each of the gate lower electrode and the upper electrode and sequentially formed in a region corresponding to the first upper electrode of the capacitor; A pixel lower electrode formed on the edge layer and formed of the same material as the gate lower electrode and the capacitor second lower electrode; and a pixel lower electrode formed of the same material as the gate upper electrode and the capacitor second upper electrode; A pixel upper electrode disposed on the edge of the pixel lower electrode to expose the lower electrode, and the gate electrode, the capacitor second electrode, and the pixel upper electrode, and the source and drain regions of the active layer are formed on the pixel upper electrode. A contact hole to be exposed, a second insulating layer that is penetrated by a via hole that exposes a part of the edge of the pixel upper electrode, and the source and drain regions formed on the second insulating layer and through the contact hole and the via hole. And a source and drain electrode connected to the pixel upper electrode.

  The present invention also provides a TFT active layer including a substrate, a channel region formed on the substrate, and a source and drain region formed at an upper edge of the channel region, and the channel region of the active layer. The capacitor is formed of the same material as the first and lower electrodes of the capacitor and the source and drain electrodes, and is formed on the same layer as the channel region and spaced apart from the active layer by a predetermined distance. A first upper electrode of the capacitor formed on the substrate, a first insulating layer formed on the substrate, the active layer and the first upper electrode, and a region formed on the first insulating layer and corresponding to the channel region A gate lower electrode and a gate upper electrode sequentially formed on the first insulating layer, and the same material as each of the gate lower electrode and the upper electrode, A second lower electrode and an upper electrode of a capacitor sequentially formed in a region corresponding to the first upper electrode of the capacitor; and formed on the first insulating layer and the same as the gate lower electrode and the capacitor second lower electrode. The pixel lower electrode is formed of the same material as the gate upper electrode and the capacitor second upper electrode, and is disposed on the edge of the pixel lower electrode so as to expose the pixel lower electrode. A pixel upper electrode, a contact hole formed on the gate electrode, the capacitor second electrode, and the pixel upper electrode, exposing the source and drain regions of the active layer, and a via hole exposing a part of the edge of the pixel upper electrode. A second insulating layer penetrating through the second insulating layer, and formed on the second insulating layer, through the contact hole and the via hole, Over scan, to provide a flat panel display device having a source and a drain electrode connected to the drain region and the pixel top electrode.

  The present invention includes a step of sequentially depositing a semiconductor layer and a first conductive layer on a substrate, a semiconductor layer and a first conductive layer as a first mask step, an active layer of a TFT, a first lower electrode of a capacitor, A process of simultaneously patterning the upper electrode, a process of forming a first insulating layer on the structure of the first mask process, and sequentially forming a second conductive layer and a third conductive layer on the first insulating layer A second mask layer, a gate lower electrode and an upper electrode of a TFT, a second lower electrode and a second upper electrode of a capacitor, a pixel lower electrode, Patterning simultaneously with the upper electrode; forming a source and drain region at an edge of the TFT active layer using the gate lower electrode and the upper electrode as a self-alignment mask; and the second mask. Forming a second insulating layer on the structure of the process; and, as a third mask process, the second insulation so that a part of the source and drain regions and a part of the edge of the pixel upper electrode are exposed. A step of patterning a layer, a step of forming a fourth conductive layer on the structure of the third mask step, a step of patterning the fourth conductive layer on the source and drain electrodes of the TFT as a fourth mask step, Forming a third insulating layer on the structure in the fourth mask process; and removing the second insulating layer and the third insulating layer so that the pixel upper electrode is exposed in the fifth mask process. And a method of manufacturing a flat panel display device.

  According to another aspect of the present invention, a semiconductor layer and a first conductive layer are sequentially deposited on a substrate, and the semiconductor layer and the first conductive layer are formed as a first mask process. The TFT includes a channel region, a source region, and a drain region. Simultaneously patterning the active layer and the first lower electrode and the upper electrode of the capacitor; forming a first insulating layer on the structure of the first mask step; and second forming a second insulating layer on the first insulating layer. A step of sequentially forming a conductive layer and a third conductive layer, and a second mask layer, a gate lower electrode and an upper electrode of a TFT, and a capacitor second lower electrode as a second mask step, respectively. And patterning the second upper electrode, the pixel lower electrode and the upper electrode at the same time, forming a second insulating layer on the structure in the second mask process, and the third mask process as the third mask process. And patterning the second insulating layer so that part of the drain region and part of the edge of the pixel upper electrode are exposed, and forming a fourth conductive layer on the structure in the third mask process. A step of patterning the fourth conductive layer on the source and drain electrodes of the TFT as a fourth mask step, a step of forming a third insulating layer on the structure of the fourth mask step, and a fifth mask And a step of removing the second insulating layer and the third insulating layer so that the pixel upper electrode is exposed as a step.

  According to the flat panel display device and the method of manufacturing the same of the present invention, the display device can be manufactured using a minimum halftone mask process while reducing the total number of masks. Reduced cost, reduced cost for minimal halftone process, and simplified manufacturing process.

FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a second mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a second mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a second mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a second mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a third mask process of the flat panel display according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a manufacturing process by a third mask process of the flat panel display according to the first embodiment of the present invention. It is sectional drawing which shows schematically the manufacturing process by the 4th mask process of the flat panel display by 1st Example of this invention. It is sectional drawing which shows schematically the manufacturing process by the 4th mask process of the flat panel display by 1st Example of this invention. It is sectional drawing which shows schematically the manufacturing process by the 5th mask process of the flat panel display by 1st Example of this invention. It is sectional drawing which shows schematically the manufacturing process by the 5th mask process of the flat panel display by 1st Example of this invention. 1 is a schematic cross-sectional view of a flat panel display according to a first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a flat panel display according to a modification of the first embodiment of the present invention. FIG. 10 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of a flat panel display according to a second embodiment of the present invention. FIG. 10 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of a flat panel display according to a second embodiment of the present invention. FIG. 10 is a cross-sectional view schematically illustrating a manufacturing process by a first mask process of a flat panel display according to a second embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a flat panel display according to a second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a flat panel display according to a modification of the second embodiment of the present invention.

  Hereinafter, the present invention will be described in more detail with reference to the preferred embodiments of the present invention shown in the accompanying drawings.

  First, a flat panel display according to a first embodiment of the present invention will be described with reference to FIGS.

  1 to 15 are cross-sectional views schematically illustrating a manufacturing process of a flat panel display according to the present embodiment. FIG. 16 is an organic light emitting diode (OLED) formed by the manufacturing process. It is sectional drawing which showed schematically.

  Referring to FIG. 16, the OLED 1 according to the present embodiment includes a substrate 10, a buffer layer 11, a TFT (Thin Film Transistor) 2, a capacitor 3, and an organic light emitting device 4.

  First, referring to FIG. 1, a buffer layer 11, a semiconductor layer 12, and a first conductive layer 13 are sequentially formed on a substrate 10.

Substrate 10 may be formed by of a transparent glass material mainly composed of SiO _2. Of course, opaque materials are also possible and may be formed of other materials such as plastic materials. However, when the image of the OLED 1 is a back-emitting type embodied on the substrate 10 side, the substrate 10 must be formed of a transparent material.

A buffer layer 11 may be provided on the upper surface of the substrate 10 in order to block the smoothness of the substrate 10 and the impregnation of impure elements. The buffer layer 11 is formed by various deposition methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition), APCVD (Atmospheric Pressure CVD), LPCVD (Low Pressure CVD) using SiO ₂ and / or SiN _x . It can be deposited.

  The semiconductor layer 12 is made of polycrystalline silicon obtained by first depositing amorphous silicon and then crystallizing it. Amorphous silicon is formed by the RTA (Rapid Thermal Annealing) method, the SPC (Solid Phase Crystallization) method, the ELA (Excimer Laser Annealing) method, the MIC (Metal Induced Crystallization) method, the MILC (MeluCdSl et al. It can be crystallized by various methods such as a lateral solidification method.

  A first conductive layer 13 is deposited on the semiconductor layer 12. The first conductive layer 13 of this embodiment is formed by vapor deposition and heat treatment of amorphous silicon containing N-type or P-type impurities, but the present invention is not limited to this. Any conductive material containing a metal may be used.

  Referring to FIG. 2, after forming the photosensitive film P1 from which the solvent is removed by pre-baking or soft baking with respect to the photosensitive agent applied to the upper part of the structure of FIG. A first mask M1 on which a predetermined pattern is drawn is prepared and aligned with the substrate 10.

  The first mask M1 is a halftone mask that includes a light transmitting part M11, a light blocking part M12, and a semi-transmissive part M13. The light transmitting part M11 transmits light in a predetermined wavelength band, the light blocking part M12 blocks light to be irradiated, and the semi-transmissive part M13 allows only part of the irradiated light to pass through.

The halftone mask M1 shown in the drawing is a conceptual diagram for conceptually explaining the function of each part of the mask. Actually, the halftone mask M1 is made of quartz (Qz). A predetermined pattern may be formed on such a transparent substrate. At this time, the light blocking part M12 is formed by patterning a material such as Cr or CrO ₂ on the quartz substrate, and the semi-transmissive part M13 includes at least one of Cr, Si, Mo, Ta, and Al. By using a substance and adjusting the ratio or thickness of the composition components, the light transmittance can be adjusted.

  The first mask M1 on which the pattern as described above is drawn is aligned with the substrate 10, and exposure is performed by irradiating the photosensitive film P1 with light of a predetermined wavelength band.

  Referring to FIG. 3, the pattern of the remaining photosensitive film after the development process for removing the exposed portion of the photosensitive film P1 is schematically shown. In this embodiment, a positive photosensitive agent (Positive-PR) that removes the exposed portion is used. However, the present invention is not limited to this, and a negative photosensitive agent (Negative-PR) can also be used.

  Referring to the drawing, the photosensitive film part P11 corresponding to the light transmitting part M11 of the halftone mask M1 is removed, and the photosensitive film part P12 corresponding to the light blocking part M12 and the photosensitive film corresponding to the semi-transmissive part M13. Part P13 remains. At this time, the thickness of the photosensitive film portion P13 corresponding to the semi-transmissive portion M13 is smaller than the thickness of the photosensitive film portion P12 corresponding to the light blocking portion M12, and the thickness of the photosensitive film P13 is equal to the pattern of the semi-transmissive portion M13. It can be adjusted by the component ratio or thickness of the constituent substances.

  Using the photoresist pattern P12 as a mask, the semiconductor layer 12 and the first conductive layer 13 on the substrate 10 are etched using an etching equipment. At this time, the structure of the portion P11 having no photosensitive film is etched first, and the thickness of a part of the photosensitive film is etched. At this time, the etching process may be performed by various methods such as wet etching and dry etching.

  Referring to FIG. 4, during the primary etching process, the semiconductor layer 12 and the first conductive layer 13 of FIG. 3 in the portion P11 having no photosensitive film were etched. Then, although the photosensitive film portion P13 corresponding to the semi-transmissive portion M13 in FIG. 3 is etched, the lower structure remains as it is. On the other hand, a part of the photosensitive film portion P12 corresponding to the light blocking portion M12 remains even in the primary etching, and the secondary etching is advanced using this as a mask.

  Referring to FIG. 5, the first conductive layer 13 which is a part of the structure remaining in the region corresponding to the photosensitive film portion P12 and the semi-transmissive portion M13 remaining after the primary etching step by the secondary etching step. All were etched. The former becomes the first lower electrode 31-1 and the upper electrode 31-2 of the capacitor, and the latter becomes the active layer 21 of the TFT.

  Since the active layer 21 of the TFT and the first lower electrode 31-1 and the upper electrode 31-2 of the capacitor are simultaneously patterned on the same structure using the same mask M1, the active layer 21 of the TFT and the first electrode of the capacitor The first lower electrode 31-1 is made of the same material and is formed of the same layer. Further, since the patterning is simultaneously performed using the same mask M1, the shapes of the end portions formed by the first lower electrode 31-1 and the upper electrode 31-2 of the capacitor are the same.

  Referring to FIG. 6, a first insulating layer 14, a second conductive layer 15, and a third conductive layer 16 are sequentially deposited on the structure of FIG. After the second photosensitive film P2 is formed, the second mask M2 is aligned with the substrate 10.

The first insulating layer 14 can be formed by depositing an inorganic insulating film such as SiN _x or SiO _x by PECVD, APCVD, or LPCVD. A part of the first insulating layer 14 is interposed between the active layer 21 of the TFT and the gate lower electrode 21-1 to act as a gate insulating film of the TFT 2, and the first upper electrode 31-2 of the capacitor 3. It is interposed between the second lower electrode 32-1 and serves as a first dielectric layer of the capacitor 3.

The second conductive layer 15 may include one or more materials selected from transparent materials such as ITO, IZO, ZnO, or In ₂ O ₃ . Such a second conductive layer 15 becomes a pixel lower electrode 42-1 of a flat panel display device to be described later, a gate lower electrode 22-1 of a TFT, and a second lower electrode 32-1 of a capacitor. On the other hand, in the present embodiment, the second conductive layer 15 is formed as a single layer, but the present invention is not limited to this, and a multi-layered conductive material can be formed. That is, when the pixel electrode 42 is formed of only a transparent material as in this embodiment, the image can be used in a back-light-emitting display device implemented on the substrate 10 side, but the image is on the opposite side of the substrate 10. In the case of a front emission display device, the second conductive layer is formed in multiple layers, for example, a conductive material having a reflective property is first deposited, and then a transparent conductive material as in this embodiment is deposited. In this manner, the reflective film can be formed, and not only two layers but also more layers can be deposited if necessary.

  The third conductive layer 16 is one or more selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, and Al / Cu. The substance may be included. The third conductive layer 16 serves as a pixel upper electrode 42-2 of a flat panel display device, a TFT gate upper electrode 22-2, and a capacitor second upper electrode 32-2.

  The second mask M2 includes a translucent part M21 having a predetermined pattern and light blocking parts M22a, M22b, M22c. The second mask M2 on which the above pattern is drawn is aligned with the substrate 10, and the photosensitive film P2 is irradiated with light of a predetermined wavelength band.

  Referring to FIG. 7, the photosensitive film portion P21 corresponding to the light transmitting portion M21 of the second mask M2 is removed, and the photosensitive film portions P22a, P22b, and P22c corresponding to the light blocking portions M22a, M22b, and M22c are left. ing.

  Using the photosensitive film patterns P22a, P22b, and P22c as a mask, the second conductive layer 15 and the third conductive layer 16 on the substrate 10 are etched using an etching equipment. At this time, the etching process may be performed by various methods such as wet etching and dry etching.

  Referring to FIG. 8, the structure formed on the substrate 10 after the etching process by the second mask process is performed is shown. The second conductive layer 15 and the third conductive layer 16 in the portion P21 having no photosensitive film were etched. Of the portions P22a, P22b, and P22c where the photosensitive film remains, the gate electrode 22 is patterned so as to correspond to the intermediate region of the active layer 21 of the TFT. Using the pattern of the gate electrode 22 as a mask, the edge of the TFT active layer 21 is doped with N or P impurities.

  Referring to FIG. 9, the structure shape after the etching process and the ion doping process by the second mask process is shown.

  An active layer 21 of a TFT including source and drain regions 21a and 21b and a channel region 21c formed by ion doping, a gate electrode 22 having a two-layer structure formed at a position corresponding to the channel region 21c of the TFT, and a two-layer structure The first and second electrodes 31 and 32 of the capacitor and the pixel electrode 42 having a two-layer structure are formed.

  Referring to the drawing, since the pixel electrode 42 having the two-layer structure, the gate electrode 22 of the TFT, and the second electrode 32 of the capacitor are simultaneously patterned on the same structure using one mask M2, the pixel lower electrode 42-1, the TFT gate lower electrode 22-1, and the capacitor first lower electrode 32-1 are formed of the same material in the same layer. The pixel upper electrode 42-2, TFT gate upper electrode 22-2 and capacitor The first upper electrode 32-2 is formed of the same material in the same layer. Also, the end portions of the pixel lower electrode 42-1 and the pixel upper electrode 42-2, the end portions of the gate lower electrode 22-1 and the gate upper electrode 22-2, and the second lower electrode 32-1 and the second end of the capacitor. The respective shapes of the ends of the two upper electrodes 32-2 match.

  Referring to FIG. 10, a second insulating layer 17 is formed on the structure of FIG. 9 as a result of the second mask process, a third photosensitive film P3 is formed thereon, and then a third mask is formed on the substrate 10. Align M3.

  The second insulating layer 17 is formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin by a method such as spin coating. The second insulating layer 17 is formed to a sufficient thickness, for example, thicker than the first insulating layer 14 described above, and the interlayer insulation between the gate electrode 22 of the TFT and source / drain electrodes 24a and 24b described later. Play the role of membrane. Meanwhile, the second insulating layer 17 is formed of not only the organic insulating material as described above but also an inorganic insulating material such as the first insulating layer 14 described above, and alternately forms the organic insulating material and the inorganic insulating material. Sometimes.

  The third mask M3 includes a pattern of light transmissive portions M31a, M31b, M31c corresponding to a partial region of the source / drain regions 21a, 21b and a partial region of the edge of the pixel electrode 42, and a light blocking portion M32. The third mask M3 having the pattern as described above is aligned with the substrate 10, and the photosensitive film P3 is exposed.

  Referring to FIG. 11, a flat panel display device is schematically illustrated after the exposed photosensitive film P3 is removed and then etched using the remaining photosensitive film pattern as a mask. Openings 23a, 23b, and 23c that expose regions corresponding to partial regions of the source / drain regions 21a and 21b and partial regions of the edge of the pixel upper electrode 42-2 are formed. Of these openings 23a, 23b, and 23c, the openings 23a and 23b formed in partial regions of the source / drain regions 21a and 21b are so-called contact holes, and are one of the edges of the pixel upper electrode 42-2. The opening 24c formed in the region corresponding to the partial region is referred to as a via hole, but the idea of the present invention is not limited to such a name.

  Referring to FIG. 12, the fourth conductive layer 18 is formed on the structure of FIG. 11, which is the result of the third mask process, the fourth photosensitive film P <b> 4 is formed thereon, and then the fourth conductive layer 18 is formed on the substrate 10. The mask M4 is aligned.

  The fourth conductive layer 18 may be selected from conductive materials such as the second or third conductive layers 15 and 16 described above, and is not limited thereto, and may be formed of various conductive materials. The conductive material is deposited to a thickness sufficient to fill the openings 23a, 23b, and 23c.

  The fourth mask M4 includes a light transmitting part M41 and light blocking parts M42a and M42b. After exposing and developing the photosensitive film P4 using the mask M4 having such a pattern, an etching process is performed using the remaining photosensitive film pattern as a mask.

  Referring to FIG. 13, as a result of the fourth mask process, source / drain electrodes 24a and 24b connected to the source / drain regions 21a and 21b through the contact holes 23a and 23b are formed on the second insulating layer 17. . One of the source / drain electrodes 24a and 24b (in this embodiment) is connected to the pixel upper electrode 42-2 through a via hole 23c partially connected to the edge region of the pixel upper electrode 42-2. Formed to connect.

  Referring to FIG. 14, after the third insulating layer 19 is formed on the structure of FIG. 13 that is the result of the fourth mask process, the fifth mask M5 is aligned on the substrate 10.

  The third insulating layer 19 may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin by a method such as spin coating. On the other hand, the third insulating layer 19 may be formed of not only the organic insulating material as described above but also an inorganic insulating material such as the first insulating layer 14 and the second insulating layer 15 described above. The third insulating layer 19 serves as a pixel definition film (PDL: Pixel Define Layer) 43 of the OLED 1 described later after the etching process using the fifth mask M5.

  In the fifth mask M5, a light transmitting part M51 is formed at a position corresponding to the pixel electrode 42, and a light blocking part M52 is formed in the remaining part.

  Referring to FIG. 15, the second insulating layer 17, the third insulating layer 19, and the pixel upper electrode 42-2 in the region corresponding to the light transmitting part M51 are etched by the etching process of FIG. -1 is exposed. The second insulating layer 17 and the third insulating layer 19 are sequentially stacked on the edge of the pixel upper electrode 42-2 around the opening 44 formed in the etching process. At this time, the third insulating layer 19 formed to have a predetermined thickness along the opening 44 widens the distance between the edge of the pixel electrode 42 and a counter electrode 47 described later, and the electric field concentrates on the edge of the pixel electrode 42. By preventing this phenomenon, the PDL 43 serves to prevent a short circuit between the pixel electrode 42 and the counter electrode 47.

  Referring to FIG. 16, the intermediate layer 46 including the organic light emitting layer 45 and the counter electrode 47 are formed on the exposed pixel lower electrode 42-1 and the PDL 43.

  The organic light emitting layer 45 emits light by electrical driving of the pixel electrode 42 and the counter electrode 47. The organic light emitting layer 45 may be made of a low molecular or high molecular organic material.

  In the case of being formed of a low molecular organic material, the intermediate layer 46 is formed by laminating a hole transport layer (HTL) and a hole injection layer (HIL) in the direction of the pixel electrode 42 around the organic light emitting layer 45. Then, an electron transport layer (Electron Transport Layer: ETL) and an electron injection layer (Electron Injection Layer: EIL) are stacked in the direction of the counter electrode 47. In addition, various layers can be stacked as necessary. At this time, usable organic materials are copper phthalocyanine (CuPc), N, N-di (naphthalen-1-yl) -N, N′-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq3). It can be applied in a variety of ways.

  On the other hand, when formed of a polymer organic material, the intermediate layer 47 may be provided with only HTL in the direction of the pixel electrode 42 around the organic light emitting layer 45. The HTL can be formed on the pixel electrode 42 by inkjet printing or spin coating using polyethylene dihydroxythiophene (PEDOT) or polyaniline (PANI). At this time, high molecular organic materials such as PPV (Poly-Phenylene Vinylene) and polyfluorene can be used as usable organic materials, and a color pattern can be obtained by an ordinary method such as inkjet printing, spin coating, or thermal transfer using laser. Can be formed.

  On the intermediate layer 46 including the organic light emitting layer 45, a counter electrode 47 is deposited as a common electrode. In the case of the OLED 1 according to the present embodiment, the pixel electrode 42 is used as an anode electrode, and the common electrode 47 is used as a cathode electrode. Of course, the polarity of the electrodes can be applied in reverse.

  When the OLED 1 is of a rear emission type in which an image is embodied in the direction of the substrate 10, the pixel electrode 45 is a transparent electrode and the common electrode 47 is a reflective electrode. At this time, the reflective electrode is a metal having a small work function, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, or these Thin compounds can be deposited.

  Meanwhile, although not shown in the drawing, a sealing member (not shown) and a moisture absorbent (not shown) for protecting the organic light emitting layer 45 from external moisture and oxygen are provided on the common electrode 47. Further provided.

  Since the OLED and the manufacturing method thereof according to this embodiment described above can generally manufacture a display device using a small number of masks, the cost can be reduced by reducing the number of masks, and the manufacturing process can be simplified and the cost can be reduced. Reduction can be realized.

  On the other hand, even if a process of using a halftone mask is introduced to use a small number of masks as described above, the cost of using a halftone mask is increased because the halftone mask is used at a minimum (once). Can be minimized.

  Further, since the pixel electrode is protected by the second insulating layer and the third insulating layer until immediately before the organic light emitting layer is formed and is exposed immediately before the organic light emitting layer is formed, the subsequent process is performed with the pixel electrode exposed. Compared with a general display device, the pixel electrode is prevented from being damaged.

  Hereinafter, a flat panel display according to a modification of the first embodiment of the present invention will be described with reference to FIG.

  An OLED 1 ′ according to this modification includes a substrate 10, a buffer layer 11, a TFT 2, a capacitor 3 ′, and an organic light emitting element 4. The OLED 1 ′ according to this modification is different in the structure of the capacitor 3 ′ from the OLED 1 described above. Hereinafter, this modification will be described focusing on this difference.

  The OLED 1 ′ of the present modification includes a capacitor third electrode 33. The third electrode 33 of the capacitor is formed on the second insulating layer 17 at a position corresponding to the second upper electrode 32-2 of the capacitor. The third electrode 33 of the capacitor is formed of the same material as the source / drain electrodes 24a and 24b.

  That is, although not shown in detail in the drawing, in order to manufacture the capacitor 3 ′ according to the present modification, light is applied to a portion corresponding to the region of the second upper electrode 32-2 of the capacitor during the fourth mask process. Exposure is performed using a mask having a mask pattern in which a blocking portion is formed. Thereafter, when a subsequent process such as etching is performed, the capacitor third electrode 33 is formed on the second insulating layer 17 as in the present modification.

  According to the display device according to the modification as described above, the capacitance of the capacitor increases, which contributes to the display quality improvement of the display device in addition to the cost reduction and pixel electrode damage prevention by the mask reduction described above.

  Hereinafter, a flat panel display according to a second embodiment of the present invention will be described with reference to FIGS.

  The OLED according to this embodiment includes a substrate 10, a buffer layer 11, a TFT 2 ′, a capacitor 3, and an organic light emitting element 4. The OLED according to this embodiment is different in TFT structure from the OLED 1 described above. Hereinafter, the present embodiment will be described focusing on the difference.

  First, referring to FIG. 18, after forming a photosensitive film P1 'on the structure of FIG. 1, a first mask M1' on which a predetermined pattern is drawn is prepared in order to pattern the photosensitive film P1 '. To align with the substrate 10.

  The first mask M1 'is a halftone mask including a light transmitting part M11', light blocking parts M12a ', M12b', M12c 'and a semi-transmissive part M13'.

  The first mask M1 'on which the above pattern is drawn is aligned with the substrate 10, and exposure is performed by irradiating the photosensitive film P1' with light of a predetermined wavelength band.

  Referring to FIG. 19, the pattern of the remaining photosensitive film after the development process for removing the exposed photosensitive film P1 'is schematically shown. The photosensitive film portions P11 ′ corresponding to the light transmitting portions M11 ′ of the halftone mask M1 ′ are removed, and the photosensitive film portions P12a ′, P12b ′, P12c ′ corresponding to the light blocking portions M12a ′, M12b ′, M13c ′, The photosensitive film portion P13 ′ corresponding to the semi-transmissive portion M13 ′ remains.

  Using the photosensitive films P12a ', P12b', P12c ', and P13' as a mask, the semiconductor layer 12 and the first conductive layer 13 on the substrate 10 are etched using the etching equipment. At this time, the structure of the portion P11 'without the photosensitive film is etched first, and the thickness of a part of the photosensitive film is etched. At this time, the etching process may be performed by various methods such as wet etching and dry etching.

  Referring to FIG. 20, during the primary etching process, the semiconductor layer 12 and the first conductive layer 13 of FIG. 19 in the portion P11 'without the photosensitive film were etched. Then, the photosensitive film portion P13 'corresponding to the semi-transmissive portion M13' of FIG. 19 is etched, but the lower structure remains as it is. On the other hand, portions of the photosensitive film portions P12a ′, P12b ′, and P12c ′ corresponding to the light blocking portions M12a ′, M12b ′, and M12c ′ remain after the primary etching, and this is used as a mask for the secondary etching. Proceed.

  Referring to FIG. 21, after the second etching process, after the remaining photosensitive film portions P12a ′, P12b ′, and P12c ′ in FIG. 20 are etched, the remaining second to fourth mask processes are completed. The shape of the OLED is schematically shown.

  A portion of the first conductive layer 13 below the region where the photosensitive film has been partially removed (between P12a ′ and P12b ′) is etched, and the first conductivity in the remaining region (below P12a ′ and P12b ′). The layer 13 was formed in the source / drain regions 21a ′ and 21b ′ of the TFT.

  According to the display device according to the above-described embodiment, since the source / drain regions are formed by the etching process of the first mask, a separate doping process is unnecessary as in the first embodiment. It can be simplified.

  Hereinafter, a flat panel display according to a modification of the second embodiment of the present invention will be described with reference to FIG.

  The OLED according to this modification includes a substrate 10, a buffer layer 11, a TFT 2 ′, a capacitor 3 ′, and an organic light emitting element 4. The OLED according to this modification is different in the structure of the TFT 2 ′ and the capacitor 3 ′ from the OLED 1 according to the first embodiment described above.

  The structure of the TFT 2 ′ is similar to that of the OLED according to the second embodiment described above. In the first mask process, the source and drain regions 21a ′ and 21b ′ formed of the same material as the first upper electrode 31-2 of the capacitor are formed. Prepare.

  On the other hand, the structure of the capacitor 3 ′ is the same as that of the OLED according to the modification of the first embodiment described above, and the third electrode 33 of the capacitor formed of the same material as the source and drain electrodes 24a and 24b in the fourth mask process. Is further provided.

  According to the display device according to the modification described above, since it is not necessary to proceed with a separate doping process for forming the source / drain regions, the process is simplified and the capacitance of the capacitor is increased. In addition to cost reduction due to reduction and prevention of pixel electrode damage, display quality of the display device can be improved.

  On the other hand, in the above-described embodiments and modifications, the OLED has been described as an example of the flat display device, but the present invention is not limited to this, and various display elements including a liquid crystal display device can be used.

  Further, in the drawings for explaining the embodiments according to the present invention, only one TFT and one capacitor are shown, but this is for convenience of explanation, and the present invention is not limited thereto. Without limitation, a plurality of TFTs and a plurality of capacitors may be provided as long as the mask process according to the present invention is not increased.

  In addition, since the components shown in the drawings can be enlarged or reduced for convenience of explanation, the present invention is not restricted by the size and shape of the components shown in the drawings. It will be understood from this that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention can be suitably applied to technical fields related to flat panel display devices.

1 OLED
2 TFT
DESCRIPTION OF SYMBOLS 3 Capacitor 4 Organic light emitting element 10 Board | substrate 11 Buffer layer 12 Semiconductor layer 13 1st conductive layer 14 1st insulating layer 15 2nd conductive layer 16 3rd conductive layer 17 2nd insulating layer 18 4th conductive layer 19 3rd insulating layer 21 Active layer 22 Gate electrode 24a, 24b Source / drain electrode 31 First electrode of capacitor 32 Second electrode of capacitor 42 Pixel electrode 43 PDL
45 Organic light emitting layer 46 Intermediate layer 47 Counter electrode

Claims (24)

A substrate,
A TFT active layer comprising a channel region, source and drain regions formed in the same layer on the substrate;
A first lower electrode of the capacitor formed of the same material as the active layer and spaced apart from the active layer by a predetermined distance; and a first upper electrode of the capacitor formed on the first lower electrode; ,
A first insulating layer formed on the substrate, the active layer and the first upper electrode;
A gate lower electrode and a gate upper electrode formed on the first insulating layer and sequentially formed in a region corresponding to the channel region;
A second lower electrode and an upper portion of the capacitor formed on the first insulating layer and made of the same material as each of the gate lower electrode and the upper electrode and sequentially formed in a region corresponding to the first upper electrode of the capacitor. Electrodes,
A pixel lower electrode formed on the first insulating layer, formed of the same material as the gate lower electrode and the capacitor second lower electrode, and formed of the same material as the gate upper electrode and the capacitor second upper electrode. A pixel upper electrode disposed on an upper edge of the pixel lower electrode so as to expose the pixel lower electrode;
A second hole is formed on the gate electrode, the capacitor second electrode and the pixel upper electrode, and is penetrated by a contact hole exposing the source and drain regions of the active layer and a via hole exposing a part of the edge of the pixel upper electrode. An insulating layer;
A flat panel display device comprising: a source and a drain electrode formed on the second insulating layer and connected to the source, drain region, and pixel upper electrode through the contact hole and via hole.   A pixel defining film formed on the second insulating layer and exposing the pixel lower electrode; an intermediate layer formed on the pixel lower electrode and including an organic light emitting layer; and a counter electrode formed on the intermediate layer The flat panel display according to claim 1, further comprising:   The flat panel display according to claim 1, wherein the TFT active layer and the first lower electrode of the capacitor are polycrystalline silicon obtained by crystallizing amorphous silicon.   The flat panel display according to claim 1, wherein the first upper electrode of the capacitor includes silicon doped with impurities.   The flat panel display according to claim 1, wherein end shapes of the first lower electrode and the upper electrode of the capacitor coincide with each other.   2. The flat panel display according to claim 1, wherein end shapes of the gate lower electrode and the upper electrode coincide with each other.   The flat panel display according to claim 1, wherein end shapes of the second lower electrode and the upper electrode of the capacitor coincide with each other.   2. The flat panel display according to claim 1, wherein end shapes of the pixel lower electrode and the upper electrode coincide with each other.   The flat panel display according to claim 1, further comprising a buffer layer on the substrate.   The flat panel display according to claim 1, wherein the second insulating layer is thicker than the first insulating layer.   The capacitor further comprises a third electrode of the capacitor formed on the second insulating layer so as to correspond to the second upper electrode of the capacitor and formed of the same material as the source and drain electrodes. A flat panel display device according to claim 1. A substrate,
A TFT active layer comprising a channel region formed on the substrate, and a source and drain region formed at an upper edge of the channel region;
The capacitor is formed of the same material as the channel region of the active layer, is spaced apart from the active layer by a predetermined distance, and is formed of the same material as the first lower electrode and the source and drain electrodes of the capacitor formed in the same layer as the channel region. A first upper electrode of the capacitor formed and formed on the first lower electrode;
A first insulating layer formed on the substrate, the active layer and the first upper electrode;
A gate lower electrode and a gate upper electrode formed on the first insulating layer and sequentially formed in a region corresponding to the channel region;
A second lower electrode and an upper portion of the capacitor formed on the first insulating layer and made of the same material as each of the gate lower electrode and the upper electrode and sequentially formed in a region corresponding to the first upper electrode of the capacitor. Electrodes,
A pixel lower electrode formed on the first insulating layer, formed of the same material as the gate lower electrode and the capacitor second lower electrode, and formed of the same material as the gate upper electrode and the capacitor second upper electrode. A pixel upper electrode disposed on an upper edge of the pixel lower electrode so as to expose the pixel lower electrode;
A contact hole is formed on the gate electrode, the capacitor second electrode, and the pixel upper electrode, and is penetrated by a contact hole exposing the source and drain regions of the active layer and a via hole exposing a part of the edge of the pixel upper electrode. Two insulating layers;
A flat panel display device comprising: a source and a drain electrode formed on the second insulating layer and connected to the source, drain region, and pixel upper electrode through the contact hole and via hole.   A pixel defining film formed on the second insulating layer and exposing the pixel lower electrode; an intermediate layer formed on the pixel lower electrode and including an organic light emitting layer; and a counter electrode formed on the intermediate layer The flat panel display according to claim 12, comprising:   The third electrode of the capacitor is further formed on the second insulating layer so as to correspond to the second upper electrode of the capacitor, and is formed of the same material as the source and drain electrodes. A flat panel display device according to claim 1. Sequentially depositing a semiconductor layer and a first conductive layer on a substrate;
Patterning the semiconductor layer and the first conductive layer on the active layer of the TFT and the first lower electrode and the upper electrode of the capacitor simultaneously as a first mask process;
Forming a first insulating layer on the structure of the first mask process;
Sequentially forming a second conductive layer and a third conductive layer on the first insulating layer;
As the second mask process, the second conductive layer and the third conductive layer are formed into a gate lower electrode and an upper electrode of the TFT, a second lower electrode and a second upper electrode of the capacitor, a pixel lower electrode and an upper electrode, respectively. Patterning at the same time;
Forming a source and drain region at the edge of the TFT active layer using the gate lower electrode and the upper electrode as a self-alignment mask;
Forming a second insulating layer on the structure of the second mask process;
Patterning the second insulating layer so that a part of the source and drain regions and a part of the edge of the pixel upper electrode are exposed as a third mask process;
Forming a fourth conductive layer on the structure of the third mask step;
Patterning the fourth conductive layer on the source and drain electrodes of the TFT as a fourth mask process;
Forming a third insulating layer on the structure of the fourth mask step;
And a step of removing the second insulating layer and the third insulating layer so that the pixel upper electrode is exposed as a fifth mask step.   16. The method of manufacturing a flat panel display according to claim 15, wherein the first mask process is a halftone mask having a semi-transmissive portion at a position corresponding to the active layer of the TFT.   The method of manufacturing a flat panel display according to claim 15, further comprising a step of sequentially forming an intermediate layer including an organic light emitting layer and a counter electrode on the structure in the fifth mask process.   The method of manufacturing a flat panel display according to claim 15, further comprising forming a buffer layer on the substrate.   The method according to claim 15, wherein the fourth masking step is a step of patterning a third electrode of the capacitor on the fourth conductive layer simultaneously with the source and drain electrodes. Sequentially depositing a semiconductor layer and a first conductive layer on a substrate;
Patterning the semiconductor layer and the first conductive layer on the active layer of the TFT including the channel region, the source and the drain region, and the first lower electrode and the upper electrode of the capacitor simultaneously as a first masking step;
Forming a first insulating layer on the structure of the first mask process;
Sequentially forming a second conductive layer and a third conductive layer on the first insulating layer;
As the second mask process, the second conductive layer and the third conductive layer are formed into a gate lower electrode and an upper electrode of the TFT, a second lower electrode and a second upper electrode of the capacitor, a pixel lower electrode and an upper electrode, respectively. Patterning at the same time;
Forming a second insulating layer on the structure of the second mask process;
Patterning the second insulating layer so that a part of the source and drain regions and a part of the edge of the pixel upper electrode are exposed as a third mask process;
Forming a fourth conductive layer on the structure of the third mask step;
Patterning the fourth conductive layer on the source and drain electrodes of the TFT as a fourth mask process;
Forming a third insulating layer on the structure of the fourth mask step;
And a step of removing the second insulating layer and the third insulating layer so that the pixel upper electrode is exposed as a fifth mask step.   21. The method of manufacturing a flat panel display according to claim 20, wherein the first mask process is a halftone mask having a semi-transmissive portion at a position corresponding to a central portion of the TFT active layer.   21. The method of manufacturing a flat panel display according to claim 20, further comprising a step of sequentially forming an intermediate layer having an organic light emitting layer and a counter electrode on the structure in the fifth mask step.   21. The method of manufacturing a flat panel display according to claim 20, further comprising a step of forming a buffer layer on the substrate.   21. The method of manufacturing a flat panel display according to claim 20, wherein the fourth masking step is a step of patterning a third electrode of the capacitor simultaneously with the source and drain electrodes on the fourth conductive layer.

Images