JPH09172183A - Semiconductor device, its fabrication and active matrix substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which, like an active matrix substrate built in a drive circuit, at least comprises a thin film transistor(TFT), another TFT having a conductivity type different from that of the former TFT or a capacitive element, whose electrical characteristics are improved with use of a minimum number of fabricating steps, and also to provide a method for fabricating the semiconductor device. SOLUTION: A TFT 10 of a first conductivity type for pixels and a TFT 20 of the first conductivity type for a drive circuit have a light doped drain(LDD) structure which includes low-concentration source/drain zones 111, 121, and 211, 221 of the first conductivity type in source/drain regions 11, 12, and 21, 22. Doped in channel regions 13 and 23 are a low concentration of impurities of a second conductivity type. A TFT 30 of the second conductivity type for the drive circuit has an offset gate structure. Since a low concentration of impurities of the second conductivity type are doped in the channel regions, offset regions 311' and 321' are also of the low concentration and of the second conductivity type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an active matrix substrate having different conductivity type thin film transistors (hereinafter abbreviated as TFT) or TFT and a capacitive element, and a manufacturing method thereof. More specifically, while simplifying the manufacturing process of these semiconductor devices, TF
The present invention relates to a technique for optimizing the electrical characteristics of T.

[0002]

2. Description of the Related Art As a semiconductor device using a TFT, there is an active matrix substrate having a built-in drive circuit of a liquid crystal display device. In the active matrix substrate, FIG.
In addition, as shown schematically from the left side region to the right side region, the P type drive circuit TF is shown.
T30 ″, N-type drive circuit TFT 20 ″, and N-type pixel TFT 10 ″ are formed on the same insulating substrate 2. Here, when each TFT is formed in a self-aligned structure, FIG. There is a problem that the off-leakage current is large, as shown by the solid line L1 for the on-off leak current characteristic of the N-type TFT and the dotted line L2 for the on-off leak current characteristic of the P-type TFT. When a large TFT is used as a pixel TFT, display unevenness is likely to occur, and also in a drive circuit TFT, a large off-leak current tends to cause unnecessary power consumption and malfunction. 31 (a) shows the withstand voltage characteristic of the N-type TFT by a solid line L23, and FIG. 31 (b) shows the withstand voltage characteristic of the P-type TFT. As shown in L24, since the withstand voltage between the source and drain of the TFT is not sufficient, longer inevitably set the channel length.

Therefore, in the active matrix substrate shown in FIG. 29, each TFT has an LDD structure. (In the present application, this may be abbreviated as LDD TFT.) All the TFTs formed on this active matrix substrate have source / drain regions 11, 12, 21, 22,
The portions of the 31, 32 facing the ends of the gate electrodes 15, 25, 35 are lightly doped source / drain regions 111, 12 respectively.
It is 1, 211, 221, 311, and 321. Therefore, in FIG. 32, the on / off leakage current characteristic of the N-type TFT is shown by a solid line L3, and the on / off leakage current characteristic of the P-type TFT is shown by a dotted line L4, so that the off-leakage current is small. Therefore, it is possible to prevent the occurrence of display unevenness and flicker, and to suppress malfunction and wasteful power consumption.
In addition, the LDD structure TFT is an N-type TFT shown in FIG.
The withstand voltage characteristics in Fig. 31 (b) are shown by the solid line L21.
As shown by the solid line L22 in the withstand voltage characteristic of the P-type TFT, the source-drain withstand voltage is high, so that there is an advantage that the channel length can be shortened.

On the other hand, when the above-mentioned semiconductor device is applied to the active matrix substrate, the storage capacitor 40 ″ may be formed on the same insulating substrate 2 in order to improve the charge holding characteristic in the liquid crystal cell. (Refer to FIG. 29.) Conventionally, this storage capacitor 40 ″ has a low concentration N formed by making a silicon film conductive.
A type silicon film is provided as the lower layer side electrode portion 40g.
Here, a silicon oxide film formed at the same time as the gate insulating films 14, 24 and 34 of the TFT is formed as a dielectric film 44 on the surface side of the lower layer side electrode portion 40g. On the surface side of the dielectric film 44, the gate electrodes 15, 25, 3 of the TFT are provided.
5, a part of the dedicated capacitance line formed at the same time as 5 or a part of the signal line in the previous stage is formed as the upper layer side electrode part 45.

The active matrix substrate 1 "having such a structure is conventionally manufactured by the following method.

First, as shown in FIG. 33 (a), island-shaped silicon films 10a, 20a formed on the surface of the insulating substrate 2,
Gate insulating films 14, 24, 3 for 30a, 40a
4, and after forming the dielectric film 44, about 1 × 10 ¹² cm
^Implant boron ions with a dose of ^-2 . This is because channel doping is performed (first impurity introducing step). As a result, each silicon film 10a, 20a, 30a, 40a becomes a low concentration P type. This is performed to adjust the threshold voltage (Vth) of the thin film transistor. (In the present application, this may be abbreviated as channel dope or C / D.) Next, as shown in FIG. 33B, the formation region of each TFT is covered with a resist mask 151 (first mask formation). Process). Subsequently, phosphorus ions are implanted with a dose amount of about 3 × 10 14 cm ⁻² to invert the silicon film 40a into an N type to form a storage capacitor 40 ″, thereby forming a lower layer side electrode portion 40g.
(Second impurity introduction step).

Next, as shown in FIG. 33C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed,
After forming the storage capacitor 40 ″, the N-type pixel TFT 1 is formed.
The formation regions of the 0 ″ and N-type drive circuit TFTs 20 ″ are covered with a resist mask 152 (second mask forming step). Subsequently, boron ions are implanted with a dose amount of about 2 × 10 ¹³ cm ^-2 , and the impurity concentration is about 2.1 × 10 ¹⁸ c.
Low concentration P-type source / drain regions 31 and 32 of m ⁻³ are formed (third impurity introducing step). The portion where no impurities are introduced becomes the channel region 33.

Next, as shown in FIG. 33D, a resist mask 15 is formed in the formation region of the P-type drive circuit TFT 30 ".
3 (3rd mask formation step). Then about 1x
Phosphorus ions are implanted at a dose of 10 ¹³ cm ^-2 to form low-concentration N-type source / drain regions 11, 12, 21, 22 having an impurity concentration of about 0.9 × 10 ¹⁸ cm ^-3 (fourth time). Impurity introduction step).

Next, as shown in FIG. 33 (e), an N-type pixel TFT 10 "forming region and an N-type drive circuit TFT are formed.
In addition to the formation region of 20 ″ and the storage capacitor 40 ″, a resist mask 154 that broadly covers the gate electrode 35 is formed (fourth mask forming step). Then, about 1 x 10
Boron ions are implanted with a dose amount of ¹⁵ cm ⁻² to form high-concentration source / drain regions 312 and 322 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ (fifth impurity introducing step). As a result, the low concentration P-type source / drain region 3 is formed.
Of the parts 1 and 32, the part covered with the resist mask 154 becomes the low-concentration source / drain regions 311 and 321 with the impurity concentration of about 2.1 × 10 ¹⁸ cm ⁻³ . In this way, the P-type drive circuit TFT 30 ″ is formed.

Next, as shown in FIG. 33F, a resist mask 155 is formed to widely cover the gate electrodes 15 and 25 in addition to the formation region of the P-type drive circuit TFT 30 "(fifth time). Mask forming step).
Phosphorus ions are implanted with a dose amount of ¹⁵ cm ⁻² to form high concentration source / drain regions 112, 122, 212, 222 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ (sixth impurity introduction step). Of the low concentration N-type source / drain regions 11, 12, 21, and 22, the resist mask 155
The impurity concentration of the part covered with is about 0.9 ×
1018 cm ^-3 low concentration source / drain region 111,
121, 211, and 221. In this way, the N-type pixel TFT 10 ″ and the N-type drive circuit TFT 20 ″ are formed.

Thereafter, as shown in FIG. 29, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16 and 1.
The active matrix substrate 1 ″ is completed by forming 7, 26, 27, 36, and 37. Thus, conventionally, the mask formation step (resist mask 151) is performed five times only to add a donor or acceptor impurity to the semiconductor film. ˜155) and six impurity introduction steps. However, if the storage capacitor 40 ″ is not formed, mask formation is performed four times just to add the donor or acceptor impurities to the semiconductor film. Process (formation of resist masks 152 to 155)
Then, the impurity introducing step is performed five times.

[0012]

However, the manufacturing cost of the active matrix substrate is largely controlled by the number of mask forming steps and the number of impurity introducing steps. There is a problem that the number of processes will increase significantly. For example, in FIG.
LD as in the manufacturing method described with reference to (a) to (f)
When the CMOS structure is formed by the DTFT and the storage capacitor 40 ″ is also formed, five mask forming steps and six impurity introducing steps are necessary only for adding a donor or acceptor impurity to the semiconductor film. Therefore, there is a problem that the manufacturing cost of the active matrix substrate is significantly increased.This problem is not limited to the active matrix substrate, and other semiconductor devices having TFTs of different conductivity types and the capacity of the TFT and the capacitor are different. The same applies to other semiconductor devices having both elements.

In view of the above problems, an object of the present invention is to provide a semiconductor device including at least a TFT and a TFT having a conductivity type different from that of the TFT, such as an active matrix substrate having a built-in drive circuit, or a semiconductor device. It is intended to provide a semiconductor device in which electric characteristics of each TFT are improved by a minimum number of manufacturing steps, a manufacturing method thereof, and an active matrix substrate.

[0014]

In order to solve the above problems, the present invention configures a semiconductor device as follows. Each of the inventions described below has a common object and problem to be a semiconductor device having improved electrical characteristics of each TFT and a method of manufacturing the same by a minimum number of manufacturing steps, but if they are further classified, The invention according to claims 1 to 26 and claims 27 to 4
The invention is broadly divided into the invention according to 8.

The invention according to claims 1 to 26 relates to a semiconductor device having a first-conductivity-type TFT and a second-conductivity-type TFT on the same substrate, and an active-matrix substrate adapted for the same, such as a liquid crystal display device. . Claims 8 to 11
Claims 19 to 22 are inventions relating to a method of manufacturing these semiconductor devices.

On the other hand, the invention according to claims 27 to 39 relates to a semiconductor device having a TFT and a capacitive element on the same substrate, and an active matrix substrate adapted for the same such as a liquid crystal display device. Claims 40 to 4
The invention according to No. 8 is an invention relating to a method for manufacturing these semiconductor devices.

[Invention of Claim 1] The present invention is a first conductivity type including a first channel region and a first conductivity type high concentration source / drain region facing the first gate electrode with a first gate insulating film interposed therebetween. In a semiconductor device having a thin film transistor, a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing the second gate electrode via a second gate insulating film,
The first conductivity type thin film transistor has an LDD structure including a first conductivity type high concentration source / drain region and a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel. The region contains an extremely low concentration second conductivity type impurity, and the second conductivity type thin film transistor has the same impurity concentration as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. And the second channel region contains an extremely low concentration of the second conductivity type impurity.

According to this structure, the off-current is small in all TFTs because the portion facing the end of the gate electrode is a low concentration region. Also, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Therefore, the on-current increases, and the transistor capacitance can be further reduced, which has the advantage of enabling high-speed operation. Further, in the second-conductivity-type drive circuit TFT, the low-concentration region facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, it is possible to reduce the mask forming step and the impurity introducing step by one each, as compared with the case of manufacturing all the TFTs with the LDD structure. The second conductivity type impurity introduced at an extremely low concentration adjusts Vth in the channel and acts as a low concentration majority carrier in the offset region. Thus, a semiconductor device in which the electric characteristics of each TFT are optimized can be realized with the minimum number of manufacturing steps.

[Invention of Claim 2] The present invention provides claim 1
The source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , the source / drain current is I _DS1, and the source / drain voltage of the second conductivity type thin film transistor is To V
_DS2 , gate voltage V _GS2 , source / drain current I _{DS
When set to 2} , | V _DS1 | = | V _DS2 |, and V _GS1 = V _GS2
The second conductivity type impurity concentrations of the second channel region and the offset region are set so that I _DS2 > I _DS1 under the condition of = 0.

With this configuration, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the on-current and the transistor capacitance of the first conductivity type TFT and the second conductivity type TFT are substantially reduced. It is possible to make them equivalent. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and malfunction does not easily occur. At the same time, the circuit configuration and layout are simplified. (Because the first conductivity type TFT and the second conductivity type TFT can have the same size and dimension.) [Invention of Claim 3] The present invention provides the semiconductor device according to claim 1 in which the first conductivity type is the same as the first conductivity type TFT. The source / drain voltage of the second type thin film transistor is V _DS1 , the gate voltage is V _GS1 , the source / drain current is I _DS1, and the source / drain voltage of the second conductivity type thin film transistor is V _DS2 , the gate voltage is V _GS2 , the source / drain. current when the _{I DS 2 | V DS1 | =} | V DS2 |, and the first conductive type thin film transistor gate voltage from 0V when serving as the I _DS2 = I _{DS 1} under conditions of V _GS1 = V _GS2 The second conductivity type impurity concentrations of the second channel region and the offset region are determined so that the second channel region and the offset region are shifted toward the ON state.

According to this structure, the second conductivity type TFT having the offset structure is weakly depleted by only optimizing the impurity concentration of the second conductivity type in the channel region and the offset region of the second conductivity type TFT. In this case, the first conduction type TFT having the LDD structure can be set to the weak enhancement mode. Thus, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the first conductivity type TFT and the second conductivity type TFT are
It is possible to make the on-current and the transistor capacitance of the two substantially equal. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and malfunction does not easily occur.
At the same time, the circuit configuration and layout are simplified. (Because the first conductivity type TFT and the second conductivity type TFT can have the same size and dimension.) [Invention of Claim 4] The present invention provides the semiconductor device according to any one of claims 1 to 3. The second conductivity type impurity concentration contained in one channel region, the second conductivity type impurity concentration contained in the second channel region, and the second conductivity type impurity concentration contained in the offset region are all the same.

That is, when the second conductivity type impurity is introduced into the channel region of the second conductivity type TFT, the second conductivity type impurity is also introduced into the channel region of the first conductivity type TFT, and at the same time, the second conductivity type impurity is also introduced into the offset region. Conductive impurities can be introduced. Therefore, the number of processes can be reduced.

[Inventions of Claims 5 and 6] In the present invention, it means that the first conductivity type and the second conductivity type are opposite conductivity types, and when the first conductivity type is N type, The second conductivity type is P type. Conversely, when the first conductivity type is P-type, the second conductivity type is N-type.

[Invention of Claim 7] In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductivity type and the second conductivity type thin film transistors are CMOS circuits in a driving circuit. One of the first conductive type thin film transistor and the second conductive type thin film transistor constitutes a pixel thin film transistor in the pixel region.

[Invention of Claim 8] The present invention provides claim 1
In the method for manufacturing a semiconductor device described in (1), an extremely low concentration of a second conductivity type impurity is introduced into the semiconductor film to form the first channel region, the second channel region and the offset region. Concentration second conductivity type impurity introduction step,
A gate electrode forming step of forming the first gate electrode and the second gate electrode, and introducing a low concentration first conductivity type impurity into the semiconductor film to form the first conductivity type low concentration source / drain regions. Low-concentration first-conductivity-type impurity introduction step, and high-concentration first-conductivity-type impurities for introducing the first-conductivity-type impurities into the semiconductor film in high concentration to form the first-conductivity-type high-concentration source / drain regions A high-concentration second-conductivity-type impurity introducing step of introducing a high-concentration second-conductivity-type impurity into the semiconductor film to form the second-conductivity-type high-concentration source / drain regions, The step of introducing the extremely low concentration second conductivity type impurities is performed before the step of forming the gate electrode, and the step of introducing the low concentration first conductivity type impurities is performed after the formation of the gate electrode.

[Invention of Claim 9] In the present invention, the step of introducing an extremely low concentration second conductivity type impurity is performed as a step of forming a doped semiconductor film containing an extremely low concentration of the second conductivity type impurity. After that, a gate insulating film may be formed on the surface of the semiconductor film.

[Invention of Claim 10] In the present invention, the step of introducing an extremely low concentration second conductivity type impurity is carried out at a low concentration of the second conductivity type impurity with respect to the semiconductor film formed before this step. It may be performed as a step of introducing, and after this step, a gate insulating film may be formed on the surface of the semiconductor film.

[Invention of Claim 11] In the present invention, the step of introducing an extremely low concentration second conductivity type impurity is performed through a gate insulating film formed on the surface of a semiconductor film formed before this step. In some cases, the second conductivity type impurity is introduced at an extremely low concentration.

[Invention of Claim 12] The present invention provides a first conductivity type having a first channel region and a first conductivity type high concentration source / drain region facing the first gate electrode through a first gate insulating film. In a semiconductor device having a thin film transistor, a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing the second gate electrode via a second gate insulating film, The first conductivity type thin film transistor includes an LDD having a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region.
Forming a structure, the first channel region contains a very low concentration first conductivity type impurity, and the second conductivity type thin film transistor is provided between the second conductivity type high concentration source / drain region and the second channel region. An offset structure having an offset region having the same impurity concentration as the second channel region is formed, and the second channel region contains an extremely low concentration of the first conductivity type impurity.

According to this structure, the off current is small because all the TFTs have a low-concentration region facing the end of the gate electrode. Also, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Therefore, the on-current increases, and the transistor capacitance can be further reduced, which has the advantage of enabling high-speed operation. Further, in the second-conductivity-type drive circuit TFT, the low-concentration region facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, it is possible to reduce the mask forming step and the impurity introducing step by one each, as compared with the case of manufacturing all the TFTs with the LDD structure. The first conductivity type impurity introduced at an extremely low concentration adjusts Vth in the channel, and acts as a low concentration majority carrier in the offset region. Thus, a semiconductor device in which the electric characteristics of each TFT are optimized can be realized with the minimum number of manufacturing steps.

[Invention of Claim 13] The present invention provides the semiconductor device according to claim 12, wherein the source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain. When the current is I _DS1 , the source / drain voltage of the second conductivity type thin film transistor is V _DS2 , the gate voltage is V _GS2 , and the source / drain current is I _DS2 , | V _DS1 | = | V _DS2 |, and V _GS1 = V
The first conductivity type impurity concentrations of the second channel region and the offset region are set so that I _DS2 > I _DS1 under the condition of _GS2 = 0.

With this configuration, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the on-current and the transistor capacitance of the first conductivity type TFT and the second conductivity type TFT are substantially reduced. It is possible to make them equivalent. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and malfunction does not easily occur. At the same time, the circuit configuration and layout are simplified. (Because the first conductivity type TFT and the second conductivity type TFT can have the same size and dimension.) [Invention of Claim 14] The present invention provides the semiconductor device according to claim 12, wherein the first conductivity type TFT is the same as the first conductivity type TFT. The source / drain voltage of the second type thin film transistor is V _DS1 , the gate voltage is V _GS1 , the source / drain current is I _DS1, and the source / drain voltage of the second conductivity type thin film transistor is V _DS2 , the gate voltage is V _GS2 , the source / drain. Current I
_{When DS2} is set, | V _DS1 | = | V _DS2 |, and V _GS1 = V
Under the condition of _GS2 , the gate voltage when I _DS2 = I _DS1 is shifted from 0 V toward the ON state of the first conductivity type thin film transistor, so that the second channel region and the offset region are The first conductivity type impurity concentration is defined.

According to this structure, only by optimizing the impurity concentration of the first conductivity type in the channel region and the offset region of the second conductivity type TFT, the weak conductivity of the second conductivity type TFT having the offset structure can be obtained. In this case, the first conduction type TFT having the LDD structure can be set to the weak enhancement mode. Thus, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the first conductivity type TFT and the second conductivity type TFT are
It is possible to make the on-current and the transistor capacitance of the two substantially equal. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and malfunction does not easily occur.
At the same time, the circuit configuration and layout are simplified. (Because the first conductivity type TFT and the second conductivity type TFT can have the same size and dimension.) [Invention of Claim 15] The present invention provides Claims 12 to 14.
In the semiconductor device described in the paragraph 1, the first conductivity type impurity concentration contained in the first channel region, the first conductivity type impurity concentration contained in the second channel region, and the first conductivity type impurity contained in the offset region. It is characterized in that the concentrations are all the same.

That is, when introducing the first conductivity type impurity into the channel region of the second conductivity type TFT, the first conductivity type impurity is introduced into the channel region of the first conductivity type TFT, and at the same time, the first conductivity type impurity is also introduced into the offset region. Conductive impurities can be introduced. Therefore, the number of processes can be reduced.

[Invention of Claims 16 and 17] In the present invention, it means that the first conductivity type and the second conductivity type are opposite conductivity types, and when the first conductivity type is N type, The second conductivity type is P type. Conversely, when the first conductivity type is P-type, the second conductivity type is N-type.

[Invention of Claim 18] In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductivity type and the second conductivity type thin film transistors are CMOS circuits in a driving circuit. One of the first conductive type thin film transistor and the second conductive type thin film transistor constitutes a pixel thin film transistor in the pixel region.

[Invention of Claim 19] The present invention provides a method of manufacturing a semiconductor device according to claim 12, wherein the first channel region, the second channel region and the offset region are formed. An extremely low concentration first conductivity type impurity introduction step of introducing one conductivity type impurity into the semiconductor film at an extremely low concentration; a gate electrode forming step of forming the first gate electrode and the second gate electrode; A low-concentration first-conductivity-type impurity introduction step of introducing a first-conductivity-type impurity into the semiconductor film at a low concentration to form a low-concentration-conductivity-type source / drain region; A high-concentration first-conductivity-type impurity introduction step of introducing a high-concentration first-conductivity-type impurity into the semiconductor film to form the second conductivity-type high-concentration source / drain region. High type impurities And a high concentration second conductivity-type impurity introduction step of introducing into the semiconductor film in degrees, polar low concentration first conductivity type impurity doping process is performed before the gate electrode formation step,
The low-concentration first conductivity type impurity introducing step is performed after the gate electrode is formed.

[Invention of Claim 20] In the present invention, the step of introducing an extremely low concentration first conductivity type impurity is performed as a step of forming a doped semiconductor film containing an extremely low concentration of the first conductivity type impurity. After that, a gate insulating film may be formed on the surface of the semiconductor film.

[Invention of Claim 21] In the present invention, the step of introducing an extremely low concentration first conductivity type impurity is performed with a low concentration of the first conductivity type impurity in a semiconductor film formed before this step. It may be performed as a step of introducing, and after this step, a gate insulating film may be formed on the surface of the semiconductor film.

[Invention of Claim 22] In the present invention, the step of introducing an extremely low concentration first conductivity type impurity is performed through a gate insulating film formed on the surface of a semiconductor film formed before this step. Therefore, it may be performed as a step of introducing the first conductivity type impurity at an extremely low concentration.

[Invention of Claim 23] The present invention provides a first conductivity type having a first channel region and a first conductivity type high concentration source / drain region facing the first gate electrode with a first gate insulating film interposed therebetween. In a semiconductor device having a thin film transistor, a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing the second gate electrode via a second gate insulating film, The first conductivity type thin film transistor includes an LDD having a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region.
The first channel region is substantially intrinsic, and the second conductivity type thin film transistor is the same as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. The offset structure has an offset region having an impurity concentration, and the second channel region is substantially intrinsic.

According to this structure, the off-current is small in all TFTs because the portion facing the end of the gate electrode is the low concentration region. Also, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Therefore, the on-current increases, and the transistor capacitance can be further reduced, which has the advantage of enabling high-speed operation. Further, in the second-conductivity-type drive circuit TFT, the semiconductor facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, it is possible to reduce the number of mask forming steps once and the number of impurity introducing steps twice as compared with the case where all TFTs are manufactured with the LDD structure. Thus, a semiconductor device in which the electric characteristics of each TFT are optimized can be realized with the minimum number of manufacturing steps.

[Inventions of Claims 24 and 25] In the present invention, it means that the first conductivity type and the second conductivity type are opposite conductivity types, and when the first conductivity type is N type, The second conductivity type is P type. Conversely, when the first conductivity type is P-type, the second conductivity type is N-type.

[Invention of Claim 26] In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductivity type and the second conductivity type thin film transistors are CMOS circuits in a driving circuit. One of the first conductive type thin film transistor and the second conductive type thin film transistor constitutes a pixel thin film transistor in the pixel region.

[Invention of Claim 27] In the present invention, a thin film transistor having a channel region facing a gate electrode via a gate insulating film and source / drain regions connected to the channel region, and a thin film transistor facing each other via a dielectric film. In the semiconductor device having a first electrode part and a capacitive element composed of a second electrode part, the thin film transistor has low concentration source / drain regions in which the source / drain regions face the ends of the gate electrode via a gate insulating film. Area and the low concentration source
An LDD structure having a high-concentration source / drain region adjacent to the drain region is formed, and the first electrode portion has the same conductivity type as the low-concentration source / drain region and the same impurity concentration of the conductivity type. It is characterized by being composed of a semiconductor film.

With such a structure, it becomes possible to simultaneously form the low-concentration source / drain regions and the first electrode portion, and by utilizing the advantages of the LDD TFT, such a semiconductor device can be manufactured with a small number of steps. Manufactured.

[Invention of Claim 28] According to the present invention, a thin film transistor having a channel region facing a gate electrode via a gate insulating film and source / drain regions connected to the channel region, and a thin film transistor facing each other via a dielectric film. In the semiconductor device having a first electrode part and a capacitive element composed of a second electrode part, the thin film transistor has low concentration source / drain regions in which the source / drain regions face the ends of the gate electrode via a gate insulating film. Area and the low concentration source
An LDD structure having a high-concentration source / drain region adjacent to a drain region is formed, and the first electrode portion has the same conductivity type as the high-concentration source / drain region and the same impurity concentration of the conductivity type. It is characterized by being composed of a semiconductor film.

With such a structure, it becomes possible to simultaneously form the high-concentration source / drain regions and the first electrode portion, and by utilizing the advantages of the LDD TFT, such a semiconductor device can be manufactured in a small number of steps. Manufactured. Further low concentration sauce
The drain region can be formed in a self-aligned manner with respect to the gate electrode, and a good TFT with a small parasitic capacitance can be obtained.

[Invention of Claim 29] The present invention provides a thin film transistor having a channel region facing a gate electrode via a gate insulating film and a source / drain region containing a high concentration of a donor impurity or an acceptor impurity, and a dielectric film. In a semiconductor device having a first electrode portion and a capacitive element formed of a second electrode portion that face each other, the thin film transistor includes the channel region between the source / drain region end and the channel region end. An offset region having an equivalent impurity concentration is provided, and the first electrode portion is composed of the same semiconductor film having the same conductivity type as the high-concentration source / drain region and the same impurity concentration of the conductivity type. Characterize.

With such a structure, it becomes possible to simultaneously form the high-concentration source / drain regions and the first electrode portion, and by utilizing the advantage of the offset TFT, such a semiconductor device can be manufactured with a small number of steps. Manufactured. Furthermore, it becomes possible to create low-concentration source / drain regions in a self-aligned manner with the gate electrode, and a good TFT with less parasitic capacitance
Is obtained.

[Invention of Claim 30] The present invention is a thin film transistor of the first conductivity type and the second conductivity type, which comprises a channel region facing a gate electrode through a gate insulating film and source / drain regions connected to the channel region. And a capacitor device comprising a first electrode part and a second electrode part which are opposed to each other with a dielectric film interposed therebetween, in the first conductivity type and second conductivity type thin film transistors, the source / drain regions are gates. An LDD structure is provided which includes a low-concentration source / drain region facing the end of the electrode via a gate insulating film, and a high-concentration source / drain region adjacent to the low-concentration source / drain region. Is the low-concentration source of the first conductivity type and second conductivity type thin film transistors.
It is characterized in that it is composed of the same semiconductor film having the same conductivity type as the drain region and the same impurity concentration of the conductivity type.

With such a structure, it becomes possible to simultaneously form the low-concentration source / drain regions and the first electrode portion, and by utilizing the advantages of the LDD CMOS TFT, such a semiconductor device can be manufactured with a small number of steps. Is manufactured.

[Invention of Claim 31] The present invention is a first-conductivity-type and second-conductivity-type thin film transistor having a channel region facing a gate electrode through a gate insulating film and source / drain regions connected to the channel region. And a capacitor device comprising a first electrode part and a second electrode part which are opposed to each other with a dielectric film interposed therebetween, in the first conductivity type and second conductivity type thin film transistors, the source / drain regions are gates. An LDD structure is provided which includes a low-concentration source / drain region facing the end of the electrode via a gate insulating film, and a high-concentration source / drain region adjacent to the low-concentration source / drain region. Is the high concentration source of the first conductivity type and second conductivity type thin film transistors.
It is characterized in that it is composed of the same semiconductor film having the same conductivity type as the drain region and the same impurity concentration of the conductivity type.

With such a structure, it becomes possible to simultaneously form the high-concentration source / drain regions and the first electrode portion, and by utilizing the advantages of the LDD CMOS TFT, such a semiconductor device can be manufactured with a small number of steps. Is manufactured. Further, it becomes possible to form the low-concentration source / drain regions in a self-aligned manner with respect to the gate electrode, and a good TFT with less parasitic capacitance can be obtained.

[Invention of Claim 32] The present invention is the semiconductor device as set forth in claim 30, wherein the first electrode portion has the first conductivity type in the low concentration source / drain region of the first conductivity type thin film transistor. And a low-concentration source / drain region of the first-conductivity-type thin film transistor, together with the first-conductivity-type impurities, is less than the first-conductivity-type impurities. ,
And the low concentration source of the second conductivity type thin film transistor
It is characterized in that it contains the same amount of impurities of the second conductivity type as the drain region.

With this configuration, the LDD CMOS
By taking advantage of the TFT, the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 33] The present invention is the semiconductor device according to claim 30, wherein the first electrode portion has the second conductivity type in the low concentration source / drain region of the second conductivity type thin film transistor. And a low-concentration source / drain region of the first-conductivity-type thin film transistor together with the first-conductivity-type impurity. In addition, the second conductivity type thin film transistor includes the same concentration of second conductivity type impurities as the low concentration source / drain regions.

With this configuration, the LDD CMOS
By taking advantage of the TFT, the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 34] The present invention is the semiconductor device according to claim 31, wherein the first electrode portion has the first conductivity type of the high-concentration source / drain region of the first conductivity type thin film transistor. And a low-concentration source / drain region of the first-conductivity-type thin film transistor, together with the first-conductivity-type impurities, is less than the first-conductivity-type impurities. In addition, the second conductivity type thin film transistor includes the same concentration of second conductivity type impurities as the low concentration source / drain regions.

With this configuration, the LDD CMOS
By taking advantage of the TFT, the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 35] The present invention is the semiconductor device as set forth in claim 31, wherein the first electrode portion has the second conductivity type in the high-concentration source / drain region of the second conductivity type thin film transistor. And a low-concentration source / drain region of the first-conductivity-type thin film transistor together with the first-conductivity-type impurity. In addition, the second conductivity type thin film transistor includes the same concentration of second conductivity type impurities as the low concentration source / drain regions.

With this structure, the LDD CMOS
By taking advantage of the TFT, the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 36] The present invention comprises a channel region facing the gate electrode via a gate insulating film and a high concentration first conductivity type source / drain region containing a high concentration of first conductivity type impurity. A first conductivity type thin film transistor, a second conductivity type thin film transistor having a high-concentration second conductivity type source / drain region containing a high-concentration channel region facing the gate electrode via a gate insulating film and a second conductivity type impurity, In a semiconductor device having a first electrode part and a capacitive element composed of a second electrode part facing each other with a dielectric film interposed therebetween, the first conductivity type thin film transistor is the high concentration first conductivity type source / drain region end. Forming an LDD structure having a low-concentration first-conductivity type source / drain region between a channel portion and an end of the channel region, and the second-conductivity-type thin film transistor is the high-concentration region. An offset region having an impurity concentration equivalent to that of the channel region is provided between the ends of the two-conductivity type source / drain regions and the end of the channel region, and the first electrode portion has a low concentration first region of the first conductivity type thin film transistor. It is characterized in that it is composed of a semiconductor film containing the same amount of impurities of the first conductivity type as the conductivity type source / drain regions.

With such a structure, the advantage of the LDD TFT and the offset TFT can be utilized, and the photo process can be further reduced by one process, and such a semiconductor device can be manufactured by a smaller number of processes.

[Invention of Claim 37] The present invention comprises a channel region facing the gate electrode via a gate insulating film and a high-concentration first-conductivity type source / drain region containing a first-conductivity-type impurity at a high concentration. A first conductivity type thin film transistor, a second conductivity type thin film transistor having a high-concentration second conductivity type source / drain region containing a high-concentration channel region facing the gate electrode via a gate insulating film and a second conductivity type impurity, In a semiconductor device having a first electrode part and a capacitive element composed of a second electrode part facing each other with a dielectric film interposed therebetween, the first conductivity type thin film transistor is the high concentration first conductivity type source / drain region end part. An LDD structure having a low-concentration first-conductivity type source / drain region between the channel region and an end portion of the channel region, and the second-conductivity-type thin film transistor is the high-concentration first transistor. An offset region having an impurity concentration equivalent to that of the channel region is provided between an end of the conductive type source / drain region and an end of the channel region, and the first electrode unit has a high-concentration first conductivity of the first conductive type thin film transistor. It is characterized in that it is composed of a semiconductor film containing the same amount of impurities of the first conductivity type as the type source / drain regions.

With such a structure, the advantage of the LDD TFT and the offset TFT can be utilized, and the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 38] The present invention comprises a channel region facing the gate electrode via a gate insulating film and a high-concentration first conductivity type source / drain region containing a high concentration of the first conductivity type impurity. A first conductivity type thin film transistor, a second conductivity type thin film transistor having a high-concentration second conductivity type source / drain region containing a high-concentration channel region facing the gate electrode via a gate insulating film and a second conductivity type impurity, In a semiconductor device having a first electrode part and a capacitive element composed of a second electrode part facing each other with a dielectric film interposed therebetween, the first conductivity type thin film transistor is the high concentration first conductivity type source / drain region end part. An LDD structure having a low-concentration first-conductivity type source / drain region between the channel region and an end portion of the channel region, and the second-conductivity-type thin film transistor is the high-concentration first transistor. An offset region having an impurity concentration equivalent to that of the channel region is provided between an end of the conductive type source / drain region and an end of the channel region, and the first electrode unit has a high-concentration second conductivity of the second conductive type thin film transistor. It is characterized by being composed of a semiconductor film containing the same amount of second conductivity type impurities as the type source / drain regions.

With such a structure, the advantage of the LDD TFT and the offset TFT can be utilized, and the photo process can be further reduced by one process, and such a semiconductor device can be manufactured with a smaller number of processes.

[Invention of Claim 39] The present invention is an active matrix substrate using the semiconductor device defined in any one of claims 27 to 38, wherein the first conductivity type and the second conductivity type are provided. The thin film transistor constitutes a CMOS circuit in a driving circuit portion, at least one of the first conductivity type and second conductivity type thin film transistors constitutes a pixel thin film transistor in a pixel region, and the capacitance element is It is characterized in that a storage capacitor for the liquid crystal cell is formed in the pixel region.

[Invention of Claim 40] The present invention comprises a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region conductively connected to the channel region through a low concentration source / drain region. In a method of manufacturing a semiconductor device having an LDD thin film transistor and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed therebetween, at least the channel region and the low-concentration source / drain regions are provided. A first step of forming a semiconductor film that constitutes the first electrode portion; and a step of introducing a dopant or acceptor impurity into a portion of the semiconductor film at a low concentration to form the low concentration source / drain regions and the first It is characterized by including a second step of forming an electrode portion and a third step of forming a gate electrode and a second electrode portion after the second step is completed.

[Invention of Claim 41] The present invention comprises a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region conductively connected to the channel region through a low concentration source / drain region. In a method of manufacturing a semiconductor device having an LDD thin film transistor and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed therebetween, at least the channel region and the high-concentration source / drain regions are provided. A first step of forming a semiconductor film forming the first electrode portion, and introducing a high-concentration impurity that becomes a donor or an acceptor into a part of the semiconductor film to form the high-concentration source / drain regions and the first It is characterized by including a second step of forming an electrode portion and a third step of forming a gate electrode and a second electrode portion after the second step is completed.

[Invention of Claim 42] According to the present invention, a gate electrode, a gate insulating film, a channel region, an offset region containing the same amount of impurities as the channel region, and a conductive connection to the channel region via the offset region. High concentration sauce
In a method of manufacturing a semiconductor device having an offset thin film transistor having a drain region and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed therebetween, at least the channel region and the capacitor Concentration source
A first step of forming a semiconductor film forming the drain region and the first electrode portion, and introducing a high concentration impurity as a donor or an acceptor into a part of the semiconductor film to form the high concentration source / drain regions It is characterized by including a second step of forming the first electrode portion and a third step of forming a gate electrode and a second electrode portion after the second step is completed.

[Invention of Claim 43] The present invention relates to a gate electrode, a gate insulating film, a channel region, and a high-concentration first conductivity type conductively connected to the channel region through a low-concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor having a source / drain region, a gate electrode, a gate insulating film, a channel region, and a high concentration first conductivity type conductive connection to the channel region via a low concentration second conductivity type source / drain region. A method of manufacturing a semiconductor device having an LDD type second conductivity type thin film transistor having two conductivity type source / drain regions, and a capacitive element composed of a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween. And at least the channel region of the LDD type first conductivity type thin film transistor, the low concentration first conductivity type source / drain region, and the LD
A channel region of the D-type second conductivity type thin film transistor,
A first step of forming a semiconductor film forming the first electrode portion, and introducing a low concentration first conductivity type impurity into a part of the semiconductor film to form the low concentration first conductivity type source / drain regions. It is characterized by including a second step of forming the first electrode portion and a third step of forming a gate electrode and a second electrode portion after the second step is completed.

[Invention of Claim 44] The present invention provides a high-concentration first-conductivity type which is conductively connected to a gate electrode, a gate insulating film, a channel region, and a low-concentration first-conductivity type source / drain region. An LDD type first conductivity type thin film transistor having a source / drain region, a gate electrode, a gate insulating film, a channel region, and a high concentration first conductivity type conductive connection to the channel region via a low concentration second conductivity type source / drain region. A method of manufacturing a semiconductor device having an LDD type second conductivity type thin film transistor having two conductivity type source / drain regions, and a capacitive element composed of a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween. And at least the channel region of the LDD type first conductivity type thin film transistor, the high-concentration first conductivity type source / drain region, and the LD
A channel region of the D-type second conductivity type thin film transistor,
A first step of forming a semiconductor film forming the first electrode portion; and a high concentration first conductivity type source / drain region by introducing a high concentration first conductivity type impurity into a part of the semiconductor film. It is characterized by including a second step of forming the first electrode portion and a third step of forming a gate electrode and a second electrode portion after the second step is completed.

[Invention of Claim 45] The present invention is the method of manufacturing a semiconductor device according to any one of claims 43 to 44, wherein the low concentration first conductivity type source / drain region of the LDD type first conductivity type thin film transistor is used. Low-concentration first-conductivity-type impurity introduction step of introducing a first-conductivity-type impurity into the semiconductor film at a low concentration to form a low-concentration second-conductivity-type source / drain of the LDD second-conductivity-type thin film transistor One of the low-concentration second-conductivity-type impurity introduction steps of introducing the second-conductivity-type impurities into the semiconductor film at a low concentration to form a region is performed without forming a mask,
Regarding the conductivity type and the substantial impurity concentration of the region into which both the first conductivity type impurity and the second conductivity type impurity are introduced, the introduction amount of the first conductivity type impurity and the second conductivity type impurity It is characterized by being defined by the difference of.

[Invention of Claim 46] The present invention provides a high-concentration gate electrode, a gate insulating film, a first channel region, and a high-concentration conductive connection to the first channel region via a low-concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor comprising a first conductivity type source / drain region;
The gate electrode, the gate insulating film, the second channel region, the high concentration second conductivity type source / drain region, and the second region between the second channel region end and the high concentration second conductivity type source / drain region end. A semiconductor device having an offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of a channel region, and a capacitive element including a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween. In the manufacturing method, a first step of forming at least the first channel region, the low-concentration first conductivity type source / drain region, the second channel region, and a semiconductor film forming the first electrode portion, A second step of introducing the first-conductivity-type impurity into a part of the semiconductor film at a low concentration to form the low-concentration first-conductivity-type source / drain regions and the first electrode portion, and after the second step is completed Gate Characterized in that it comprises a third step of forming a pole and the second electrode portion.

[Invention of Claim 47] The present invention provides a gate electrode, a gate insulating film, a first channel region, and a high concentration conductive connection to the first channel region via a low concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor comprising a first conductivity type source / drain region;
The gate electrode, the gate insulating film, the second channel region, the high concentration second conductivity type source / drain region, and the second region between the second channel region end and the high concentration second conductivity type source / drain region end. A semiconductor device having an offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of a channel region, and a capacitive element including a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween. In the manufacturing method, a first step of forming a semiconductor film forming at least the first channel region, the high-concentration first conductivity type source / drain region, the second channel region, and the first electrode portion, A second step of introducing a high-concentration first-conductivity-type impurity into a part of the semiconductor film to form the high-concentration first-conductivity-type source / drain regions and the first electrode portion, and after the second step Gate Characterized in that it comprises a third step of forming a pole and the second electrode portion.

[Invention of Claim 48] The present invention relates to a gate electrode, a gate insulating film, a first channel region, and a high concentration conductive connection to the first channel region through a low concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor comprising a first conductivity type source / drain region;
The gate electrode, the gate insulating film, the second channel region, the high concentration second conductivity type source / drain region, and the second region between the second channel region end and the high concentration second conductivity type source / drain region end. A semiconductor device having an offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of a channel region, and a capacitive element including a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween. In the manufacturing method, a first step of forming a semiconductor film forming at least the first channel region, the second channel region, the high-concentration second conductivity type source / drain region, and the first electrode portion; A second step of introducing a second conductivity type impurity at a high concentration into a part of the semiconductor film to form the high concentration second conductivity type source / drain regions and the first electrode portion, and after the second step is completed. Gate Characterized in that it comprises a third step of forming a pole and the second electrode portion.

[0079]

Embodiments of the present invention will be described with reference to the drawings. Each of the embodiments described below is an example in which the semiconductor device according to the present invention is applied to a drive circuit built-in active matrix substrate in a liquid crystal display device.
However, the semiconductor device of the present invention can be applied to a semiconductor device formed on an LSI or a ceramic substrate in addition to the active matrix substrate. In addition, since any active matrix substrate described below has substantially the same basic structure as that of the active matrix substrate shown in FIG. 29 such as a TFT, the same reference numerals are given to portions having corresponding functions in the following description. There is. In this example, the first conductivity type is N type and the second conductivity type is P type. However, of course, the first conductivity type is P type.
The second conductivity type may be N type.

Each of the embodiments discloses a semiconductor device in which the electrical characteristics of each TFT are improved by a minimum number of manufacturing steps and a method of manufacturing the semiconductor device. To 2 and the groups of Examples 3 to 16.

Examples 1 and 2 correspond to the invention according to claims 1 to 26. That is, it is based on a structure having TFTs of the first conductivity type and the second conductivity type on the same substrate. On the other hand, Embodiments 3 to 16 correspond to the inventions according to claims 27 to 48. That is, it is based on a structure having a TFT and a capacitive element on the same substrate.

[Embodiment 1] (Structure of Active Matrix Substrate) FIG. 1 schematically shows the structure when the semiconductor device according to the present invention is applied to a drive circuit built-in active matrix substrate in a liquid crystal display device. It is a sectional view shown in FIG.

In FIG. 1, three types of TF are provided on the surface side of the insulating substrate 2 which is the base of the active matrix substrate 1.
T is formed, of which the one shown on the right side is the first conductivity type pixel TFT 10 (first conductivity type TFT),
In the center is the TFT for the first conductivity type drive circuit.
20 (first conductivity type TFT), and shown on the left side is a second conductivity type drive circuit TFT 30 ′ (second conductivity type TFT). Of these TFTs, the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT 3
Reference numeral 0'constitutes a drive circuit inverter or the like as a CMOS circuit. That is, the active matrix substrate 1 shown in FIG. 1 is a semiconductor device having a first conductivity type TFT and a second conductivity type TFT.

As shown in FIG. 2A, the liquid crystal display device is
On the active matrix substrate, there is a pixel region defined by signal lines 90 and scanning lines 91, and there is a liquid crystal capacitor 94 of a liquid crystal cell to which an image signal is input via a pixel TFT 92. For the signal line 90,
A data driver unit 82 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is formed on the active matrix substrate.
For the scanning line 91, the scanning driver unit 83 including the shift register 88 and the level shifter 89 is formed on the active matrix substrate. A storage capacitor 40 is also formed in the pixel region between the scanning line of the previous stage. Here, the TFT for the drive circuit includes a shift register,
Although used for level shifters and analog switches, a shift register will be described as an example. Shift register 8
In Nos. 4 and 88, as shown in the two-stage inverter in FIG. 2B, the first conductivity type TFTs n1 and n2 and the second conductivity type Tn are provided.
A CMOS circuit is constituted by FTp1 and p2, respectively. Of these TFTs, the first conductivity type TFTn
1 and n2 are TFTs for the drive circuit of the first conductivity type shown in FIG.
20 corresponding to the second conductivity type TFTs p1 and p2 shown in FIG.
Corresponding to the second conductivity type drive circuit TFT 30 'shown in
The pixel TFT 92 is a first conductivity type pixel T shown in FIG.
Corresponds to FT10.

Again referring to FIG. 1, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20.
Has channel regions 13 and 23 for forming channels between the source / drain regions 11, 12, 21 and 22, and these channel regions 13 and 23 have a low concentration of the second conductivity type impurity (mainly, In the example, it contains boron (B), aluminum (Al), gallium (Ga), indium (In), and other acceptor impurities that exhibit P-type conductivity. The first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 are opposed to the end portions of the gate electrodes 15 and 25 via the gate insulating films 14 and 24 and are of the first-conductivity type low. Concentration source / drain regions 111 _, 12
1, 211, 221, and source / drain electrodes 16, 1
First-conductivity-type high-concentration source / drain regions 112, 122, 212, 22 to which 7, 26, 27 are electrically connected
Have two. In this example, since the N-type TFT is used as the first conductivity type TFT, the N-type impurities contained in the source / drain regions are phosphorus (P) and arsenic (As) exhibiting N-type conductivity. , Antimony (Sb), etc.

On the other hand, the second conductivity type drive circuit TFT 3
Reference numeral 0'denotes a channel region 33 containing a low-concentration second conductivity type impurity, and an offset region 311 'facing the end of the gate electrode 35 with the same impurity concentration as the channel region through the gate insulating film 34. 321 'and second-concentration high-concentration source / drain regions 312, 322 to which the source / drain electrodes 36, 37 are electrically connected.

Channel regions 13 and 2 of both conductivity type TFTs
3, 33, and source / drain regions 11, 12, 2
1, 22, 31, 32 are made of semiconductor films such as silicon (Si) and germanium (Ge). As the type of semiconductor film, in addition to the film made of these Group IV elements,
Silicon-germanium (Si _x Ge _1-x ; 0 <x <
1), Silicon Carbide (Si _x C _1-x ; 0 <x
<1), germanium carbide (Ge _x C _1-x ;
Group IV element composites such as 0 <x <1 and gallium arsenide (G
aAs), indium antimony (InSb), etc., a complex of a Group 3 element and a Group 5 element, and further cadmium.
A composite of a Group 2 element such as selenium (CdSe) and a Group 5 element is also possible. The physical state of these semiconductors can be a single crystal state, a polycrystalline state, a microcrystalline state, a mixed crystal state, an amorphous state, or the like. In this example, a polycrystalline silicon film (poly-Si film) is used as a semiconductor film.

In the active matrix substrate 1 thus constructed, the channel regions 13, 23 and 33 are all channel-doped with a low concentration of boron ions, so that the impurity concentration is about 1 × 10 ¹⁶ cm ^{−. 3} to about 5x
It is a low-concentration second conductivity type region of about 10 ¹⁷ cm ⁻³ .

In the drive circuit section of the present invention, the CMOS
Even when the circuits are connected in multiple stages, the offset type or LDD structure TFTs are used, so that the parasitic capacitance between the gate electrode and the source / drain region is reduced.
Therefore, high speed operation is possible. Furthermore, by reducing the transistor size (shortening the channel length),
The on-current increases. Along with this, the transistor capacity between the gate and the channel is also reduced, and extremely high speed operation is realized. Moreover, as will be described later, since impurities for forming a low concentration region are introduced into the source / drain regions in the same step as the channel doping, the number of manufacturing steps of the active matrix substrate 1 can be reduced. There is also.

In this example, the channel doping is performed with the second conductivity type impurities, but even when the first conductivity type impurities are channel doped, high speed operation and reduction in the number of manufacturing steps can be achieved.

The first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 ′ are provided on the front surface side of the channel regions 13, 23, 33. The gate electrodes 15, 25 and 35 are provided to face each other through the gate insulating films 14, 24 and 34 (silicon oxide film having a thickness of about 1200 Å), and each T
Between the FTs, the channel regions 13, 23, and 33 may have the same length and width to ensure the balance of transistor capacitance.

In the active matrix substrate 1, the source / drain regions 11, 12, 21, 22 are formed on the gate insulating films 14, 24 with respect to the end portions of the gate electrodes 15, 25.
The low-concentration source / drain regions 111, 121, 211, and 221 of the first conductivity type are provided in a portion facing each other through, and the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are , LDD structure.

On the other hand, the source / drain regions 3
In the offset regions 31 and 32, the portions facing the ends of the gate electrode 35 with the gate insulating film 34 interposed therebetween are offset regions 31.
1 ', 321', and this offset area 311 ',
321 'is a low-concentration second conductivity type region having an impurity concentration of about 1 × 10 ¹⁶ cm ^-3 to about 5 × 10 ¹⁷ cm ^-3 , like the channel region 33.

In the source / drain regions 11, 12, 21, 22 of the first-conductivity-type pixel TFT 10 and the first-conductivity-type driver circuit TFT 20, the first-conductivity-type low-concentration source / drain regions are formed. 111, 121, 211, 22
Regions other than 1 are high-concentration source / drain regions 112, 122, 212, 222 of the first conductivity type having an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ to about 5 × 10 ²⁰ cm ⁻³ . Source / drain electrodes 16, 17, 2 such as signal lines and pixel electrodes for each TFT in the high concentration region
6 and 27 are electrically connected through the contact hole of the interlayer insulating film 4.

In the source / drain regions 31 and 32 of the second-conductivity-type drive circuit TFT 30 ′, the portion adjacent to the offset regions 311 ′ and 321 ′ has an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ to about 5. High-concentration source / drain regions 312 and 322 of the second conductivity type of about 10 ²⁰ cm ⁻³ , and source / drain electrodes 36 and 37 such as signal lines and pixel electrodes are provided between these high-concentration regions as interlayers. Insulation film 4
It is electrically connected through the contact hole.

In the present invention, the second conductivity type TFT has the same conductivity (P-type conductivity) in all of the source / drain region, the offset region and the channel region, and is of the first conductivity type. In the TFT, the channel region has the opposite conductivity (P-type conductivity) to the source / drain region and the LDD region (N-type conductivity). On the contrary, in the second conductivity type TFT, the source / drain region (P
(Type conductivity), the offset region and the channel region have opposite conductivity (N-type conductivity), and the first conductivity type TFT has the same conductivity in all of the source / drain region, the LDD region, and the channel region. (N-type conductivity) is also possible.
However, in this case, when the transistor is turned on, the second conductivity type T
FT channel (inverted and second conductivity / P-type conductivity)
And a weak PN junction is formed between the offset region and the source / drain region (first conductivity / N-type conductivity), which limits the off current.

(TFT On / Off Current Characteristics) In the on / off current characteristics of the TFT thus constructed, which T
Also in the FT, the portion facing the end portions of the gate electrodes 15, 25, 35 is a low concentration region (first conductivity type low concentration source / drain regions 111, 121, 211, 221, or offset regions 311 ', 321'. ), The electric field strength at the drain end is relaxed. Therefore, the drain current-gate voltage characteristics of the first conductivity type TFT (first conductivity type pixel TFT 10 and first conductivity type drive circuit TFT 20) of the LDD structure are shown in FIG.
As shown in FIG. 3 and compared therewith, a second conductivity type TFT having an offset gate structure (a second conductivity type drive circuit TFT
The drain current-gate voltage characteristics of 30 ') are shown by dotted line L4'.
As shown by, the off current of each TFT is extremely small.

In FIG. 31A, the solid line L21 shows the withstand voltage characteristics of the first conductivity type TFT (first conductivity type pixel TFT 10 and first conductivity type drive circuit TFT 20) of the LDD structure. As shown by the solid line L22 in FIG. 31B, the withstand voltage characteristic of the second conductivity type TFT of the LDD structure shows that the LDD structure TFT has a self-aligned TF.
Since the withstand voltage is higher than that of T, not only can the channel length be shortened, but the TF of the offset gate structure can also be used.
The withstand voltage characteristic of the T (second conductive type drive circuit TFT 30 ') is further superior to the withstand voltage characteristic of the LDD structure TFT. Therefore, the second-conductivity-type drive circuit TFT 30 'also has a much higher withstand voltage than the self-aligned structure TFT, so that the channel length can be further shortened. Therefore, high speed operation can be realized by reducing the transistor capacitance.

In this example, the first conductivity type is the first conductivity type and the second conductivity type is the second conductivity type, but they may be reversed. That is, the pixel TFT may be of the second conductivity type.
Further, the impurity concentrations of the offset regions 311 'and 321' and the channel region 33 of the second conductivity type drive circuit TFT 30 'are set to about 1 × 10 ¹⁶ cm ^-3 to about 5 × 10 ¹⁷ cm ^-3 . This concentration also has a property that it should be set to an optimum value according to the specifications of the active matrix substrate 1 and the dimensions of the channel length, and is not limited to the above numerical values.

(Method of Manufacturing TFT) The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.

As shown in FIG. 4A, among the surfaces of the insulating substrate 2 such as a quartz substrate, the first conductivity type pixel TFT 10,
Low-concentration second conductivity type silicon films 10a, 20a, 30a and gate insulating films 14, 24, 34 are formed in regions where the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT 30 'are formed. To do.

First, an intrinsic polysilicon film is formed on the surface of an insulating substrate 2 such as a glass substrate or a quartz substrate by the LPCVD method or the plasma CVD method, and then the polysilicon film is formed by the photolithography method. After patterning, the island-shaped silicon films 10a, 20
a and 30a (silicon film forming step). The polysilicon film may be formed by growing crystal grains by a laser annealing method or a solid phase growth method after forming an amorphous silicon film.

Next, the island-shaped silicon films 10a, 20a,
30a, thermal oxidation method, TEOS-CVD method, LP
The gate insulating film 14 or 2 made of a silicon oxide film having a thickness of about 200 Å to about 1500 Å, for example, about 1200 Å, is formed by a CVD method, a plasma CVD method, an HTO method, or the like.
4, 34 are formed (gate insulating film forming step).

After that, for example, the gate insulating film 14,
The thickness of 24 and 34 is about 1200 angstroms and 1
In the case of impurities of about × 10 ¹⁷ cm ^-3 , 1 × 10
Channel doping is performed by implanting boron ions (second conductivity type impurities) with a dose amount of ¹² cm ⁻² (channel doping step / low concentration second conductivity type impurity introducing step / first impurity introducing step).

As a result, the island-shaped silicon films 10a and 20 are formed.
Both a and 30a become low concentration second conductivity type silicon films 10a, 20a and 30a.

Next, as shown in FIG. 4B, the gate electrode 1 made of doped silicon, a silicide film, a metal thin film or the like is formed on the surfaces of the gate insulating films 14, 24 and 34.
5, 25 and 35 are formed (gate electrode forming step).

Next, the formation region of the second conductivity type pixel TFT 30 'is covered with the resist mask 61, while the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TF are used.
The formation region of T20 is opened (first mask formation step). In this state, the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 is Conductive impurities, such as phosphorus ions, about 1.0 × 101
Ion implantation is performed with a dose amount of 3 cm-2 to form the gate electrode 1.
The impurity concentration is about 1.0 × in a self-aligning manner with respect to 5, 25
Low concentration source / drain regions 11 and 1 of 10 ¹⁸ cm ^-3
2, 21, and 22 are formed (low-concentration first conductivity type impurity introduction step / second impurity introduction step). The portions where no impurities are introduced become the channel regions 13 and 23.

After that, the resist mask 61 is removed.

Next, as shown in FIG. 4C, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT.
In addition to 20, the resist mask 62 that broadly covers the gate electrode 35 of the second-conductivity-type drive circuit TFT 30 'is formed (second mask forming step). Here, the distance between the end of the resist mask 62 and the end of the gate electrode 35 is preferably about 0.5 μm to 2.0 μm.

In this state, second conductivity type impurities, for example, boron ions are ion-implanted at a dose amount of 1.0 × 10 ¹⁵ cm ^-2 (high-concentration second conductivity type impurity introduction step / third impurity introduction). Process).

As a result, the second-conductivity-type impurity concentration is 1.0 × 10 ²⁰ c in the low-concentration second-conductivity-type silicon film 30a.
m ^-3 second conductivity type high concentration source / drain region 31
2, 322 are formed. On the other hand, the portion of the low-concentration second-conductivity-type silicon film 30a covered by the resist mask 62 has the second-conductivity-type impurity concentration of about 1.0 × 1.
The offset regions 311 'and 321' are 0 ¹⁷ cm ^-3 . Of course, the channel region 33 remains as a low-concentration second-conductivity-type region having a second-conductivity-type impurity concentration of about 1.0 × 10 ¹⁷ cm ⁻³ .

In this way, the second conductivity type drive circuit T
Form FT 30 '. After that, the resist mask 6
Remove 2.

Next, as shown in FIG. 4D, in addition to the formation region of the second-conductivity-type drive circuit TFT 30 ', the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT are formed. T
A resist mask 63 is formed to widely cover the gate electrodes 15 and 25 of the FT 20 (third mask forming step).
Again, the end of the resist mask 63 and the gate electrode 1
A suitable distance from the ends of Nos. 5 and 25 is 0.5 μm to 2.0 μm.

In this state, impurities of the first conductivity type, for example, phosphorus ions are ion-implanted at a dose amount of 1.0 × 10 ¹⁵ cm ^-2 (high-concentration first conductivity-type impurity introduction step / 4th impurity introduction step). ).

As a result, the first-conductivity-type high-concentration source / drain having the first-conductivity-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ is formed in the low-concentration source-drain regions 11, 12, 21, and 22. Regions 112, 122, 212, 222 are formed. On the other hand, low concentration source / drain regions 11 and 12,
Of the parts 21 and 22, the part covered with the resist mask 63 has the first conductivity type impurity concentration of about 1.0 × 10.
¹⁸ cm ^-3 first conductivity type low concentration source / drain region 1
11, 121, 211, 222. Of course, the channel regions 13 and 23 have a second conductivity type impurity concentration of about 1.0 ×.
The low-concentration second conductivity type region of 10 ¹⁷ cm ⁻³ remains.

In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 63 is removed.

Thereafter, as shown in FIG. 1, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter,
Source / drain electrodes 1 by forming contact holes
When 6, 17, 26, 27, 36, and 37 are formed, the source of the TFT having the CMOS structure is formed by three mask forming steps for forming the resist masks 61 to 63 and four impurity introducing steps. The drain region and the channel region can be formed, and the active matrix substrate 1 can be manufactured.

As described above, in the method of manufacturing the active matrix substrate 1 of this example, the second conductivity type drive circuit TFT 3 is used.
In 0 ', when making the portion facing the gate electrode 35 the low concentration region, not the LDD structure but the offset gate structure having the same conductivity type and the same concentration as the channel is used. Therefore, as compared with the conventional manufacturing method described with reference to FIGS. 33A to 33E, each of the mask forming step and the impurity introducing step is reduced once.
That is, in this example, the low-concentration second-conductivity-type impurity introduction step is performed at the same time as the channel doping for the channel region of each TFT before the gate electrode formation step, so that all the TFTs are manufactured with the LDD structure. Also, the impurity introduction step can be reduced by one time. Further, the low-concentration second-conductivity-type impurity introducing step is performed at the same time as the channel doping, so
A higher concentration of impurities of the first conductivity type is introduced into the regions to be the source / drain regions of the first conductivity type. Therefore, a mask is not required in the low-concentration second-conductivity-type impurity introducing step, so that the number of mask forming steps can be reduced by one time as compared with the case of manufacturing all the TFTs with the LDD structure. Therefore, the electrical characteristics of the pixel region and the TFT of the drive circuit unit can be improved with the minimum number of manufacturing steps.

(Another TFT Manufacturing Method) The active matrix substrate 1 of this example can also be manufactured by the method described below.

As shown in FIG. 5A, the pixel TFT 1 on the surface of the insulating substrate 2 such as a glass substrate or a quartz substrate.
0, the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT 30 'are formed in the low concentration second conductivity type silicon films 10a, 20a, 30a and the gate insulating films 14, 24, 34. To form.

First, an intrinsic polysilicon film is formed on the surface of an insulating substrate 2 such as a quartz substrate by LPCVD or plasma CVD, and then the polysilicon film is patterned by photolithography. , The island-shaped silicon films 10a, 20a, 30a are formed (silicon film forming step).

Next, the island-shaped silicon films 10a, 20a,
30a, thermal oxidation method, TEOS-CVD method, LP
The gate insulating films 14 and 24 made of a silicon oxide film having a thickness of about 200 Å to about 1500 Å, for example, about 1200 Å, are formed by a CVD method, a plasma CVD method, an HTO method, or the like.
34 is formed (gate insulating film forming step).

Thereafter, channel doping is performed by implanting boron ions (second conductivity type impurities) at a dose of 1 × 10 ¹² cm ^-2 (channel doping step / low concentration second conductivity type impurity introducing step / 1. Second impurity introduction step).

As a result, the island-shaped silicon films 10a and 20 are formed.
Both a and 30a become low concentration second conductivity type silicon films 10a, 20a and 30a.

Next, as shown in FIG. 5B, the gate electrode 1 made of doped silicon, a silicide film, or a metal thin film is formed on the surfaces of the gate insulating films 14, 24, 34.
5, 25 and 35 are formed (gate electrode forming step).

The above steps are the same as those in the manufacturing method described with reference to FIGS.

Next, the second conductivity type drive circuit TFT 3 is formed.
In addition to the formation region of 0 ', the first conductivity type pixel TFT 1
A resist mask 71 that broadly covers the gate electrodes 15 and 25 of the drive circuit TFT 20 of the first conductivity type and 0 is formed (first mask forming step). Also in this case, the distance between the end of the resist mask 71 and the ends of the gate electrodes 15 and 25 is preferably about 0.5 μm to 2.0 μm.

In this state, first conductivity type impurities, for example, phosphorus ions are ion-implanted at a dose amount of 1.0 × 10 ¹⁵ cm ^-2 (high-concentration first conductivity type impurity introduction step / second impurity introduction step). ).

As a result, the first-conductivity-type impurity concentration is 1.0 × in the low-concentration second-conductivity-type silicon films 10a and 20a.
High-concentration source / drain regions 112, 122, 212, 222 of the first conductivity type of 10 ²⁰ cm ⁻³ are formed. On the other hand, in the low-concentration second-conductivity-type silicon films 10a and 20a, the portion covered with the resist mask 71 has a second-conductivity-type impurity concentration of about 1.0 × 10 ¹⁷ cm ⁻³ . It remains the conductivity type region.

After that, the resist mask 71 is removed.

Next, as shown in FIG. 5C, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT.
In addition to 20, a resist mask 72 is formed to widely cover the gate electrode 35 of the second-conductivity-type drive circuit TFT 30 '(second mask forming step). Here, the distance between the end of the resist mask 72 and the end of the gate electrode 35 is preferably about 0.5 μm to 2.0 μm.

In this state, for example, boron ions are added to 1.0
Ion implantation is performed at a dose of × 10 ¹⁵ cm ^-2 (high-concentration second conductivity type impurity introduction step / third impurity introduction step).
As a result, in the low-concentration second conductivity type silicon film 30a,
Second-conductivity-type high-concentration source / drain regions 312 and 322 having a second-conductivity-type impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed. On the other hand, the low concentration second conductivity type silicon film 30a
Among them, the portions covered with the resist mask 72 become the offset regions 311 ′ and 321 ′ having the second conductivity type impurity concentration of about 1.0 × 10 ¹⁷ cm ⁻³ as they are. Of course, the channel region 33 has a second conductivity type impurity concentration of about 1.0 × 1.
The low-concentration second conductivity type region of 0 ¹⁷ cm ⁻³ remains as it is.

In this way, the second conductivity type drive circuit T
Form FT 30 '. After that, the resist mask 7
Remove 2.

Next, the formation region of the second conductivity type pixel TFT 30 'is covered with the resist mask 73, while the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TF are used.
The formation region of T20 is opened (third mask formation step). In this state, the first conductivity type pixel T
About 1.0 × 10 ¹³ phosphorus ions, for example, are applied to the formation region of the FT 10 and the drive circuit TFT 20 of the first conductivity type.
Ion implantation is performed with a dose amount of cm ⁻² (low-concentration first conductivity type impurity introduction step / 4th impurity introduction step).

As a result, the source / drain regions 10, 2
0 is the first conductivity type low concentration source / drain regions 111, 121, 2 having a first conductivity type impurity concentration of about 1.0 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with respect to the gate electrodes 15, 25.
11, 221 are formed. The portions where no impurities are introduced become the channel regions 13 and 23.

In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 73 is removed.

Thereafter, as shown in FIG. 1, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter,
Source / drain electrodes 1 by forming contact holes
When 6, 17, 26, 27, 36 and 37 are formed, the source of the TFT having the CMOS structure is formed by three mask forming steps for forming the resist masks 71 to 73 and four impurity introducing steps. The drain region and the channel region can be formed, and the active matrix substrate 1 can be manufactured.

Even in such a manufacturing method, in the second conductivity type drive circuit TFT 30 ′, when the portion facing the gate electrode 35 is set to the low concentration region, it is not the LDD structure but the same conductivity type as the channel. The offset gate structure has the same concentration. Therefore, as shown in FIG.
Compared with the conventional manufacturing method described with reference to (e),
The number of mask formation steps and the number of impurity introduction steps are reduced once. Therefore, the electrical characteristics of the pixel region and the TFT of the drive circuit unit can be improved with the minimum number of manufacturing steps.

[Embodiment 2] In this embodiment, the on-current balance between the first conductivity type TFT and the second conductivity type TFT is improved by optimizing the channel doping condition for each TFT. Since the basic structure and the manufacturing method thereof are substantially the same as those of the first embodiment,
The basic structure will be briefly described with reference to FIG. 1, and the manufacturing method thereof will be omitted.

Also in the present example, as shown in FIG. 1, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 have source / drain regions 11, 12, 2
Channel region 1 for forming a channel between 1 and 22
3 and 23, and these channel regions 13 and 23 are
Low-concentration second conductivity type impurities (in this example, boron (B), aluminum (Al), gallium (G) having P-type conductivity)
a), acceptor impurities such as indium (In))
Is included. The first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 include a gate electrode 15,
First-conductivity-type low-concentration source / drain region 11 facing the end portion of 25 through gate insulating films 14 and 24.
1, 121, 121, 122 and the high-concentration source / drain regions 112, 122, 21 of the first conductivity type in which the source / drain electrodes 16, 17, 26, 27 are electrically connected.
2 and 222. In this example, the first conductivity type TF
Since an N-type TFT is used as T for explanation, the first conductivity type impurities contained in the source / drain regions are phosphorus (P), arsenic (As), antimony (S) having N-type conductivity.
b) etc.

On the other hand, the second conductivity type drive circuit TFT 3
Reference numeral 0'denotes a channel region 33 containing a low-concentration second conductivity type impurity, and an offset region 311 'facing the end of the gate electrode 35 with the same impurity concentration as the channel region through the gate insulating film 34. 321 'and second-concentration high-concentration source / drain regions 312, 322 to which the source / drain electrodes 36, 37 are electrically connected.

In the thus constructed active matrix substrate 1, the channel regions 13, 23 and 33 are all channel-doped with a low concentration of boron ions as in the case of the first embodiment, and the low concentration second conductivity type region is formed. However, the impurity concentration is set so as to satisfy the conditions described below, for example, about 5 × 10 ¹⁶ cm ⁻³ to about 1 × 10 ¹⁸ cm.
^-3 . Generally, the second conductivity type drive circuit TFT 30 'having the offset structure tends to have a slightly smaller on-current than the first conductivity type drive circuit TFT 20 having the LDD structure. The main reason for this is the difference in the specific resistance between the offset structure and the LDD structure. Moreover, when the second conductivity type is the second conductivity type and the first conductivity type is the first conductivity type, more holes are generated. This is also due to the fact that the mobility is smaller than that of electrons.

Therefore, in this example, by setting a large amount of impurities to be channel-doped, the second conductivity type (second conductivity type) drive circuit TFT 30 'is set to the weak depletion mode, and The drive circuit TFT 20 of one conductivity type (which is the first conductivity type) is set to the weak enhancement mode. As a result, the second conductivity type drive circuit TFT 3
The 0'offset regions 311 'and 312' are substantially LDD regions having low resistance. Moreover, in the ON state (for example, in the second conductivity type drive circuit TFT 30 ',
Source / drain voltage V _DS = -5V, gate voltage V _GS =
In the driving circuit TFT 20 of −10 V, the first conductivity type, the source / drain voltage V _DS = + 5 V, the gate voltage V _GS = +
It is possible to make the level of the on-current in the 10 V state) uniform between the TFTs of both conductivity types.

That is, as shown in FIG. 6, a first conductivity type TFT
The drain current-gate voltage characteristics of (the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20) are indicated by a solid line L5, and the second conductivity type TFT (second conductivity type drive circuit TFT 30) is shown. The drain current-gate voltage characteristic of ′) is indicated by a dotted line L6, and the source / drain voltage of the first conductivity type TFT (first conductivity type drive circuit TFT 20) is VDS1, the gate voltage is VGS1, and the source / drain current is Let IDS1 be the source / drain voltage of the second conductivity type TFT (the second conductivity type drive circuit TFT 30 ') be V _DS2 , the gate voltage be V _GS2 and the source / drain current be I _DS2 , then | V _DS1 ｜ = ｜ V _{DS 2} ｜, V _GS1
= V _GS2 = 0, so that I _DS2 > I _DS1
Second conductivity type TFT (second conductivity type drive circuit TFT 3
0 ') offset areas 311', 321 ', and each T
The second conductivity type impurity concentration is set in the channel regions 13, 23, 33 of the FT.

In other words, under the condition of | V _DS1 | = | V _DS2 |, the solid line L5 representing the source / drain current I _DS1 of the first conductivity type TFT and the source / drain current of the second conductivity type TFT Intersection R (V with the dotted line L6 representing I _DS2
The value of the gate voltage corresponding to _GS1 = V _GS2 and I _DS1 = I _DS2 ) is obtained in the TFT 20 for the drive circuit of the first conductivity type.
A gate voltage region corresponding to the on-region side of the source / drain current I _DS1 (a gate voltage region corresponding to the off-region side of the source / drain current I _DS2 in the second-conductivity-type drive circuit TFT 30 ′), that is, It is in the positive gate voltage region.

For reference, FIG. 6 shows the first-conductivity-type TFT according to the first embodiment shown in FIG. 3 (first-conductivity-type pixel TFT 10 and first-conductivity-type drive circuit TFT 20).
Of the drain current-gate voltage characteristic of the second conductivity type TFT (second conductivity type driving circuit TFT 30 ') is indicated by a chain line L4' in Example 1. There is.

As described above, in this example, the offset regions 311 'and 312' of the second conductivity type drive circuit TFT 30 'are provided.
Is a LDD region having a substantially small resistance, thereby reducing the parasitic resistance caused by this portion. Further, when comparing the offset region and the LDD region, it is general that the resistance value is smaller in the LDD region, but in this example, a weak depletion is applied to the second conductivity type drive circuit TFT 30 'of the offset structure. The mode and the LDD structure of the first conductivity type drive circuit TFT 20 is in the weak enhancement mode. Therefore, the gate bias value in the ON state of the offset structure of the second conductivity type drive circuit TFT 30 '. Can be larger than the gate bias value in the ON state of the drive circuit TFT 20 of the first conductivity type having the LDD structure. Explaining with the example shown in FIG. 6,
For example, the position of the intersection R is set to V _GS = + 2V, and the ON state is set to | V _GS | = 10V. In this case, the gate bias value in the ON state of the drive circuit TFT 30 'of the second conductivity type having the offset structure corresponds to about -12 V in the characteristic represented by the alternate long and short dash line L4', and the first conductivity type of the LDD structure is obtained. Since the gate bias value in the ON state of the drive circuit TFT 20 is equivalent to about +8 V in the characteristic represented by the alternate long and short dash line L3, it is possible to balance the ON currents. In this method, it is also possible to make the transistor capacitances of the second conductivity type drive circuit TFT 30 'of the offset structure and the first conductivity type drive circuit TFT 20 of the LDD structure equal. . That is, the second conductivity type drive circuit T
The on-current balance between the FT 30 'and the drive circuit TFT 20 of the first conductivity type is ensured by channel doping (the amount of doping in the offset regions 311' and 321 '). By making the channel length / channel width equal between the two, it is possible to secure the balance of the transistor capacitance between the two TFTs. Therefore, since the transistor capacities are the same and the on-currents are the same, it is possible to obtain a CMOS circuit that operates stably at high speed.

Since the method of manufacturing the TFT having such a structure is almost the same as that of the first embodiment, the description of the manufacturing method will be omitted.
The amount of impurities introduced into each region is set to an optimum value corresponding to the channel doping amount. The optimum channel doping amount varies depending on the quality of the gate insulating film and the quality of the base protective film (protective film between the semiconductor layer and the substrate).

[Modifications of Embodiments 1 and 2] As in this embodiment,
The gate insulating films 14, 24, 34 are formed on the silicon films 10a, 20a, 30a if the method is to form the offset regions 311 ', 321' so that the portion facing the gate electrode 35 is a low concentration region. After that, instead of the method of implanting boron ions (impurities of low concentration second conductivity type) in the low concentration second conductivity type silicon film forming step, the gate insulating film 1 is applied to the silicon films 10a, 20a and 30a.
Before forming 4, 24, 34, boron ions may be implanted in the low-concentration second conductivity type silicon film forming step, and then the gate insulating films 14, 24, 34 may be formed.

In addition, the intrinsic silicon films 10a, 20a, 30
After forming a, instead of the method of implanting the low-concentration second-conductivity-type impurities in the low-concentration second-conductivity-type silicon film forming step, a low-concentration boron doping is performed using a mixed gas of B2H6 and SiH6. The silicon film (doped silicon film / doped semiconductor film) is formed as the low-concentration second conductivity type silicon films 10a, 20a, 30a by the CVD method, and then the gate insulating films 14, 24, 34 are formed thereon. After that, the steps shown in FIGS. 4B to 4D or the steps shown in FIGS. 5B to 5D may be performed.

Further, in the active matrix substrate manufacturing method of this embodiment, in any case, at least the low concentration second conductivity type impurity introducing step, the gate electrode forming step, the low concentration first conductivity type impurity introducing step, and the high concentration The first-conductivity-type impurity introduction step and the high-concentration second-conductivity-type impurity introduction step are performed. The order of the steps is as follows: low-concentration second-conductivity-type impurity introduction step, gate electrode formation step If the channel doping of the channel region of each TFT is performed at the same time as the above, and the low-concentration first conductivity type impurity introduction step is performed using the gate electrode as a mask after the gate electrode formation step, the conditions shown in Table 1 are used. Any process sequence from A to condition T may be used.

[0152]

[Table 1]

That is, in Table 1, the low-concentration second conductivity type impurity introduction step is C / D (P ⁻ ), and the gate electrode formation step is Gat.
e, the low concentration first conductivity type impurity introduction step is indicated by N ⁻ , the high concentration first conductivity type impurity introduction step is indicated by N ⁺ , and the high concentration second conductivity type impurity introduction step is indicated by P ^+. A
Is the process sequence described with reference to FIG. 4, and the condition C therein is the process sequence described with reference to FIG.

The low-concentration second-conductivity-type impurity introducing step may be formed by a step of forming a doped semiconductor film containing a low-concentration second-conductivity-type impurity. For example, when doping boron, monosilane (SiH ₄ ) or disilane (S
obtained by i ₂ H ₆₎ at the same time introducing a diborane (B ₂ H _6). When depositing these doped semiconductor films by the LPCPD method, the concentration of the additive such as diborane is
About 0.1 ppm to 100 ppm is preferable, and hydrogen, helium, and nitrogen are suitable as the diluent gas. On the other hand, PEC
In the case of depositing by the VD method, the concentration is the same as above, but helium, argon, etc. are suitable as the diluent gas. Thus, the doped semiconductor film may be deposited and then patterned, and a gate insulating film may be further formed on the surface of the semiconductor film.

As the impurity introducing method, for example, a method of implanting all ions generated from the dopant gas without mass separation, that is, a so-called ion doping method may be used. In this method, for example, when implanting impurities of the first conductivity type to a high concentration, a mixed gas containing PH ₃ of about 1% to about 10% and the balance of hydrogen gas or helium gas is used. All ions generated from are implanted without mass separation. On the other hand, in the case of implanting the first conductivity type impurity in a low concentration, PH ₃ is about 0.01% to
After implanting all the ions generated from a mixed gas containing about 1% and the rest being hydrogen gas without mass separation, the ions generated from pure hydrogen gas are injected without mass separation, and It is preferable to terminate the asymmetric bond. Further, regarding the method of introducing impurities, in addition to the ion implantation method and the ion doping method, the plasma doping method,
A laser doping method or the like may be used.

In the active matrix substrate 1 of this example,
The impurity concentration of the first-conductivity-type low-concentration source / drain regions 111, 121, 211, and 221 of the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 is about 1.0 × 10 ¹⁸ cm ^{−. 3} and has a high concentration impurity doped source and drain regions 112,122,212,222 of the first conductivity type is approximately 1.0 × 10 ²⁰ cm ^-3, for such concentration, the specifications of the active matrix substrate 1 It is a property that should be set to an optimum value according to the above, and is not limited to the above numerical values. Furthermore, the material of the mask is not limited to the resist mask.

[Embodiment 3] (Structure of Active Matrix Substrate) FIG. 7 is a sectional view schematically showing the structure of a drive circuit built-in type active matrix substrate in the liquid crystal display device of the present embodiment. It is a block diagram which shows the structure of a liquid crystal display device typically.

In FIG. 7, in the active matrix substrate with a built-in drive circuit of the liquid crystal display device of this example, the drive circuit portion, the pixel region, and the storage capacitor in this pixel region are arranged from the left side region to the right side region. As schematically shown in the formation region, the second conductivity type drive circuit TFT 30, the first conductivity type drive circuit TFT 20, and the first conductivity type pixel TFT 1
0 and the storage capacitor 40 are formed on the same insulating substrate 2.

In this example, as shown in FIG. 8, a storage capacitor 40 is formed in the pixel region between the scanning line 91 in the preceding stage, and this storage capacitor 40 stores the charge in the liquid crystal cell (liquid crystal capacitor 94). It has the function of enhancing the retention characteristics. This holding capacity 40
Is the lower layer side electrode portion 40c (first electrode portion) which is obtained by making the silicon film S2 simultaneously formed with the silicon film S1 for forming the pixel TFT 10 conductive, and with respect to the lower layer side electrode portion 40c. The upper layer side electrode portion 45 (second electrode portion) protruding from the preceding scanning line 91 is in an overlapping state.
The storage capacitor 40 is used for the scanning line 9 in the preceding stage in each pixel area.
However, it may be formed with a dedicated capacitance line.

Again, referring to FIG. 7, the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 are all source / drain regions 11. , 12, 21, 22, 31, 32
Channel regions 13 and 2 for forming a channel between
I have 3, 33. These channel regions 13, 2
Channels ^{3 and 33} are low-concentration second conductivity type regions having an impurity concentration of about 1 × 10 ¹⁷ cm ^{−3 because} they are channel-doped with low-concentration boron ions. Therefore, the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT
The threshold voltage (Vth) of 30 is set to a predetermined value. In general, the mobility of holes is smaller than the mobility of electrons. Therefore, conventionally, the on-current of the drive circuit TFT of the second conductivity type is smaller than the on-current of the drive circuit TFT of the first conductivity type. Tended to be significantly smaller. In the present example, such a problem can be almost eliminated by adjusting Vth. Therefore, in the active matrix substrate 1 of this example,
Good balance of on-current between the TFTs forming the CMOS circuit.

The first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 are gate-insulated with respect to the surface side of the channel regions 13, 23, and 33. It has gate electrodes 15, 25 and 35 facing each other through films 14, 24 and 34 (silicon oxide film having a thickness of about 1200 Å).

In the active matrix substrate 1 thus constructed, the source / drain regions 11, 12, 2 are formed.
1, 22, 31, 32 are gate electrodes 15, 25, 35
The low-concentration source / drain regions 111, 1 are formed in the portions facing the ends of the gate insulating films 14, 24, 34, respectively.
21, 211, 221, 311 and 321,
Each TFT has an LDD structure.

The source / drain regions 11, 12, and 2 of the first-conductivity-type pixel TFT 10, the first-conductivity-type driver circuit TFT 20, and the second-conductivity-type driver circuit TFT 30.
Of the regions 1, 22, 31, 32, except for the low concentration source / drain regions 111, 121, 211, 221, 311 and 321, the high concentration source / drain regions having an impurity concentration of about 1 × 10 ²⁰ cm ^−3. 112, 122, 212, 22
2, 312, 322. For these high-concentration regions, the signal line for each TFT, the source of the pixel electrode, etc.
The drain electrodes 16, 17, 26, 27, 36, 37 are electrically connected through the contact holes of the interlayer insulating film 4.

(TFT On / Off Leakage Current Characteristic) The TFT thus constructed has gate electrodes 15, 25 and 35.
Since there is a low concentration region (low concentration source / drain regions 111, 121, 211, 221) facing the end portion of, the electric field strength at the drain end is relaxed. Therefore, FIG. 32 shows a first-conductivity-type TFT (first-conductivity-type pixel TFT 10 and first-conductivity-type drive circuit TF).
The drain current-gate voltage characteristic of T20) is shown by the solid line L3, and the second conductivity type TFT (T for the second conductivity type drive circuit) is shown.
The drain current-gate voltage characteristics of FT30) are shown by the dotted line L4.
As shown by, the off-leakage current of the TFT is extremely small.

In FIG. 31A, the solid line L21 shows the withstand voltage characteristics of the first conductivity type TFT (first conductivity type pixel TFT 10 and first conductivity type drive circuit TFT 20) of the LDD structure. As shown by the solid line L22 in FIG. 31 (b), which shows the withstand voltage characteristic of the second conductivity type TFT of the LDD structure, the TFT of the LDD structure has a self-aligned TF.
Since the withstand voltage between the source and the drain is higher than T, the channel length can be shortened.

(Method for Manufacturing TFT) The active matrix substrate 1 having such a structure can be manufactured by, for example, the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.

First, in order to adjust the Vth of the TFT, impurities are introduced into the semiconductor film at a low concentration. That is, as shown in FIG. 9A, among the surface of the insulating substrate 2 such as a quartz substrate, the pixel TFT 10, the first conductivity type drive circuit TFT 20, the second conductivity type drive circuit TFT 30, and the storage capacitor. In the formation region of 40, for example, the low-concentration second-conductivity-type silicon films 10a, 20a, 30 having an impurity concentration of 1 × 10 ¹⁷ cm ^−3.
a, 40a, the gate insulating films 14, 24, 34, and the dielectric film 44 are simultaneously formed (low concentration second conductivity type silicon film forming step).

To that end, on the surface of the insulating substrate 2, LPCV
After the intrinsic polysilicon film is formed by using the D method or the plasma CVD method, the polysilicon film is patterned by the photolithography method to form the island-shaped silicon films 10a, 20a, 30a, 40a (silicon. Film formation process).

The polysilicon film may be formed by forming crystal grains by a laser annealing method or a solid phase growth method after forming an amorphous silicon film. next,
For the island-shaped silicon films 10a, 20a, 30a, 40a, a thermal oxidation method, a TEOS-CVD method, an LPCVD method,
The thickness is about 12 by plasma CVD method, HTO method, etc.
Gate insulating films 14, 24, 34 made of a silicon oxide film of 00 angstrom and a dielectric film 44 are simultaneously formed (gate insulating film forming step).

Thereafter, channel ions are implanted by implanting boron ions (second conductivity type impurities / second conductivity type impurities) with a dose amount of about 1 × 10 ¹² cm ^-2 (channel doping step / first impurity introduction). Process). As a result, the silicon films 10a, 20a, 30a, 40a become the low-concentration second conductivity type silicon films 10a, 20a, 30a, 40a having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG. 9B, a resist mask 101 is formed which covers the formation region of the second conductivity type drive circuit TFT 30 and slightly widens the formation regions of the gate electrodes 15 and 25. Forming (first mask forming step).

Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁴ cm ^-2 (second impurity introduction step / low concentration first step). Conductive impurity introduction step).

As a result, in the low-concentration second-conductivity-type silicon films 10a and 20a, the region in which phosphorus ions have been implanted has the conductivity type reversed and the impurity concentration is about 1 × 10 ¹⁹ cm ^−3.
Low concentration first conductivity type source / drain regions 11 and 1
It becomes 2, 21, and 22. The low-concentration second-conductivity-type silicon film 40a has an impurity concentration of about 1 × 10 6 because the conductivity type is reversed.
19 cm-3 low-concentration first conductivity type lower layer side electrode portion 40c
(First electrode portion). Further, the portions where no impurities are introduced become the channel regions 13 and 23. After that, the resist mask 101 is removed.

Next, as shown in FIG. 9C, gate electrodes 15, 25 and 35 made of doped silicon or a silicide film are formed on the surfaces of the gate insulating films 14, 24 and 34. At the same time, the upper electrode 4 is formed on the surface of the dielectric film 44.
5 (second electrode portion) is formed (gate electrode forming step). This upper layer side electrode portion 45 may be a part of the signal line in the previous stage. In this way, the storage capacitor 40 in which the lower layer side electrode portion 40c and the upper layer side electrode portion 45 face each other with the dielectric film 44 in between is formed.

Next, a resist mask 102 is formed to cover the formation region of the first-conductivity-type pixel TFT 10, the formation region of the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40 (second mask formation step). ).

Subsequently, boron ions are added to about 1 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity-type silicon film 30a has a low-concentration second-conductivity-type impurity concentration of about 1.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. Source / drain regions 31 and 32 are formed. The portion where no impurities are introduced becomes the channel region 33.
After that, the resist mask 102 is removed.

Next, as shown in FIG. 9D, the formation region of the first-conductivity-type pixel TFT 10, the formation region of the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40 are covered and the gate is formed. A resist mask 103 that widely covers the electrode 35.
Are formed (third mask formation step).

Subsequently, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fourth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 ²⁰ cm 2.
^-3 high concentration source / drain regions 312 and 322 are formed. In addition, the low concentration second conductivity type source / drain region 3
Of the parts 1 and 32, the part covered with the resist mask 103 becomes the low-concentration source / drain regions 311 and 321 with an impurity concentration of about 1.1 × 10 ¹⁸ cm ⁻³ .

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 10
3 is removed.

Next, as shown in FIG. 9E, in addition to the second-conductivity-type drive circuit TFT 30, the gate electrodes 15 and 2 are formed.
A resist mask 104 is formed to cover 5 as well (4
Second mask formation step).

Subsequently, phosphorus ions are ion-implanted at a dose of 1 × 10 ¹⁵ cm ^-2 (fifth impurity introducing step /
High concentration first conductivity type impurity introduction step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 221, 222 are formed. In addition, low-concentration first conductivity type source / drain regions 11, 12, 21, 2
Of the two, the portion covered with the resist mask 104 becomes the low-concentration source / drain regions 111, 121, 211, 221 with an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ .

In this way, the first-conductivity-type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 104 is removed.

After that, as shown in FIG. 7, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter,
Source / drain electrodes 1 by forming contact holes
When 6, 17, 26, 27, 36, and 37 are formed, a semiconductor device such as the active matrix substrate 1 is formed by four mask forming steps for forming the resist masks 101 to 104 and five impurity introducing steps. Can be manufactured.

As described above, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 9B, before forming the gate electrodes 15, 25, 35 and the upper electrode 45, Concentration source / drain regions 111, 121, 2
The low-concentration first-conductivity-type impurity introduction step for forming 11, 221 is performed, and by using this step, the lower-layer side electrode portion 40
forming c. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one as compared with the conventional manufacturing method. Therefore, the electrical characteristics of each TFT can be improved while forming the TFT and the capacitive element (holding capacitor 40) by a small number of manufacturing steps.

In Tables 2 to 4, the channel doping step is “C / D”, the low concentration first conductivity type impurity introduction step is “N ⁻ ”, and the high concentration first conductivity type impurity introduction step is “N ⁻ ”.
“ ⁺ ”, The low concentration second conductivity type impurity introduction step is “P ⁻ ”, the high concentration second conductivity type impurity introduction step is “P ⁺ ”, and the gate electrode formation step is abbreviated as “G”. 9A and 9B, a low-concentration second conductivity type impurity introducing step shown in FIG.
The gate electrodes 15, 25, 3 are formed by switching the order between the high concentration second conductivity type impurity introduction step shown in (d) and the high concentration first conductivity type impurity introduction step shown in FIG. 9 (e).
5, and before forming the upper-layer side electrode 45, a low-concentration first conductivity type impurity introduction step for forming the low-concentration source / drain regions 111, 121, 211, and 221 is performed, and by using this step, Any process order may be used as long as the lower layer side electrode portion 40c is formed.

[0189]

[Table 2]

[0190]

[Table 3]

[0191]

[Table 4]

[Embodiment 4] The structure of the active matrix substrate of this embodiment will be described with reference to FIG.

In FIG. 7, the feature of the active matrix substrate 1 of this example is that the first conductive type pixel TFT 10 and the first conductive type TFT 10 are manufactured by the same number of steps as the manufacturing method according to the third embodiment. Low concentration source of the drive circuit TFT 20
The point is that the drain regions 111, 121, 211, 221 have a lower concentration than the lower layer side electrode portion 40c of the storage capacitor 40.

That is, the lower layer side electrode portion 40c of the storage capacitor 40.
Has an impurity concentration of about 1 × 1019 cm, as in the third embodiment.
-3 of the low-concentration first conductivity type region, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 2
0 low concentration source / drain regions 111, 121, 21
Reference numerals 1 and 221 contain phosphorus ions (phosphorus ions having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ ) of the same amount as the lower electrode portion 40c of the storage capacitor 40, and the second conductivity type drive circuit T
It is a low-concentration first conductivity type region into which the same amount of boron ions as the low-concentration regions 311 and 321 of the FT 30 (boron ions having an impurity concentration of about 1.1 × 10 ¹⁸ cm ⁻³ ) are introduced.
Therefore, the low concentration source / drain regions 111, 121,
The impurity concentration of 211 and 221 is about 9 × 10 ¹⁸ cm ⁻³ .

The active matrix substrate 1 having such a configuration
Can be manufactured by the manufacturing method described below. Note that the manufacturing method described below has steps common to those of the third embodiment, and therefore these steps will be briefly described.

First, as shown in FIG. 10A, on the surface of the insulating substrate 2, island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions are implanted at a dose of 1 × 10 ¹² cm ^-2 to perform channel doping (channel doping step / first impurity introducing step).

Next, as shown in FIG. 10B, while covering the formation region of the second conductivity type drive circuit TFT 30, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. A resist mask 201 is formed so as to cover the regions where the gate electrodes 15 and 25 are to be formed slightly wider (first mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹⁴ cm ^-2.
Ion implantation with a dose of (second impurity introduction step /
Low concentration first conductivity type impurity introduction step), impurity concentration is about 1
The low-concentration first conductivity type source / drain regions 11, 12, 21, 22 of × 10 ¹⁹ cm ⁻³ and the low-concentration first conductivity type lower layer side electrode portion 40 c are formed.

Next, as shown in FIG. 10C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

The above steps are the same as in the manufacturing method according to the third embodiment.

Next, while covering the formation region of the storage capacitor 40, the gate electrodes 15 and 2 are formed in the same manner as the resist mask 201.
A resist mask 202 is formed so as to slightly cover 5 as well (second mask forming step).

Subsequently, boron ions are added to about 1 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the silicon film 30a has an impurity concentration of about 1.1 × in a self-aligned manner with the gate electrode 35.
Low-concentration second conductivity type source / drain regions 31 and 32 of 10 ¹⁸ cm ⁻³ are formed.

On the other hand, the low-concentration first-conductivity-type source / drain regions 11, 12, 21, and 22 are substantially reduced in concentration by the boron ions implanted therein, so that the low-concentration first-conductivity-type source / drain regions are formed. Areas 11, 12, 11, 12
Has an impurity concentration of about 9 × 10 ¹⁸ cm ⁻³ . After that, the resist mask 202 is removed.

Thereafter, as in the third embodiment, as shown in FIG. 10D, the formation region of the first conductivity type pixel TFT 10 is formed.
A resist mask 203 is formed to cover the formation region of the first-conductivity-type drive circuit TFT 20 and the storage capacitor 40 and to widely cover the gate electrode 35 (third mask formation step).

Subsequently, boron ions (second conductivity type impurities) are ion-implanted at a dose of about 1 × 10 ¹⁵ cm ^-2 (fourth impurity introduction step / high-concentration second conductivity type impurity introduction step). As a result, the low-concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 ²⁰ cm 2.
^-3 high-concentration source / drain regions 312 and 322, and a low-concentration source / drain region with an impurity concentration of about 1.1 × 10 ¹⁸ cm ^−3.
The drain regions 311 and 321 are formed. In this way, the second conductivity type drive circuit TFT 30 is formed. After that, the resist mask 203 is removed.

Next, as shown in FIG. 10E, in addition to the second conductivity type drive circuit TFT 30, the gate electrode 15,
A resist mask 204 is formed so as to cover 25 as well (the fourth mask formation step).

Subsequently, phosphorus ion (first conductivity type impurity)
Is ion-implanted at a dose of 1 × 10 ¹⁵ cm ⁻² (fifth impurity introducing step / high-concentration first conductivity type impurity introducing step).

As a result, the low concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1.
× 10 ²⁰ cm ^-3 high concentration source / drain region 112,
122, 212, 222, and an impurity concentration of about 9 × 10
¹⁸ cm ^-3 low concentration source / drain regions 111 and 12
It becomes 1, 211, 221. Thus, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 2
Form 0. After that, the resist mask 204 is removed.

As a result, resist masks 201-204
A semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the film and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of the present embodiment, as shown in FIG. 10B, before forming the gate electrodes 15, 25, 35 and the upper electrode 45, Concentration source / drain regions 111, 121,
The low-concentration first-conductivity-type impurity introducing step for forming 211 and 221 is performed, and the lower-layer side electrode portion 4 is incorporated by using this step.
It forms 0c. Therefore, as compared with the conventional manufacturing method, the number of mask forming steps and the number of impurity introducing steps can be reduced once, and the same effects as in the third embodiment can be obtained.

Further, as shown in FIG. 10C, in the low-concentration second-conductivity-type impurity introducing step for forming the low-concentration source / drain regions 311, 321, the boron ions implanted at this time are first-conductive. Type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are also formed. That is, the low concentration source / drain regions 311, 321
A low-concentration first-conductivity-type source / drain region 11 by using a low-concentration second-conductivity-type impurity introduction step for forming
The impurity concentrations of 12, 21, and 22 are changed. Because of this,
The storage capacity is 4 without increasing the number of steps as compared with the third embodiment.
It is possible to form low-concentration source / drain regions 111, 121, 211, and 221 whose concentration is lower than that of the lower electrode part 40c of 0. Therefore, the electrical characteristics of each TFT can be further improved with a small number of steps.

As in Example 3, as shown in Tables 2 to 4, the low concentration second conductivity type impurity introducing step shown in FIG. 10C, and the high concentration second conductivity type shown in FIG. 10D. The order of the impurity introduction step and the high-concentration first conductivity type impurity introduction step shown in FIG.
5, 25, 35, and before forming the upper electrode 45,
Low concentration source / drain regions 111, 121, 211,
Any step order may be adopted as long as the low-concentration first-conductivity-type impurity introducing step for forming 221 is performed and the lower layer side electrode portion 40c is formed by using this step.

[Embodiment 5] Referring to FIG. 10C, a low-concentration first conductivity type impurity is added to the low-concentration second-conductivity-type impurity introducing step for forming the low-concentration source / drain regions 311 and 321. Type source / drain regions 11, 12, 21, 2
The impurity concentration of only one of the two may be changed.

For example, in this example, the low-concentration source / drain regions 111 and 121 of the first-conductivity-type pixel TFT 10 shown in FIG. 7 are manufactured by the same number of steps as the manufacturing method according to the third and fourth embodiments. The impurity concentration is lower than that of the low-concentration source / drain regions 211 and 221 of the first conductivity type drive circuit TFT. That is, in the active matrix substrate 1 of this example, the lower layer side electrode portion 40 of the storage capacitor 40 is
c and the low-concentration source / drain regions 211 and 221 of the first-conductivity-type drive circuit TFT are low-concentration first-conductivity-type regions having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ , as in the third embodiment. There is a low-concentration source of the first conductivity type pixel TFT.
The drain regions 111 and 121 have the same amount of phosphorus ions as the lower electrode portion 40c of the storage capacitor 40 (impurity concentration of about 1%).
Along with × 10 ¹⁹ cm ^-3 of phosphorus ions, boron ions of the same amount as the low-concentration regions 311 and 321 of the second conductivity type driving circuit TFT 30 (impurity concentration of about 1.1 × 10 ¹⁸ c).
m ⁻³ boron ion) is introduced in the low concentration first conductivity type region. Therefore, the low concentration source / drain region 11
The impurity concentration of 1,121 is about 9 × 10 ¹⁸ cm ⁻³ .

Active matrix substrate 1 having such a configuration
In manufacturing this, in this example, the following manufacturing method is used.

First, as shown in FIG. 11A, island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Thereafter, channel doping is performed by implanting boron ions with a dose amount of 1 × 10 ¹² cm ^-2 (first impurity introducing step).

Next, as shown in FIG. 11B, while covering the formation region of the second conductivity type drive circuit TFT 30, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. A resist mask 301 is formed so as to widely cover the regions where the gate electrodes 15 and 25 are formed (first mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹⁴ cm ^-2.
Ion implantation with a dose of (second impurity introduction step /
Low concentration first conductivity type impurity introduction step), impurity concentration is about 1
Low-concentration first-conductivity-type source / drain regions 11, 12, 21, 22 of × 10 ¹⁹ cm ⁻³ , and the lower-layer side electrode portion 40
Form c.

Next, as shown in FIG. 11C, the gate electrodes 15, 25, 35 and the upper electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.

The above steps are the same as those in the manufacturing method according to the third and fourth embodiments.

Next, the TFT 2 for the drive circuit of the first conductivity type
A resist mask 302 is formed to cover 0 and the region where the storage capacitor 40 is formed and to cover the gate electrode 15 slightly like the resist mask 301 (second mask forming step).

Then, boron ions are added to about 1 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the impurity concentration of the silicon film 30a is about 1.1 × in a self-aligned manner with the gate electrode 35.
Low-concentration second conductivity type source / drain regions 31 and 32 of 10 ¹⁸ cm ⁻³ are formed. The low-concentration first conductivity type source / drain regions 11 and 12 are substantially reduced in concentration by the boron ions implanted therein, and the impurity concentration of the low-concentration first conductivity type source / drain regions 11 and 12 is , About 9 × 10 ¹⁸ cm ⁻³ . After that, the resist mask 302 is removed.

Thereafter, as in the third embodiment, as shown in FIG. 11D, the formation region of the pixel TFT 10 of the first conductivity type,
A resist mask 303 is formed to cover the formation region of the first-conductivity-type drive circuit TFT 20 and the storage capacitor 40 and to widely cover the gate electrode 35 (third mask formation step).

Subsequently, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fourth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the low concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 ²⁰ cm 2.
^-3 high-concentration source / drain regions 312 and 322, and a low-concentration source / drain region with an impurity concentration of about 1.1 × 10 ¹⁸ cm ^−3.
The drain regions 311 and 321 are formed. In this way, the second conductivity type drive circuit TFT 30 is formed. After that, the resist mask 303 is removed.

Next, as shown in FIG. 11E, in addition to the second conductivity type drive circuit TFT 30, the gate electrode 15,
A resist mask 304 is formed to cover 25 as well (the fourth mask formation step).

Subsequently, phosphorus ions (first conductivity type impurities)
Is ion-implanted at a dose of 1 × 10 ¹⁵ cm ⁻² (fifth impurity introducing step / high-concentration first conductivity type impurity introducing step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1.
× 10 ²⁰ cm ^-3 high concentration source / drain region 112,
122, 212, 222, impurity concentration is about 9 × 10 ¹⁸ c
The low-concentration source / drain regions 111 and 121 of m ⁻³ and the low-concentration source / drain regions 211 and 221 of impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ are formed. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 304 is removed.

Therefore, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the resist masks 301 to 304 and five impurity introducing steps.

As described above, the method of manufacturing the active matrix substrate 1 of the present example has the same effects as those of the third and fourth embodiments, and, in addition, as shown in FIG. The impurity concentration of the low-concentration first conductivity type source / drain regions 11 and 12 is changed by using the low-concentration second conductivity-type impurity introduction step for forming the regions 311 and 321. For this reason, the low-concentration source / drain having a lower concentration than the lower-layer side electrode portion 40c of the storage capacitor 40 and the low-concentration source / drain regions 211 and 221 can be obtained without increasing the number of steps as compared with the third and fourth embodiments. Regions 111 and 121 can be formed. Therefore, the impurity concentration of the low-concentration source / drain regions 211 and 221 of the first-conductivity-type drive circuit TFT 20 and the lower-layer side electrode portion 40c is kept unchanged, and the pixel T is maintained.
Low concentration source / drain regions 111 and 121 of FT10
The TFT's electrical characteristics can be optimized for each region with a small number of steps, such as by reducing the concentration and reducing the off-leak current of the pixel TFT 10 without sacrificing the operating speed in the drive circuit. Can be done.

The low concentration second conductivity type impurity introduction step shown in FIG. 11C, the high concentration second conductivity type impurity introduction step shown in FIG. 11D, and the high concentration first impurity step shown in FIG. 11E. It is needless to say that the order may be exchanged between the conductive type impurity introducing steps.

[Embodiment 6] FIG. 12 is a cross-sectional view schematically showing the structure of an active matrix substrate having a built-in drive circuit in the liquid crystal display device of this embodiment.

In FIG. 12, in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, the first conductive type pixel TFT 10 and the first conductive type drive circuit T are provided.
Since the FT 20 and the channel regions 13, 23 and 33 of the second conductivity type drive circuit TFT 30 ′ are channel-doped with low concentration boron ions, the impurity concentration is low at about 1 × 10 ¹⁷ cm ⁻³ . It is a second conductivity type region. Therefore, the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT
The threshold voltage of 30 'is set to a predetermined value.

In the active matrix substrate 1 thus constructed, the source / drain regions 11, 12, 2 are formed.
1, 22 are provided with low-concentration source / drain regions 111, 121, 211, and 221 at portions facing the ends of the gate electrodes 15 and 25 with the gate insulating films 14 and 24 interposed therebetween. Type pixel TFT 10 and the first conductivity type drive circuit TFT 20 have an LDD structure.

On the other hand, the second conductivity type drive circuit T
The FT 30 'has an offset gate structure, and in the source / drain regions 31 and 32, the gate electrode 3 is formed.
Offset portions 311 ′ and 321 ′ are portions facing the end portion 5 of the gate insulating film 34. The offset regions 311 ′ and 321 ′ correspond to the channel region 33.
Similarly, the impurity concentration is about 1 × 10 ¹⁷ cm −3 in the low concentration second conductivity type region.

In the storage capacitor 40, the lower layer side electrode portion 40c has the low-concentration source / drain regions 111, 12
1, 211, and 221 are low-concentration first conductivity type regions formed simultaneously.

Source regions 11 and 2 of the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20.
1 and the drain regions 12 and 22, low-concentration source regions 111 and 211 and low-concentration drain regions 121 and 2
The region except 21 has an impurity concentration of about 1 × 10 20 cm −.
High-concentration source / drain regions 112, 122, 21
It is 2, 222. For each of these high density regions, each T
Source / drain electrodes 16, 17, 26, 27 such as signal lines and pixel electrodes for the FT are electrically connected through the contact holes of the interlayer insulating film 4. In addition, the source / drain region 3 of the second conductivity type drive circuit TFT 30 '.
1 and 32, the high-concentration source / drain regions 312 and 322 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ adjacent to the offset regions 311 ′ and 321 ′, the source / drain electrodes 36 such as signal lines, 37 is electrically connected through the contact hole of the interlayer insulating film 4.

(TFT On / Off Leakage Current Characteristic) In the active matrix substrate 1 thus constructed,
Since the TFT having the offset gate structure has the on / off leak current characteristic equivalent to that of the LDD structure TFT, the off leak current of each of the TFTs is extremely small. In addition, the TFT having the offset gate structure has an LDD even in the withstand voltage characteristic.
It exhibits the same characteristics as the structured TFT. Therefore, which T
Since the FT also has a higher withstand voltage than the TFT having the self-aligned structure, the channel length can be shortened.

(Method of Manufacturing TFT) The active matrix substrate 1 having such a structure can be manufactured by the following method.

First, as in the third embodiment, as shown in FIG. 13A, an island-shaped silicon film 10a is formed on the surface of the insulating substrate 2.
After forming 20a, 30a, 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Next, channel doping is performed by implanting boron ions with a dose of 1 × 10 ¹² cm ^-2 (channel doping step / first impurity introducing step).

Next, as shown in FIG. 13B, while covering the formation region of the second conductivity type drive circuit TFT 30 ',
A resist mask 401 is formed to slightly widen the formation regions of the gate electrodes 15 and 25 of the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 (first mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹⁴ cm ^-2.
Ion implantation with a dose of (second impurity introduction step /
Low concentration first conductivity type impurity introduction step), impurity concentration is about 1
Low-concentration first-conductivity-type source / drain regions 11, 12, 21, 22 of × 10 ¹⁹ cm ⁻³ , and the lower-layer side electrode portion 40
Form c.

Next, as shown in FIG. 13C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.

Next, a resist mask 402 is formed which covers the formation regions of the first-conductivity-type pixel TFT 10, the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40, and also broadly covers the gate electrode 35. (Second mask forming step).

In this state, boron ions are added at 1 × 10 ¹⁵ c
Ion implantation is performed with a dose amount of m ⁻² (high-concentration second conductivity type impurity introduction step / third impurity introduction step).

As a result, high concentration source / drain regions 312 and 322 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ are formed in the low concentration second conductivity type silicon film 30a. On the other hand, in the low-concentration second-conductivity-type silicon film 30a, the portion covered with the resist mask 402 has the impurity concentration of about 1 × 10 ¹⁷ cm ^{−3 as} the offset regions 311 ′, 3 ′.
21 '. Of course, the channel region 33 remains as a low-concentration second conductivity type region having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ .

In this way, the second conductivity type drive circuit T
Form FT 30 '. After that, the resist mask 4
02 is removed.

Next, as shown in FIG. 13D, a resist mask 403 which broadly covers the gate electrodes 15 and 25 in addition to the formation region of the second conductivity type drive circuit TFT 30 '.
Are formed (third mask formation step).

Subsequently, phosphorus ion (first conductivity type impurity)
Is ion-implanted with a dose amount of 1 × 10 ¹⁵ cm ⁻² (fourth impurity introduction step / high-concentration first conductivity type impurity introduction step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1.
× 10 ²⁰ cm ^-3 high concentration source / drain region 112,
122, 212, 222, and the impurity concentration is about 1 × 10
¹⁹ cm ^-3 low concentration source / drain regions 111 and 12
It becomes 1, 211, 221. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT
20 is formed. After that, the resist mask 403 is removed.

Therefore, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 401 to 403 and four impurity introducing steps.

As described above, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 13B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the low concentration Source / drain regions 111, 121, 2
The low-concentration first-conductivity-type impurity introduction step for forming 11, 221 is performed, and this step is used to assist the lower-layer side electrode portion 40c.
Has formed. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

Further, in this example, as shown in FIG.
In the second-conductivity-type drive circuit TFT 30 ', an offset gate structure is used instead of the LDD structure in order to make the portion facing the gate electrode 35 a low concentration region. Therefore, as compared with the third embodiment, the number of mask formation steps and the number of impurity introduction steps are reduced once. That is, compared with the conventional manufacturing method, the number of times of the mask forming step and the impurity introducing step is twice each. Therefore,
The electrical characteristics of the TFTs in the pixel region and the driving circuit section can be improved by the smallest number of manufacturing steps.

[0259] Naohyo 5 and In Table 6, the channel doping process, "C / D", a low concentration first conductivity type impurity doping process "N ^-", a high-concentration first conductivity type impurity doping process "N
⁺ ", The high-concentration second-conductivity-type impurity introduction step is abbreviated as" P ⁺ ", and the gate electrode formation step is abbreviated as" G ", so that the gate electrodes 15, 25, 35 and the upper electrode 4
5 is formed, the low concentration source / drain region 11 is formed.
If the low-concentration first-conductivity-type impurity introduction step for forming 1, 121, 211, and 221 is performed and the lower-layer side electrode portion 40c is formed by using this step, the order of steps is not limited. Good.

[0260]

[Table 5]

[0261]

[Table 6]

[Embodiment 7] FIG. 14 is a sectional view schematically showing the structure of an active matrix substrate having a built-in drive circuit in the liquid crystal display device of this embodiment.

In FIG. 14, in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, the first conductive type pixel TFT 10 and the first conductive type drive circuit T are provided.
The FT 20 and the second conductivity type drive circuit TFT 30 are
Each has an LDD structure, and in any TFT, the channel regions 13, 23, and 33 are channel-doped with low-concentration boron ions, so that the impurity concentration is about 1 × 10 ¹⁷ cm ⁻³ . It is a low-concentration second conductivity type region.

In this example, the lower layer side electrode portion 4 of the storage capacitor 40 is used.
0d (first electrode portion) is the first conductivity type pixel TFT 1
0 and the high-concentration first-conductivity-type region having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ formed simultaneously with the high-concentration source / drain regions 112, 122, 212, and 222 of the first-conductivity-type drive circuit TFT ^20. There is.

Active matrix substrate 1 having such a structure
Can be produced, for example, by the following method.

First, as shown in FIG. 15A, the island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of about 1 × 10 ¹² cm ^-2 to perform channel doping (channel doping step / first impurity introduction). Process).

Next, as shown in FIG. 15B, a resist mask which covers the formation region of the second-conductivity-type drive circuit TFT 30 and broadly covers the formation regions of the gate electrodes 15 and 25 to be formed later. 501 is formed (first mask forming step).

Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ⁻² (second impurity introduction step / high concentration first Conductive impurity introduction step).

As a result, in the low-concentration second-conductivity-type silicon films 10a and 20a, the region in which phosphorus ions have been implanted has the conductivity type reversed and the impurity concentration is about 1 × 10 ²⁰ cm ^−3.
High concentration source / drain regions 112, 122, 21 of
2, 222. Also, a low concentration second conductivity type silicon film 4
The conductivity type of 0a is also reversed and the impurity concentration is about 1 × 10 ²⁰ cm
^-3 of the high-concentration first conductivity type lower layer side electrode portion 40d. After that, the resist mask 501 is removed.

Next, as shown in FIG. 15C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 (second electrode portion) are formed (gate electrode forming step). In this way, the storage capacitor 40 in which the lower layer side electrode portion 40d and the upper layer side electrode portion 45 face each other with the dielectric film 44 in between is formed.

Next, a resist mask 502 covering the formation regions of the first-conductivity-type pixel TFT 10, the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40 is formed (second mask formation step).

Subsequently, boron ions are added to about 1 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity-type silicon film 30a has a low-concentration second-conductivity-type impurity concentration of about 1.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. Source / drain regions 31 and 32 are formed. The portion where no impurities are introduced becomes the channel region 33.
After that, the resist mask 502 is removed.

Next, as shown in FIG. 15D, a resist mask 503 covering the formation region of the second conductivity type drive circuit TFT 30 is formed (third mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (4th impurity introducing step / low-concentration first conductivity type impurity introducing step).

As a result, the high concentration source / drain region 1
The gate electrode 1 is formed on the low-concentration second-conductivity-type silicon films 10a and 20a sandwiched between 12, 122, 212, and 222.
The impurity concentration is about 0.9 × in a self-aligned manner with respect to 5 and 25.
10 ¹⁸ cm ⁻³ low concentration source / drain regions 211, 2
21 is formed. The portions into which the impurities have not been introduced become the channel regions 23 and 33. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 503 is removed.

Next, as shown in FIG. 15E, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT are provided.
A resist mask 504 is formed to cover the formation region of the storage capacitor 20 and the storage capacitor 40 and to widely cover the gate electrode 35 (fourth mask formation step). Here, the distance between the end of the resist mask 504 and the end of the gate electrode 35 is
0.5 μm to 2 μm is suitable.

Subsequently, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fifth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the low concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 ²⁰ cm 2.
^-3 high concentration source / drain regions 312 and 322 are formed. In addition, the low concentration second conductivity type source / drain region 3
Of the parts 1 and 32, the part covered with the resist mask 504 becomes the low-concentration source / drain regions 311 and 321 with the impurity concentration of about 1.1 × 10 ¹⁸ cm ⁻³ .

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 50
Remove 4.

Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the resist masks 501 to 504 and five impurity introducing steps.

As described above, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 15B, before forming the gate electrodes 15, 25 and 35 and the upper electrode 45, Concentration source / drain regions 112, 122,
A high-concentration first-conductivity-type impurity introduction step for forming 212, 222 is performed, and this step is used to assist the lower-layer side electrode section 40.
forming d. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one as compared with the conventional manufacturing method. Therefore, the electrical characteristics of each TFT can be improved while forming the TFT and the capacitive element (holding capacitor 40) by a small number of manufacturing steps.

In Table 7, the channel doping step is "C / D", and the low-concentration first conductivity type impurity introducing step is "N".
^- ", a high-concentration first conductivity type impurity doping process" N ⁺ ", a low concentration second conductivity-type impurity introduction step" P ^- ", the high-concentration second conductivity-type impurity introduction step" P ⁺ ", the gate electrode The formation process is abbreviated as “G” to indicate the process sequence, and the gate electrode 1
5, 25, 35, and before forming the upper electrode 45,
High concentration source / drain regions 112, 122, 212,
Any step order may be used as long as a high-concentration first-conductivity-type impurity introduction step for forming 222 is performed and this step is used to form the lower-layer side electrode portion 40d.

[0285]

[Table 7]

[Embodiment 8] The structure of the active matrix substrate of this embodiment will be described with reference to FIG. 14 as in Embodiment 7.

In FIG. 14, the feature of the active matrix substrate 1 of the present example is that the number of mask forming steps is one less than that of the manufacturing method according to the seventh embodiment. The manufacturing method will be described below. Exactly as you would.

First, as shown in FIG. 16 (a), island-shaped silicon films 10a, 20a, 30a, and
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted with a dose amount of about 1 × 10 ¹² cm ^-2 to perform channel doping (channel doping step / first impurity introduction). Process).

Next, as shown in FIG. 16B, a resist mask which covers the formation region of the second-conductivity-type drive circuit TFT 30 and broadly covers the formation regions of the gate electrodes 15 and 25 to be formed later. 601 is formed (first mask forming step).

Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ⁻² (second impurity introduction step / high-concentration first conductivity type). Type impurity introduction step).

As a result, in the low-concentration second-conductivity-type silicon films 10a and 20a, the region in which phosphorus ions have been implanted has the conductivity type reversed and the impurity concentration is about 1 × 10 ²⁰ cm ^−3.
High concentration source / drain regions 112, 122, 21 of
2, 222. Also, a low concentration second conductivity type silicon film 4
In 0a, the conductivity type is reversed and the impurity concentration is about 1 × 10 ²⁰ c.
It becomes the lower layer side electrode portion 40d of the high concentration first conductivity type of m ^-3 .
After that, the resist mask 601 is removed.

Next, as shown in FIG. 16C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

Next, a resist mask 602 covering the formation regions of the first-conductivity-type pixel TFT 10, the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40 is formed (second mask formation step).

Subsequently, boron ions are added to about 3 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity type silicon film 30a has a low-concentration second-conductivity-type impurity concentration of about 3.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. Source / drain regions 31 and 32 are formed. The portion where no impurities are introduced becomes the channel region 33.
After that, the resist mask 602 is removed.

Next, as shown in FIG. 16D, phosphorus ions are added to about 1 × 10 ¹³ c without forming a resist mask.
Ion implantation is performed with a dose amount of m ⁻² (fourth impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the high concentration source / drain region 1
The gate electrode 1 is formed on the low-concentration second-conductivity-type silicon films 10a and 20a sandwiched between 12, 122, 212, and 222.
The impurity concentration is about 0.9 × in a self-aligned manner with respect to 5 and 25.
10 ¹⁸ cm ^-3 low concentration source / drain regions 111, 1
21, 211, 221 are formed. The portions into which the impurities have not been introduced become the channel regions 23 and 33. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed.

Here, the low concentration second conductivity type source / drain regions 31 and 32 also have phosphorus ions of 1 × 10 ¹³ cm 3.
Ions are implanted with a dose amount of ⁻² , and the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is about 3.1 × 10 ¹⁸ cm ⁻³ . Therefore, the low-concentration second conductivity type source / drain regions 31 and 32 substantially have an acceptor-type impurity concentration of about 2.1 × 10 ¹⁸ cm ^−3.
However, the conductivity type is not reversed.

Next, as shown in FIG. 16E, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT are provided.
A resist mask 603 is formed to cover the formation region of the storage capacitor 40 and the storage capacitor 40 and to widely cover the gate electrode 35 (third mask formation step).

Subsequently, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fifth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 ²⁰ cm 2.
^-3 high concentration source / drain regions 312 and 322 are formed. In addition, the low concentration second conductivity type source / drain region 3
Of the parts 1 and 32, the part covered with the resist mask 603 becomes the low-concentration source / drain regions 311 and 321 with the impurity concentration of about 2.1 × 10 ¹⁸ cm ⁻³ .

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 60
3 is removed.

Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 601 to 603 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of the present example, as shown in FIG. 16B, before forming the gate electrodes 15, 25 and 35 and the upper electrode 45, Concentration source / drain regions 112, 122,
A high-concentration first-conductivity-type impurity introduction step for forming 212, 222 is performed, and this step is used to assist the lower-layer side electrode section 40.
forming d. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

In addition, the low concentration source / drain region 11
In the process for forming 1, 121, 211, 221,
Phosphorus ion implantation is performed without forming a mask. Therefore, each of the TFTs and the storage capacitor 40 can be manufactured by performing the mask forming step 3 times and the impurity introducing step 5 times.

As in the seventh embodiment, the gate electrodes 15 and 2 are
5, 35, and the high-concentration source / drain regions 112, 122, 212, 222 before forming the upper electrode 45.
A high-concentration first-conductivity-type impurity introducing step for forming the above is performed, and any step sequence shown in Table 7 may be used as long as the lower-layer side electrode portion 40d is formed by using this step.

[Ninth Embodiment] The structure of the active matrix substrate of this embodiment will be described with reference to FIG. 14 as in the seventh embodiment. Similar to the eighth embodiment, the feature of this embodiment is that the number of mask forming steps is one less than that of the manufacturing method according to the seventh embodiment, and the manufacturing method is as described below.

First, as shown in FIG. 17A, island-shaped silicon films 10a, 20a, 30a, on the surface of the insulating substrate 2,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step.) Next, with a dose amount of about 1 × 10 12 cm −2. Channel doping is performed by implanting boron ions (second conductivity type impurities / second conductivity type impurities) (channel doping step / 1
Second impurity introduction step).

Next, as shown in FIG. 17B, a resist mask which covers the formation region of the second-conductivity-type drive circuit TFT 30 and widens the formation regions of the gate electrodes 15 and 25 to be formed later. 701 is formed (first mask forming step).

Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ⁻² (second impurity introduction step / high concentration first Conductive impurity introduction step).

As a result, in the low-concentration second-conductivity-type silicon films 10a and 20a, the region in which phosphorus ions have been implanted has the conductivity type reversed and the impurity concentration is about 1 × 10 ²⁰ cm ^−3.
High concentration source / drain regions 112, 122, 21 of
2, 222. Also, a low concentration second conductivity type silicon film 4
In 0a, the conductivity type is reversed and the impurity concentration is about 1 × 10 ²⁰ c.
It becomes the lower layer side electrode portion 40d of the high concentration first conductivity type of m ^-3 .
After that, the resist mask 701 is removed.

Next, as shown in FIG. 17C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

Next, a resist mask 702 covering the formation region of the p-type drive circuit TFT 30 is formed (second mask forming step).

Subsequently, phosphorus ions were added to about 3 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (third impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the high concentration source / drain region 1
The gate electrode 1 is formed on the low-concentration second-conductivity-type silicon films 10a and 20a sandwiched between 12, 122, 212, and 222.
The impurity concentration is about 2.9 × in a self-aligning manner with respect to 5 and 25.
10 ¹⁸ cm ^-3 low concentration source / drain regions 111, 1
21, 211, 221 are formed. The portions into which the impurities have not been introduced become the channel regions 23 and 33. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed.

Next, as shown in FIG. 17D, the resist mask 702 is removed, and boron ions are ion-implanted at a dose of about 1 × 10 ¹³ cm ^-2 without directly forming the resist mask. (Fourth impurity introducing step / low-concentration second conductivity type impurity introducing step).

As a result, in the low-concentration second conductivity type silicon film 30a, the low-concentration p-type region 3 having an impurity concentration of about 1.1 × 10 ¹⁸ cm ⁻³ is self-aligned with the gate electrode 35.
1, 32 are formed. The portion where no impurities are introduced becomes the channel region 33.

Here, boron ions are also ion-implanted into the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 at a dose of 1 × 10 ¹³ cm ^-2. Low concentration source / drain regions 111 and 12
The impurity concentration of 1, 211, 221 is about 2.9 × 10 ¹⁸
It is cm ^-3 . Therefore, the low concentration source / drain region 1
Nos. 11, 121, 211 and 221 substantially lower the donor type impurity concentration to about 1.9 × 10 ¹⁸ cm ⁻³ , and do not invert the conductivity type. Further, the high-concentration dose / drain regions 112, 122, 212, 222 are also only slightly lowered in concentration, the conductivity type is not reversed, and the concentration is still high.

Next, as shown in FIG. 17E, while covering the formation region of the first-conductivity-type pixel TFT 10, the formation region of the first-conductivity-type drive circuit TFT 20, and the storage capacitor 40, the gate is formed. A resist mask 70 covering the electrode 35 widely.
3 is formed (third mask forming step).

Then, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fifth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the impurity concentration of the low-concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 ²⁰ c.
High concentration source / drain regions 312 and 322 of m ⁻³ are formed. In the low concentration second conductivity type source / drain regions 31 and 32, the portion covered with the resist mask 703 has an impurity concentration of about 2.1 × 10 ¹⁸ cm ^−3.
Of the low concentration source / drain regions 311 and 321.

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 70
3 is removed.

Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 701 to 703 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 17B, the high electrode is formed before the gate electrodes 15, 25, 35 and the upper electrode 45 are formed. Concentration source / drain regions 112, 122,
A high-concentration first-conductivity-type impurity introduction step for forming 212, 222 is performed, and this step is used to assist the lower-layer side electrode section 40.
forming d. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

In addition, the low concentration source / drain region 31
In the step of forming Nos. 1 and 321, boron ions are implanted without forming a mask. Therefore, each of the TFTs and the storage capacitor 40 can be manufactured by performing the mask forming step 3 times and the impurity introducing step 5 times.

Note that the gate electrodes 15 and 2 are the same as in the seventh embodiment.
5, 35, and the high-concentration source / drain regions 112, 122, 212, 222 before forming the upper electrode 45.
A high-concentration first-conductivity-type impurity introducing step for forming the above is performed, and any step sequence shown in Table 7 may be used as long as the lower-layer side electrode portion 40d is formed by using this step.

[Embodiment 10] FIG. 18 is a cross-sectional view schematically showing the structure of an active matrix substrate having a built-in drive circuit in the liquid crystal display device of this embodiment.

In FIG. 18, in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 have an LDD structure. It has become. On the other hand, the second conductivity type drive circuit TFT 30 ′ has an offset gate structure.

In this example, the lower layer side electrode portion 40d of the storage capacitor 402 is composed of the high-concentration source / drain regions 112, 122, 212 of the first-conductivity-type drive circuit TFT 20 and the first-conductivity-type pixel TFT 10. It is a high-concentration first conductivity type region having an impurity concentration of 1 × 10 ²⁰ cm ^{−3 which} is formed simultaneously with 222.

Active matrix substrate 1 having such a structure
Can be produced by the following method.

First, as shown in FIG. 19 (a), island-shaped silicon films 10a, 20a, 30a, are formed on the surface of the insulating substrate 2.
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Thereafter, channel doping is performed by implanting boron ions with a dose amount of 1 × 10 ¹² cm ⁻² (channel doping step / first impurity introducing step).

Next, as shown in FIG. 19B, while covering the formation region of the second conductivity type drive circuit TFT 30 ',
A resist mask 801 which broadly covers the regions where the gate electrodes 15 and 25 of the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 are to be formed is formed (first mask forming step).

Subsequently, first conductivity type impurities such as phosphorus ions are ion-implanted at a dose of about 1 × 10 ¹⁵ cm ^-2 (second impurity introduction step / high-concentration first conductivity type impurity introduction step).

As a result, in the silicon films 10a and 20a, the regions in which phosphorus ions have been implanted have the conductivity type inverted and the high-concentration source / drain regions 112, 122 and 211 with an impurity concentration of about 1 × 10 ²⁰ cm ^-3. It becomes 221. The conductivity type of the silicon film 40a is reversed and the impurity concentration is about 1 ×.
High-concentration first conductivity type lower layer side electrode portion 40d of 10 ²⁰ cm ^-3
Becomes After that, the resist mask 801 is removed.

Next, as shown in FIG. 19C, gate electrodes 15, 25 and 35 made of doped silicon or a silicide film are formed on the surfaces of the gate insulating films 14, 24 and 34 (gate electrode formation). Process). At the same time, the dielectric film 44
The upper electrode portion 45 is formed on the surface of the. The upper layer side electrode portion 45 may be a part of the signal line in the previous stage. In this way, the storage capacitor 40 in which the lower layer side electrode portion 40c and the upper layer side electrode portion 45 face each other with the dielectric film 44 in between is formed.

Next, the second-conductivity-type drive circuit TFT 30.
Forming a resist mask 802 covering the mask (second mask forming step).

In this state, phosphorus ions are added at 1 × 10 ¹³ cm
Ion implantation is performed at a dose of ^-2 (low-concentration first conductivity type impurity introduction step / third impurity introduction step).

As a result, the high concentration source / drain region 1
The gate electrode 1 is formed on the low-concentration second conductivity type silicon films 20a and 30a sandwiched between 12, 122, 212 and 222.
The impurity concentration is about 0.9 × in a self-aligned manner with respect to 5 and 25.
A low concentration source / drain region 111 of 10 ¹⁸ cm −3,
121, 211, and 221 are formed. The portions into which the impurities have not been introduced become the channel regions 23 and 33. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed.

Next, as shown in FIG. 19D, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT
A resist mask 803 is formed to cover the formation region of the storage capacitor 40 and the storage capacitor 40 and to widely cover the gate electrode 35 (third mask formation step).

In this state, boron ions are added at 1 × 10 ¹⁵ c
Ion implantation is performed with a dose amount of m ⁻² (high-concentration second conductivity type impurity introduction step / 4th impurity introduction step).

As a result, high concentration source / drain regions 312 and 322 having an impurity concentration of 1 × 10 20 cm −3 are formed in the low concentration second conductivity type silicon film 30a.
On the other hand, in the low-concentration second conductivity type silicon film 30a, the portion covered with the resist mask 803 has the impurity concentration of about 1 × 10 ¹⁷ cm ^{−3 as} the offset region 31.
1 ', 321'. The channel region 33 remains as a low-concentration second conductivity type region having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ .

In this way, the second conductivity type drive circuit T
Form FT 30 '. After that, the resist mask 8
03 is removed.

Therefore, the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 801 to 803 and four impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 19B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a high concentration Source / drain regions 112, 122, 2
The high-concentration first-conductivity-type impurity introducing step for forming the first and second conductive layers 122 and 222 is performed, and this step is used to assist the lower electrode section 40.
forming d. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

Further, in this example, as shown in FIG.
In the second-conductivity-type drive circuit TFT 30 ', an offset gate structure is used instead of the LDD structure in order to make the portion facing the end of the gate electrode 35 a low concentration region. Therefore, as compared with the third embodiment, the number of mask formation steps and the number of impurity introduction steps are reduced by one each. That is, compared with the conventional manufacturing method, the number of times of the mask forming step and the impurity introducing step is twice each.
Therefore, the electrical characteristics of the TFTs in the pixel region and the drive circuit section can be improved with the least number of manufacturing steps.

In Table 8, the channel doping step is "C / D" and the low-concentration first conductivity type impurity introducing step is "N-."
, The high-concentration first conductivity type impurity introducing step is abbreviated as “N ⁺ ”, the high-concentration second conductivity type impurity introducing step is abbreviated as “P ⁺ ”, and the gate electrode forming step is abbreviated as “G”. Before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the high concentration source / drain regions 112, 12 are formed.
Any step order may be adopted as long as a low-concentration first conductivity type impurity introducing step for forming 2, 212, 222 is performed and the lower layer side electrode portion 40d is formed by using this step. .

[0349]

[Table 8]

[Embodiment 11] As shown in FIG. 20, in the active matrix substrate 1 of this embodiment, the second conductivity type drive circuit TFT 30, the first conductivity type drive circuit TFT 20,
And the first conductivity type pixel TFT 10 are both LDD
It is structured.

Further, in the active matrix substrate 1 of this example, the lower layer side electrode portion 40e (first electrode portion) of the storage capacitor 40 is the low concentration source / drain regions 311 and 312 of the second conductivity type drive circuit TFT 30. And a low-concentration second conductivity type region having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ formed at the same time.

Active matrix substrate 1 having such a structure
Can be produced, for example, by the following method.

First, as shown in FIG. 21A, on the surface of the insulating substrate 2, island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Next, channel ions are implanted by implanting boron ions (second conductivity type impurities / second conductivity type impurities) with a dose amount of about 1 × 10 ¹² cm ⁻² (channel doping step / first impurity). Introduction process).

Next, as shown in FIG. 21B, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TF.
A resist mask 9 which covers the formation region of T20 and covers a formation region of a gate electrode 35 which will be formed later slightly.
01 is formed (first mask forming step).

Subsequently, for example, boron phosphorus ions (second conductivity type impurities / second conductivity type impurities) are added to about 1 × 10 ¹⁴ cm 2.
Ion implantation is performed at a dose of ^-2 (second impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, low concentration second conductivity type source / drain regions 31 and 32 having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ are formed in the low concentration second conductivity type silicon film 30a. The low-concentration second-conductivity-type silicon film 40a becomes the low-concentration second-conductivity-type lower-layer-side electrode portion 40e having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ . After that, the resist mask 9
01 is removed.

Next, as shown in FIG. 21C, gate electrodes 15, 25 and 35 made of doped silicon, a silicide film or the like are formed on the surfaces of the gate insulating films 14, 24 and 34. At the same time, the upper layer side electrode portion 45 (second electrode portion) is formed on the surface of the dielectric film 44 (gate electrode forming step). The upper layer side electrode portion 45 may be a part of the signal line in the previous stage. In this way, the storage capacitor 40 in which the lower layer side electrode portion 40e and the upper layer side electrode portion 45 are opposed to each other with the dielectric film 44 interposed therebetween is formed.

Next, the second conductivity type drive circuit TFT 3
A resist mask 902 that covers 0 and the region where the storage capacitor 40 is formed is formed (second mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (third impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity-type silicon films 10a and 20a have a low-concentration impurity concentration of about 0.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23. After that, the resist mask 902 is removed.

Next, as shown in FIG. 21D, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT
A resist mask 903 which covers the gate electrode 35 and the formation region of the storage capacitor 40 and the storage capacitor 20 is formed (third mask forming step).

Subsequently, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fourth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the low concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 ²⁰ c.
High concentration source / drain regions 312 and 322 of m ⁻³ are formed. In the low concentration second conductivity type source / drain regions 31 and 32, the portion covered with the resist mask 103 has an impurity concentration of about 1.1 × 10 ¹⁸ cm ^−3.
Of the low concentration source / drain regions 311 and 321.

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 90
3 is removed.

Next, as shown in FIG. 21E, a resist mask 904 is formed to cover the second conductivity type drive circuit TFT 30 and widely cover the gate electrodes 15 and 25 (fourth mask formation). Process).

Subsequently, phosphorus ions are ion-implanted at a dose of 1 × 10 ¹⁵ cm ^-2 (fifth impurity introducing step /
High concentration first conductivity type impurity introduction step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 212, 222 are formed. In addition, low-concentration first conductivity type source / drain regions 11, 12, 21, 2
Of the two, the part covered with the resist mask 904 is
As it is, the low-concentration source / drain regions 111, 121, 211, 221 whose impurity concentration is about 0.9 × 10 ¹⁸ cm ⁻³
Becomes

In this way, the first-conductivity-type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 904 is removed.

After that, as shown in FIG. 20, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, the semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the resist masks 901 to 904 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 21B, before forming the gate electrodes 15, 25, 35 and the upper electrode 45, A low-concentration second-conductivity-type impurity introduction step for forming the high-concentration source / drain regions 311 and 321;
The lower layer side electrode portion 40e is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one as compared with the conventional manufacturing method. Therefore, with a small number of manufacturing steps,
It is possible to improve the electrical characteristics of each TFT in the pixel region and the drive circuit portion while forming the capacitor element (holding capacitor 40) with the above.

[0372] Note that the manufacturing method of this embodiment, in the manufacturing method according to Example 3 shown in Table 2 to Table 4, "N ^-" a low concentration first conductivity type impurity introducing step indicated by "P ^- It corresponds to a method in which the low-concentration second conductivity type impurity introduction step shown in FIG. 10 is replaced, and therefore, the low-concentration source / drain regions 3 are formed before the gate electrodes 15, 25, 35 and the upper electrode 45 are formed.
The low-concentration second-conductivity-type impurity introduction step for forming 11, 321 is performed, and the lower-layer side electrode section 40 is incorporated by using this step.
As long as e is formed, any of 60 process steps may be performed.

[Embodiment 12] A feature of the active matrix substrate 1 of the present embodiment is that it is manufactured by the same number of steps as the manufacturing method according to Embodiment 11, while the second conductivity type TFT for drive circuit is manufactured.
The low concentration source / drain regions 311 and 321 of 30 have a lower concentration than the lower layer side electrode portion 40e of the storage capacitor 40.

That is, in FIG. 20, the lower layer side electrode portion 40e of the storage capacitor 40 is similar to the eleventh embodiment in that the low-concentration source / drain region 31 of the second conductivity type drive circuit TFT 30 is used.
Although formed at the same time as that of No. 1 and 321, the impurity concentration of the lower layer side electrode portion 40e is a low concentration second conductivity type region of about 1 × 10 ¹⁹ cm ⁻³ , while driving of the second conductivity type is performed. Low concentration source / drain regions 311 and 3 of the circuit TFT 30
21 has an impurity concentration of about 9 × 10 ¹⁸ cm ⁻³ .

In the active matrix substrate 1 of this example, the second conductivity type drive circuit TFT 30, the first conductivity type drive circuit TFT 20, and the first conductivity type pixel TFT 10 are used.
Any one of the low concentration source / drain regions 111, 121, 21 is formed in a portion facing the ends of the gate electrodes 15, 25, 35 via the gate insulating films 14, 24, 34.
It has an LDD structure including 1, 221, 311, and 321.

Active matrix substrate 1 having such a structure
Can be produced, for example, by the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.

First, as shown in FIG. 22A, on the surface of the insulating substrate 2, island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of about 1 × 10 ¹² cm ⁻² to perform channel doping (channel doping step / first impurity introduction). Process).

Next, as shown in FIG. 22B, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TF.
A resist mask 1101 is formed to cover the formation region of T20 and to slightly widen the formation planned region of the gate electrode 35 of the second-conductivity-type drive circuit TFT 30 to be formed later (first mask formation step).

Then, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are ion-implanted at a dose of about 1 × 10 ¹⁴ cm ^-2 (second impurity introduction step /
Low concentration second conductivity type impurity introduction step).

As a result, low concentration second conductivity type source / drain regions 31 and 32 having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ are formed in the low concentration second conductivity type silicon film 30a. The low-concentration second-conductivity-type silicon film 40a becomes the low-concentration second-conductivity-type lower-layer-side electrode portion 40e having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ . After that, the resist mask 11
01 is removed.

Next, as shown in FIG. 22C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

Next, a resist mask 1102 which covers the formation region of the storage capacitor 40 is formed (second mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (third impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity-type silicon films 10a and 20a have a low-concentration impurity concentration of about 0.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23.

Here, the low concentration second conductivity type silicon film 3 is formed.
To 1,32, phosphorus ions but it is ion-implanted at a dose of about 1 × 10 ¹³ cm ^-2, a low concentration impurity concentration of the second conductivity type silicon films 31 and 32 is about 1 × 10 ¹⁹ cm ^- Is ³ . Therefore, the low concentration second conductivity type silicon films 31 and 3 are formed.
2 has a substantially acceptor-type impurity concentration of about 9 × 10
^The concentration is reduced to ¹⁸ cm ^-3 , but the conductivity type is not reversed.

After that, the resist mask 1102 is removed.

Next, as shown in FIG. 22D, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT
A resist mask 1103 is formed to cover the gate electrode 35 and the formation region of the storage capacitors 40 and 20 (third mask formation step).

Then, boron ions are added to about 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (fourth impurity introduction step / high-concentration second conductivity type impurity introduction step).

As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 ²⁰ c.
High concentration source / drain regions 312 and 322 of m ⁻³ are formed. Of the low-concentration second conductivity type source / drain regions 31 and 32, the portion covered with the resist mask 1103 has a low-concentration source / drain region 311 having an impurity concentration of about 9 × 10 ¹⁸ cm ⁻³ . It becomes 321.

In this way, the second conductivity type drive circuit T
FT30 is formed. After that, the resist mask 11
03 is removed.

Next, as shown in FIG. 22E, a resist mask 1104 is formed to cover the formation regions of the second-conductivity-type drive circuit TFT 30 and the storage capacitor 40 and to widely cover the gate electrodes 15 and 25. (4th mask forming step).

Subsequently, phosphorus ions are ion-implanted at a dose of 1 × 10 ¹⁵ cm ^-2 (fifth impurity introduction step /
High concentration first conductivity type impurity introduction step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 222, 222 are formed. In addition, low-concentration first conductivity type source / drain regions 11, 12, 21, 2
Of the two, the portion covered with the resist mask 1104 is the low concentration source / drain regions 111, 121, 211, 2 with the impurity concentration of about 0.9 × 10 ¹⁸ cm ^−3.
It becomes 21.

In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1104 is removed.

After that, as shown in FIG. 20, after the interlayer insulating film 4 is formed, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the resist masks 1101 to 1104 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 22B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A low-concentration first conductivity type impurity introduction step for forming the high-concentration source / drain regions 311 and 321;
The lower layer side electrode portion 40e is formed by using this step. Therefore, compared with the conventional manufacturing method, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one, and the same effect as that of the twelfth embodiment is obtained.

Further, as shown in FIG. 22C, in the low concentration first conductivity type impurity introducing step for forming the low concentration source / drain regions 111, 121, 211, 221,
The phosphorus ions that are implanted at this time are also implanted in the formation region of the second conductivity type drive circuit TFT 30. That is, the low-concentration source /
The impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 for forming the drain regions 311 and 321 is changed. Therefore, without increasing the number of steps as compared with the eleventh embodiment, the low-concentration source / drain regions 311 and 31, whose concentration is lower than that of the lower electrode portion 40e of the storage capacitor 40, are obtained.
21 can be formed.

The manufacturing method of this example corresponds to the manufacturing method according to the fourth embodiment in which the low-concentration first conductivity type impurity introducing step and the low-concentration second conductivity type impurity introducing step are replaced. Therefore, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a low-concentration second conductivity type impurity introduction step for forming the low-concentration source / drain regions 311 and 321 is performed. Incorporating the lower electrode part 4
0e is to be formed, the low-concentration first conductivity type impurity introduction step indicated by “N ⁻ ” and the low-concentration second step indicated by “P ⁻ ” in the 60-step sequence shown in Tables 2 to 4 The order of the steps may be interchanged with the step of introducing the conductive impurity.

[Embodiment 13] FIG. 23 is a sectional view schematically showing the structure of an active matrix substrate having a built-in drive circuit in the liquid crystal display device of this embodiment. In the active matrix substrate of this example, the basic structure of each TFT is substantially the same as that of the active matrix substrate shown in FIG.

In FIG. 23, in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit T are provided.
The FT 20 and the second conductivity type drive circuit TFT 30 are
Each has an LDD structure, and in any TFT, the channel regions 13, 23, and 33 are channel-doped with low-concentration boron ions, so that the impurity concentration is about 1 × 10 ¹⁷ cm ⁻³ . It is a low-concentration second conductivity type region.

In this example, the lower layer side electrode portion 40f (first electrode portion) of the storage capacitor 402 is the second conductivity type drive circuit T.
High concentration source / drain regions 311, 312 of FT30
And a high-concentration second conductivity type region having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ formed at the same time.

Active matrix substrate 1 having such a structure
Can be produced, for example, by the following method.

First, as shown in FIG. 24 (a), island-shaped silicon films 10a, 20a, 30a, are formed on the surface of the insulating substrate 2.
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are simultaneously formed (gate insulating film forming step).

Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of about 1 × 10 ¹² cm ⁻² to perform channel doping (channel doping step / first impurity). Introduction process).

Next, as shown in FIG. 24B, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TF.
A resist mask 1201 is formed to cover the formation region of T20 and to cover a formation region of the gate electrode 35 of the second-conductivity-type drive circuit TFT 30 that will be formed later slightly wider (first mask formation step).

Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are ion-implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² (second impurity introduction step /
High-concentration second conductivity type impurity introduction step).

[0408] As a result, among the low concentration second conductivity type silicon film 30a, a region where a high concentration of boron ions is implanted is, high concentration source of impurity concentration of about 1 × 10 ²⁰ cm ^-3
The drain regions 312 and 322 are formed. The low concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10 ²⁰ c.
It becomes the lower layer side electrode portion 40f of the high concentration second conductivity type of m ⁻³ .
After that, the resist mask 1201 is removed.

Next, as shown in FIG. 24C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 (second electrode portion) are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

Next, the second conductivity type drive circuit TFT 3
A resist mask 1202 is formed to cover 0 and the region where the storage capacitor 40 is formed (second mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (third impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the low-concentration second conductivity type silicon films 10a and 20a have a low-concentration impurity concentration of about 0.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23. After that, the resist mask 1202 is removed.

Next, as shown in FIG. 24D, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT are provided.
A resist mask 1203 is formed to cover the area where the storage capacitor 40 and the storage capacitor 40 are formed (third mask forming step).

Subsequently, boron ions are added to about 1 × 10 ¹³ cm
Ion implantation is performed at a dose of ^-2 (the fourth impurity introduction step / low-concentration second conductivity type impurity introduction step).

As a result, the high concentration source / drain regions 3
In the low-concentration second conductivity type silicon film 30a sandwiched between 12, 322, a low-concentration source / drain region having an impurity concentration of about 1.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. 311 and 321 are formed. The portion where no impurities are introduced becomes the channel region 33. In this way, the second conductivity type drive circuit TFT 30 is formed.
After that, the resist mask 1203 is removed.

Next, as shown in FIG. 24E, a resist mask 1204 is formed to cover the formation regions of the second-conductivity-type drive circuit TFT 30 and the storage capacitor 40 and to broadly cover the gate electrodes 15 and 25. Forming (fourth mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹⁵ cm ^-2.
Ion implantation with a dose amount of (5th impurity introducing step / high-concentration first conductivity type impurity introducing step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 212, 222 are formed. In addition, low-concentration second conductivity type source / drain regions 11, 12, 21, 2
Of the two, the portion covered with the resist mask 1204 is the low concentration source / drain regions 111, 121, 211, 2 with the impurity concentration of about 0.9 × 10 ¹⁸ cm ^−3.
It becomes 21. In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1204 is removed.

After that, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, the semiconductor device such as the active matrix substrate 1 can be manufactured by four mask forming steps for forming the resist masks 1201 to 1204 and five impurity introducing steps.

As described above, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 24 (b), before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration second-conductivity-type impurity introduction step for forming the high-concentration source / drain regions 312 and 322;
The lower layer side electrode portion 40f is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one as compared with the conventional manufacturing method. Therefore, with a small number of manufacturing steps,
Each TFT while forming a capacitive element (holding capacitor 40) with
The electrical characteristics of can be improved.

The manufacturing method of this example corresponds to the manufacturing method according to the seventh embodiment in which the high-concentration first conductivity type impurity introducing step and the high-concentration second conductivity type impurity introducing step are replaced. Therefore, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. Incorporating the lower electrode part 4
If 0f is to be formed, in the 24 steps shown in Table 7, the high-concentration first-conductivity-type impurity introduction step indicated by "N ⁺ " and the high-concentration second-conductivity-type impurity indicated by "P ⁺ " Any order of steps may be used with the introduction step replaced.

[Embodiment 14] A feature of the active matrix substrate 1 of this embodiment is that the number of mask forming steps is one less than that of the manufacturing method according to Embodiment 13, and the manufacturing method will be described below. Exactly as you would.

First, as shown in FIG. 25A, the island-shaped silicon films 10a, 20a, 30a,
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of about 1 × 10 ¹² cm ^-2 to perform channel doping (channel doping step / first impurity). Introduction process).

Next, as shown in FIG. 25B, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TF.
A resist mask 1301 is formed to cover the formation region of T20 and slightly widen the formation region of the gate electrode 35 of the second conductivity type drive circuit TFT 30 to be formed later (first mask formation step).

Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ^-2 (second impurity introduction step /
High-concentration second conductivity type impurity introduction step).

[0427] As a result, among the low concentration second conductivity type silicon film 30a, a region where a high concentration of boron ions is implanted is, high concentration source of impurity concentration of about 1 × 10 ²⁰ cm ^-3
The drain regions 312 and 322 are formed. The low concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10 ²⁰ c.
It becomes the lower layer side electrode portion 40f of the high concentration second conductivity type of m ⁻³ .
After that, the resist mask 1301 is removed.

Next, as shown in FIG. 25C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.

Next, the second conductivity type drive circuit TFT 3 is formed.
0, and a resist mask 1302 that covers the formation region of the storage capacitor 40 is formed (second mask forming step).

Subsequently, phosphorus ions were added to about 3 × 10 ¹³ cm ^-2.
Ion implantation with a dose amount of (third impurity introduction step / low-concentration first conductivity type impurity introduction step).

As a result, the low-concentration second-conductivity-type silicon films 10a and 20a have a low-concentration impurity concentration of about 2.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23. After that, the resist mask 1302 is removed.

Next, as shown in FIG. 25D, boron ions are ion-implanted at a dose of about 1 × 10 ¹³ cm ^-2 without forming a mask (the fourth impurity introduction step /
Low concentration second conductivity type impurity introduction step).

As a result, the high concentration source / drain regions 3
In the low-concentration second conductivity type silicon film 30a sandwiched between 12, 322, a low-concentration source / drain region having an impurity concentration of about 1.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. 311 and 321 are formed. The portion where no impurities are introduced becomes the channel region 33. In this way, the second conductivity type drive circuit TFT 30 is formed.

On the other hand, low concentration first conductivity type silicon film 1
Boron ions are also about 1 × 10 1, 2, 21 and 22.
^{Although the} ions are implanted with a dose amount of ¹³ cm ⁻² , the impurity concentration of the low-concentration first conductivity type silicon films 11, 12, 21, 22 is about 2.9 × 10 ¹⁸ cm ⁻³ . Therefore, the low-concentration first-conductivity-type silicon films 11, 12, 21, and 22 are substantially reduced in donor-type impurity concentration to about 1.9 × 10 ¹⁸ cm ⁻³ , but Do not flip.

Next, as shown in FIG. 25 (e), a resist mask 1303 is formed to cover the formation regions of the second conductivity type drive circuit TFT 30 and the storage capacitor 40 and to broadly cover the gate electrodes 15 and 25. Forming (third mask forming step).

Subsequently, phosphorus ions are added to about 1 × 10 ¹⁵ cm ^-2.
Ion implantation with a dose amount of (5th impurity introducing step / high-concentration first conductivity type impurity introducing step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 212, 222 are formed. In addition, low-concentration second conductivity type source / drain regions 11, 12, 21, 2
Of the two, the portion covered with the resist mask 1204 is the low concentration source / drain regions 111, 121, 211, 2 with the impurity concentration of about 1.9 × 10 ¹⁸ cm ^−3.
It becomes 21. In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1303 is removed.

Thereafter, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 1301 to 1303 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 25B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration second-conductivity-type impurity introduction step for forming the high-concentration source / drain regions 312 and 322;
The lower layer side electrode portion 40f is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

Moreover, as shown in FIG. 25D, in the step of forming the low-concentration source / drain regions 311, 321 boron ions are implanted without forming a mask. Therefore, each of the TFTs and the storage capacitor 40 can be manufactured by performing the mask forming step 3 times and the impurity introducing step 5 times.

The manufacturing method of this example corresponds to the manufacturing method of Example 8 in which the high-concentration first conductivity-type impurity introducing step and the high-concentration second conductivity-type impurity introducing step are replaced. Therefore, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. Incorporating the lower electrode part 4
If 0f is to be formed, in the 24 steps shown in Table 7, the high-concentration first-conductivity-type impurity introduction step indicated by "N ⁺ " and the high-concentration second-conductivity-type impurity indicated by "P ⁺ " Any order of steps may be used with the introduction step replaced.

[Embodiment 15] The active matrix substrate of the present embodiment and the method of manufacturing the same are basically the same as those in Embodiment 14.
Is the same as. The feature of this example is that, like the fourteenth embodiment, the number of mask forming steps is one less than that of the manufacturing method according to the thirteenth embodiment, and the manufacturing method is as described below.

First, as shown in FIG. 26A, island-shaped silicon films 10a, 20a, 30a, and
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Next, channel ions are implanted by implanting boron ions (second conductivity type impurities / second conductivity type impurities) with a dose amount of about 1 × 10 ¹² cm ⁻² (channel doping step / first impurity). Introduction process).

As a result, the silicon films 10a, 20a, 3
0a and 40a have an impurity concentration of about 1 × 10 17 cm −3.
Low concentration second conductivity type silicon films 10a, 20a, 30
a and 40a.

Next, as shown in FIG. 26B, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TF.
A resist mask 1401 is formed to cover the formation region of T20 and widen the formation planned region of the gate electrode 35 of the second conductivity type drive circuit TFT 30 to be formed later (first mask formation step).

Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ^-2 (second impurity introduction step /
High-concentration second conductivity type impurity introduction step).

As a result, in the low-concentration second-conductivity-type silicon film 30a, the region in which the high-concentration boron ions are implanted has a high-concentration source concentration of about 1 × 10 ²⁰ cm ^-3.
The drain regions 312 and 322 are formed. The low concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10 ²⁰ c.
It becomes the lower layer side electrode portion 40f of the high concentration second conductivity type of m ⁻³ .
After that, the resist mask 1401 is removed.

Next, as shown in FIG. 26C, gate electrodes 15, 25 and 35 made of doped silicon, a silicide film or the like are formed on the surfaces of the gate insulating films 14, 24 and 34. At the same time, the upper layer side electrode portion 45 is formed on the surface of the dielectric film 44 (gate electrode forming step). The upper layer side electrode portion 45 may be a part of the signal line in the previous stage.
In this way, the lower layer side electrode portion 40f and the upper layer side electrode portion 45
Form a storage capacitor 40 opposed to each other via the dielectric film 44.

Next, a resist mask 1402 covering the formation regions of the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TFT 20 is formed (second mask forming step).

Subsequently, boron ions are added to about 3 × 10 ¹³ cm.
Ion implantation is performed at a dose of ^-2 (third impurity introduction step / low concentration second conductivity type impurity introduction step).

As a result, the high concentration source / drain regions 3
In the low-concentration second conductivity type silicon film 30a sandwiched between 12, 322, the low-concentration source / drain regions whose impurity concentration is about 3.1 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrode 35. 311 and 321 are formed. The portion where no impurities are introduced becomes the channel region 33. In this way, the second conductivity type drive circuit TFT 30 is formed.
After that, the resist mask 1402 is removed.

Next, as shown in FIG. 26D, phosphorus ions are ion-implanted at a dose of about 1 × 10 ¹³ cm ^-2 without forming a mask (4th impurity introduction step / low concentration). First conductivity type impurity introduction step).

As a result, the low-concentration second conductivity type silicon films 10a and 20a have a low-concentration impurity concentration of about 0.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23.

Here, the low concentration source / drain region 31
In 1 and 321, phosphorus ion is about 1 × 1013 cm-2
Although the ion implantation is performed with a dose amount of, the impurity concentration of the low concentration source / drain regions 311 and 321 is about 3.1 × 1.
It is 0 ¹⁸ cm ^-3 . Therefore, the low-concentration source / drain regions 311 and 321 have a substantially low acceptor-type impurity concentration of about 2.1 × 10 ¹⁸ cm ⁻³ , but the conductivity type is not inverted.

Next, as shown in FIG. 26E, a resist mask 1403 is formed to cover the formation regions of the second-conductivity-type drive circuit TFT 30 and the storage capacitor 40 and to broadly cover the gate electrodes 15 and 25. Forming (third mask forming step).

Subsequently, phosphorus ions were added to about 1 × 10 ¹⁵ cm ^-2.
Ion implantation with a dose amount of (5th impurity introducing step / high-concentration first conductivity type impurity introducing step).

As a result, in the low concentration first conductivity type source / drain regions 11, 12, 21 and 22, the high concentration source / drain regions 11 having the impurity concentration of 1 × 10 ²⁰ cm ⁻³ are formed.
2, 122, 212, 222 are formed. In addition, low-concentration first conductivity type source / drain regions 11, 12, 21, 2
2, the portion covered with the resist mask 1403 is the low concentration source / drain regions 111, 121, 211, 2 with the impurity concentration of about 0.9 × 10 ¹⁸ cm ^−3.
It becomes 21. In this way, the first conductivity type pixel TFT
10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1403 is removed.

After that, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and thereafter, contact holes are formed to form the source / drain electrodes 16, 17, 26, 27. , 36, 37, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask forming steps for forming the resist masks 1401 to 1403 and five impurity introducing steps.

As described above, according to the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 26B, the high electrode is formed before the gate electrodes 15, 25, 35 and the upper electrode 45 are formed. A high-concentration second-conductivity-type impurity introduction step for forming the high-concentration source / drain regions 312 and 322;
The lower layer side electrode portion 40f is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

Moreover, as shown in FIG. 26D, the lightly doped source / drain regions 111, 121, 211, 221 are formed.
In the step for forming the film, phosphorus ions are implanted without forming a mask. Therefore, 3 mask formation steps and 5
Each TFT and storage capacitor 4 is
0 can be manufactured.

The manufacturing method of this example corresponds to the manufacturing method of the ninth embodiment in which the high-concentration first conductivity type impurity introducing step and the high-concentration second conductivity type impurity introducing step are replaced. Therefore, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. Incorporating the lower electrode part 4
If 0f is to be formed, in the 24 steps shown in Table 7, the high-concentration first-conductivity-type impurity introduction step indicated by "N ⁺ " and the high-concentration second-conductivity-type impurity indicated by "P ⁺ " Any order of steps may be used with the introduction step replaced.

[Embodiment 16] FIG. 27 is a sectional view schematically showing the structure of an active matrix substrate having a built-in drive circuit in the liquid crystal display device of this embodiment. In the active matrix substrate of this example, the basic structure of each TFT is substantially the same as that of the active matrix substrate shown in FIG.

In FIG. 27, even in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, both the first-conductivity-type drive circuit TFT 20 and the first-conductivity-type pixel TFT 10 are used. It has an LDD structure.

On the other hand, the second conductivity type drive circuit T
The FT 30 'has an offset gate structure, and the offset regions 311' and 321 'are the channel regions 33.
Similarly, the impurity concentration is about 1 × 10 ¹⁷ cm ^{−3 in} the low concentration second conductivity type region.

In this example, the lower electrode portion 40d of the storage capacitor 402 has an impurity concentration of 1 × 10 ²⁰ formed at the same time as the high concentration source / drain regions 312 and 322 of the second conductivity type drive circuit TFT 30 '. It is a high concentration second conductivity type region of cm ⁻³ .

Active matrix substrate 1 having such a structure
Can be produced by the following method.

First, as shown in FIG. 28 (a), island-shaped silicon films 10a, 20a, 30a, are formed on the surface of the insulating substrate 2.
After forming 40a (silicon film forming step), the gate insulating films 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).

Then, boron ions are implanted at a dose of 1 × 10 ¹² cm ^-2 to perform channel doping (channel doping step / first impurity introduction step).

Next, as shown in FIG. 28B, the first-conductivity-type pixel TFT 10 and the first-conductivity-type drive circuit TF.
A resist mask 15 that covers the formation region of T20 and widely covers the formation region of the gate electrode 35 to be formed later in the formation region of the second conductivity type drive circuit TFT 30 '.
01 is formed (first mask forming step).

Subsequently, a second conductivity type impurity such as boron ion is ion-implanted at a dose amount of about 1 × 10 ¹⁵ cm ^-2 (second impurity introduction step / high concentration second conductivity type impurity introduction step).

As a result, high concentration source / drain regions 312 and 322 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ are formed in the low concentration second conductivity type silicon film 30a. On the other hand, in the low-concentration second-conductivity-type silicon film 30a, the portion covered with the resist mask 1501 has an impurity concentration of about 1 × 10 ¹⁷ cm ^{−3 as} an offset region 31.
1 ', 321'. Of course, the channel region 33 remains as a low-concentration second conductivity type region having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ . The silicon film 40a has a high-concentration second-conductivity-type lower-layer side electrode portion 4 having an impurity concentration of about 1 × 10 ²⁰ cm ^−3.
It becomes 0f. After that, the resist mask 1501 is removed.

Next, as shown in FIG. 28C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.

Next, the second conductivity type drive circuit TFT 30 is provided.
And a resist mask 15 covering the formation region of the storage capacitor 40.
02 is formed (second mask forming step).

In this state, phosphorus ions were added at 1 × 10 ¹³ cm
Ion implantation is performed at a dose of ^-2 (low-concentration first conductivity type impurity introduction step / third impurity introduction step).

As a result, the low-concentration first-conductivity-type silicon films 10a and 20a have a low-concentration impurity concentration of about 0.9 × 10 ¹⁸ cm ^{−3 in} a self-aligned manner with the gate electrodes 15 and 25. One conductivity type source / drain regions 11, 12, 2
1, 22 are formed. The portions where no impurities are introduced become the channel regions 13 and 23. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1502 is removed.

Next, as shown in FIG. 28D, a resist mask 1503 which covers the formation regions of the second-conductivity-type drive circuit TFT 30 and the storage capacitor 40 and also broadly covers the gate electrodes 15 and 25. Are formed (third mask formation step).

In this state, phosphorus ions are added at 1 × 10 ¹⁵ cm
Ion implantation is performed at a dose of ^-2 (high-concentration first conductivity type impurity introduction step / 4th impurity introduction step).

As a result, the low-concentration first conductivity type source / drain regions 11, 12, 21, 22 have a high-concentration source / drain region 11 with an impurity concentration of 1 × 10 ²⁰ cm ^−3.
2, 122, 212, 222 are formed. On the other hand, low-concentration first conductivity type source / drain regions 11, 12, 2
Of those 1 and 22, the portion covered with the resist mask 1503 has an impurity concentration of about 0.9 × 10 ¹⁸ cm ^−3.
Low concentration source / drain regions 111, 121, 21
It becomes 1,221. In this way, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are formed. After that, the resist mask 1503 is removed.

Therefore, the resist masks 1503 to 150
The active matrix substrate 1 can be manufactured by three mask forming steps for forming No. 3 and four impurity introducing steps.

As described above, according to the method for manufacturing the active matrix substrate 1 of this example, as shown in FIG. 28B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, a high concentration A high-concentration second-conductivity-type impurity introducing step for forming the source / drain regions 311 and 321 is performed, and the lower layer side electrode portion 40f is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

Further, in this example, as shown in FIG.
In the second-conductivity-type drive circuit TFT 30 ', an offset gate structure is used instead of the LDD structure in order to make the portion facing the gate electrode 35 a low concentration region. Therefore, as compared with the third embodiment, the number of mask formation steps and the number of impurity introduction steps are reduced by one each.
That is, compared with the conventional manufacturing method, the number of times of the mask forming step and the impurity introducing step is twice each. Therefore, the electrical characteristics of the TFTs in the pixel region and the drive circuit section can be improved with the least number of manufacturing steps.

The manufacturing method of this example is the same as the manufacturing method of the tenth embodiment, except that a high-concentration first conductivity type impurity introducing step is performed.
This corresponds to a method in which the high-concentration second-conductivity-type impurity introduction step is replaced, so that the high-concentration source / drain regions 312 and 322 are formed before the gate electrodes 15, 25 and 35 and the upper layer side electrode 45 are formed. If a high-concentration second-conductivity-type impurity introduction step is performed and the lower-layer side electrode portion 40f is formed by using this step, “N ⁺ ” in 10 steps shown in Table 8 is used. Any step sequence may be used in which the high concentration first conductivity type impurity introduction step shown and the high concentration second conductivity type impurity introduction step shown by "P ⁺ " are interchanged.

[Modifications of Examples 3 to 16] As a method of introducing impurities, for example, a method of implanting all ions generated from the dopant gas without mass separation, that is, a so-called ion doping method may be used. . In this method, for example, when implanting impurities of the first conductivity type to a high concentration, a mixed gas containing about 5% PH3 and the balance hydrogen gas is used, and all the ions generated from this mixed gas are mass-produced. Drive without separating. On the other hand, in the case of implanting the first conductivity type impurity in a low concentration, all the ions generated from the mixed gas containing PH ₃ of about 5% and the balance of hydrogen gas were implanted without mass separation. After that, ions generated from pure hydrogen gas are implanted without mass separation,
It is preferable to terminate the asymmetric bonds in the silicon film. Further, as a method of introducing impurities, a plasma doping method, a laser doping method, or the like may be used in addition to the ion implantation method and the ion doping method. Further, the material of the mask is not limited to the resist mask. In either form, the first conductivity type is N type and the second conductivity type is P type.
You may reverse. That is, the pixel TFT may be of P type.

[0485]

As described above, in the semiconductor device according to the present invention, the off current is small because all the TFTs have a low concentration region in a portion facing the end portion of the gate electrode. Also, because the withstand voltage between the source and drain of the TFT is high,
Since the channel length can be shortened, high speed operation is possible.
Further, in the second-conductivity-type drive circuit TFT, the low-concentration region facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region.
Therefore, the mask forming step and the impurity introducing step can be reduced by one time, respectively, compared with the case where all the TFTs are manufactured with the LDD structure. Therefore, a semiconductor device capable of improving the electrical characteristics of each TFT can be realized with the minimum number of manufacturing steps.

In particular, when the semiconductor device according to the present invention is applied to a drive circuit built-in type active matrix substrate, a TFT in which uneven display is unlikely to occur in the pixel region
On the other hand, in the drive circuit section, malfunctions are less likely to occur, and a TFT with a small current passing through the power supply terminals of the CMOS circuit can be formed, so that the electrical characteristics of the TFT are improved for each pixel region and drive circuit section. You can do it.

In the present invention, the second conductivity type TFT having an offset structure is configured as a weak depletion mode, and the first conductivity type TFT having an LDD structure is configured as a weak enhancement mode. When the impurity concentration of the second conductivity type is set in the channel region and the offset region of the conductivity type thin film transistor, the offset structure TFT generally tends to have a smaller on-state than the LDD structure TFT. However, according to the present invention,
Even if the same absolute value gate voltage is applied, a gate bias voltage larger than that of the first conductivity type TFT is applied to the second conductivity type TFT, so that the on-current balance of both TFTs is balanced. You can secure it. Moreover, since it is realized by the impurity concentration of the second conductivity type in the channel region and the offset region of the second conductivity type thin film transistor, it is possible to secure the balance of the transistor capacitance. Therefore, a CMOS circuit capable of high speed operation can be constructed.

In the present invention, the concentration of the second conductivity type impurity contained in the channel region of the first conductivity type TFT and the concentration of the second conductivity type impurity contained in the channel region of the second conductivity type TFT,
When the second conductivity type impurity concentration included in the offset region of the second conductivity type TFT is made to be all equal, that is, the second conductivity type TFT
When the second conductivity type impurity is introduced into the channel region of the first conductivity type TFT, if the second conductivity type impurity is introduced into the channel region of the first conductivity type TFT, the second conductivity type impurity is introduced into the channel region without using a mask. Therefore, the number of processes can be reduced.

Further, in the present invention, before forming one electrode of the capacitive element on the upper layer of the semiconductor film, the low concentration source /
An impurity introduction step for forming a drain region or high-concentration source / drain regions is performed, and an impurity is introduced into a semiconductor film for forming a capacitor element by using this step, and the other electrode of the capacitor element is removed. It has a feature in configuring. Therefore, according to the present invention, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.

When forming the low-concentration source / drain regions of the TFT, when the offset gate structure is used, the mask forming step and the impurity introducing step can be reduced once as compared with the LDD structure.

A low-concentration source / drain region of the first-conductivity-type thin film transistor is doped with a first-conductivity-type impurity together with a second-conductivity-type impurity equivalent to the low-concentration source / drain region of the second-conductivity-type thin film transistor. When it is configured as one conductivity type region, the substantial impurity concentration can be changed between the low concentration source / drain region and the first electrode portion.

[0492] A step of introducing a low concentration first conductivity type impurity for forming the low concentration source / drain regions of the first conductivity type thin film transistor, and a low concentration source / drain region of the second conductivity type thin film transistor. One of the steps of introducing the low-concentration second-conductivity-type impurity into the substrate is performed without forming a mask, and the conductivity-type and the impurity concentration of the region into which both the first- and second-conductivity-type impurities are introduced. When the above is defined by the difference between the introduction amounts of the first and second conductivity type impurities, the mask forming step can be further reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a first embodiment of the present invention.

2A is an explanatory diagram of a semiconductor device such as an active matrix substrate of a liquid crystal display device using the TFT shown in FIG. 1, and FIG. 2B is an explanatory diagram of a CMOS circuit used for its driving circuit. .

FIG. 3 is a graph showing the ON / OFF current characteristics of each TFT on a semiconductor device such as the active matrix substrate shown in FIG. 1 in comparison.

4A to 4D are process sectional views showing a method for manufacturing a semiconductor device such as the active matrix substrate shown in FIG.

5A to 5D are process cross-sectional views showing another manufacturing method of the semiconductor device such as the active matrix substrate shown in FIG.

FIG. 6 is a diagram showing each TF formed on a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a second embodiment of the invention.
6 is a graph showing the on / off current characteristics of T in comparison.

FIG. 7 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Examples 3 to 5 of the present invention.

FIG. 8 is an explanatory diagram showing a structure of a storage capacitor formed in a semiconductor device such as an active matrix substrate of a liquid crystal display device.

9A to 9E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a third embodiment of the present invention.

10A to 10E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a fourth embodiment of the present invention.

11A to 11E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 6 of the present invention.

13A to 13D are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 14 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 7 of the present invention.

15A to 15E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a seventh embodiment of the present invention.

16 (a) to 16 (e) are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 8 of the present invention.

17A to 17E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a ninth embodiment of the present invention.

FIG. 18 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 10 of the present invention.

19A to 19D are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a tenth embodiment of the present invention.

FIG. 20 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 11 of the present invention.

21A to 21E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 11 of the present invention.

22A to 22E are process sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a twelfth embodiment of the present invention.

FIG. 23 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 13 of the present invention.

24A to 24E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 13 of the present invention.

25A to 25E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a fourteenth embodiment of the present invention.

26A to 26E are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to a fifteenth embodiment of the present invention.

FIG. 27 is a sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 16 of the present invention.

28A to 28D are process cross-sectional views showing a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 16 of the present invention.

FIG. 29 is a sectional view schematically showing a conventional semiconductor device such as an active matrix substrate.

FIG. 30 is a graph showing on / off leakage current characteristics of a TFT having a self-aligned structure.

FIG. 31A is a graph showing the relationship between the channel length in an N-type TFT and the withstand voltage between the source and drain, and FIG. 31B is the channel length and the source in a P-type TFT. It is a graph showing the relationship with the withstand voltage between drains.

FIG. 32 is a graph showing the on / off leakage current characteristics of the LDD structure TFT.

33A to 33F are process cross-sectional views showing the method for manufacturing a semiconductor device such as the active matrix substrate shown in FIG. 29.

[Explanation of symbols]

1, 1 ″ ... Active matrix substrate (semiconductor device) 2 ... Insulating substrate 10, 10 ″ ... N type pixel TFT 20, 20 ″ ... N type drive circuit TFT 30, 30 ′, 30 ″ ... P-type driving circuit TFTs n1, n2 ... N-type TFTs p1, p2 ... P-type TFTs 11, 12, 21, 22, 31, 32 ... Source ... Drain region 13, 23, 33 ... Channel region 14, 24, 34 ... Gate insulating film 15, 25, 35 ... Gate electrode 82 ... Data driver part (driving circuit) 83 ... Scan driver Part (driving circuit) 84, 88 ... Shift register 85, 89 ... Level shifter 90 ... Signal line 91 ... Scan line 92 ... Pixel TFT 111, 121, 211, 221, 311, 321・ ・
.Low concentration source / drain regions 311 ', 321' ... Offset regions

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78 617A

Claims (48)

[Claims] 1. A first-conductivity-type thin film transistor comprising a first channel region and a first-conductivity-type high-concentration source / drain region facing the first gate electrode via a first gate insulating film, and a second-gate electrode having a first-conductivity-type thin film transistor. A semiconductor device having a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing each other through a two-gate insulating film, wherein the first conductivity type thin film transistor is An LDD structure having a first conductivity type low concentration source / drain region between one conductivity type high concentration source / drain region and the first channel region is formed, and the first channel region has an extremely low concentration second conductivity. The second conductivity type thin film transistor has the same impurity concentration as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. Form an offset structure comprising a that offset region, wherein the second channel region is a semiconductor device, characterized in that there comprises a second conductivity type impurity of very low concentration. 2. The source of the second conductivity type thin film transistor according to claim 1, wherein the source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain current is I _DS1.・ Drain voltage is V _DS2 , gate voltage is V _GS2 , source-drain current is I
_{When DS2} is set, | V _DS1 | = | V _DS2 |, and V _GS1 = V
_2. A semiconductor device, wherein the second conductivity type impurity concentrations of the second channel region and the offset region are set so that I _DS2 > I _DS1 under the condition of _GS2 = 0. 3. The source of the second conductivity type thin film transistor according to claim 1, wherein the source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain current is I _DS1.・ Drain voltage is V _DS2 , gate voltage is V _GS2 , source-drain current is I
_{When DS2} is set, | V _DS1 | = | V _DS2 |, and V _GS1 = V
Under the condition of _GS2 , the gate voltage when I _DS2 = I _DS1 is shifted from 0 V toward the ON state of the first conductivity type thin film transistor, so that the second channel region and the offset region are A semiconductor device characterized in that a second conductivity type impurity concentration is defined. 4. The impurity concentration of the second conductivity type contained in the first channel region, and the impurity concentration of the second conductivity type contained in the second channel region according to claim 1. A semiconductor device, wherein the second conductivity type impurity concentrations included in the offset regions are all equal. 5. The first conductivity type according to claim 1, wherein the first conductivity type is N type, and the second conductivity type is P type.
A semiconductor device characterized by being a mold. 6. The method according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type.
A semiconductor device characterized by being a mold. 7. An active matrix substrate using the semiconductor device defined in claim 1, wherein the first conductivity type thin film transistor and the second conductivity type thin film transistor are CMOS in a driving circuit region. An active matrix substrate comprising a circuit, wherein at least one of the first conductivity type thin film transistor and the second conductivity type thin film transistor forms a pixel thin film transistor in a pixel region. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductivity type impurity is made to have an extremely low concentration in order to form the first channel region, the second channel region and the offset region. An extremely low-concentration second-conductivity-type impurity introducing step for introducing into the semiconductor film, a gate-electrode forming step for forming the first gate electrode and the second gate electrode, and the first-conductivity-type low-concentration source / drain region. A low-concentration first-conductivity-type impurity introduction step of introducing a low-concentration first-conductivity-type impurity into the semiconductor film to form the first-conductivity-type impurity for forming the first-conductivity-type high-concentration source / drain regions; A high-concentration first-conductivity-type impurity introduction step of introducing impurities into the semiconductor film at a high concentration; and a second-conductivity-type impurity at a high concentration to form the second-conductivity-type high-concentration source / drain regions. Takano to be introduced to A second conductivity type impurity introduction step, wherein the extremely low concentration second conductivity type impurity introduction step is performed before the gate electrode formation step, and the low concentration first conductivity type impurity introduction step is performed after the gate electrode formation. A method of manufacturing a semiconductor device, which is performed. 9. The extremely low concentration second conductivity type impurity introducing step according to claim 8, wherein the doped semiconductor film containing the second conductivity type impurity at an extremely low concentration is formed. A method of manufacturing a semiconductor device, comprising forming a gate insulating film after the second conductivity type impurity introducing step. 10. The step of introducing the extremely low concentration second conductivity type impurity according to claim 8, wherein the extremely low concentration second conductivity type impurity is introduced into the semiconductor film formed before this step. A method for manufacturing a semiconductor device, wherein a gate insulating film is formed after the step of introducing the extremely low concentration second conductivity type impurity. 11. The method of introducing an extremely low concentration second conductivity type impurity according to claim 8, wherein the semiconductor film formed before this step has a second conductivity type via a gate insulating film formed on the surface thereof. A method of manufacturing a semiconductor device, which comprises a step of introducing impurities at an extremely low concentration. 12. A first-conductivity-type thin film transistor comprising a first channel region and a first-conductivity-type high-concentration source / drain region facing the first gate electrode with a first gate insulating film interposed between the first-channel-type thin film transistor and the second gate electrode. A semiconductor device having a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing each other through a two-gate insulating film, wherein the first conductivity type thin film transistor is An LDD structure having a first conductivity type low concentration source / drain region between one conductivity type high concentration source / drain region and the first channel region is formed, and the first channel region has an extremely low concentration first conductivity. -Type impurities, the second conductivity type thin film transistor has the same impurity concentration as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. Form an offset structure comprising an offset region, said second channel region semiconductor device, characterized in that there comprises a first conductivity type impurity of very low concentration. 13. The source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain current is I _{DS1 according} to claim 12.
When the source / drain voltage of the second conductivity type thin film transistor is V _DS2 , the gate voltage is V _GS2 , and the source / drain current is I _DS2 , | V _DS1 | = | V _DS2 |, and V _GS1 =
A semiconductor device, wherein the first conductivity type impurity concentrations of the second channel region and the offset region are set so that I _DS2 > I _DS1 under the condition of V _GS2 = 0. 14. In claim 12, wherein the first conductivity type source-drain voltage V _DS1 of the thin film transistor, the gate voltage V _GS1, the source-drain current as I _DS1,
When the source / drain voltage of the second conductivity type thin film transistor is V _DS2 , the gate voltage is V _GS2 , and the source / drain current is I _DS2 , | V _DS1 | = | V _DS2 |, and V _GS1 =
Under the condition of V _GS2 , the gate voltage when I _DS2 = I _DS1 is shifted from 0 V in the direction in which the first conductivity type thin film transistor is turned on, so that the second channel region and the offset region are The semiconductor device characterized in that the first-conductivity-type impurity concentration is defined. 15. The impurity concentration of the first conductivity type contained in the first channel region, and the impurity concentration of the first conductivity type contained in the second channel region according to claim 12. A semiconductor device, wherein the first conductivity type impurity concentrations included in the offset regions are all equal. 16. The semiconductor device according to claim 12, wherein the first conductivity type is N type and the second conductivity type is P type. 17. The semiconductor device according to claim 12, wherein the first conductivity type is P type and the second conductivity type is N type. 18. An active matrix substrate using the semiconductor device according to claim 12, wherein the first conductivity type thin film transistor and the second conductivity type thin film transistor are CMOS in a drive circuit region. An active matrix substrate comprising a circuit, wherein at least one of the first conductivity type thin film transistor and the second conductivity type thin film transistor forms a pixel thin film transistor in a pixel region. 19. The method of manufacturing a semiconductor device according to claim 12, wherein the first conductivity type impurity is made to have an extremely low concentration in order to form the first channel region, the second channel region and the offset region. An extremely low-concentration first-conductivity-type impurity introducing step for introducing into the semiconductor film, a gate-electrode forming step for forming the first gate electrode and the second gate electrode, and a first-conductivity-type low-concentration source / drain region. A low-concentration first-conductivity-type impurity introduction step of introducing a low-concentration first-conductivity-type impurity into the semiconductor film to form the first-conductivity-type impurity for forming the first-conductivity-type high-concentration source / drain regions; A high-concentration first-conductivity-type impurity introduction step of introducing impurities into the semiconductor film at a high concentration; and a second-conductivity-type impurity at a high concentration to form the second-conductivity-type high-concentration source / drain regions. To introduce Concentration second conductivity type impurity introduction step, the extremely low concentration first conductivity type impurity introduction step is performed before the gate electrode formation step, and the low concentration first conductivity type impurity introduction step is performed. A method of manufacturing a semiconductor device, which is performed later. 20. The ultra low concentration first conductivity type impurity introducing step according to claim 19, wherein the doped semiconductor film containing the first conductivity type impurity in an extremely low concentration is formed. A method of manufacturing a semiconductor device, which comprises forming a gate insulating film after the first conductivity type impurity introducing step. 21. The extremely low concentration first conductivity type impurity introduction step according to claim 19, wherein the first conductivity type impurity is introduced at an extremely low concentration into the semiconductor film formed before this step. A method of manufacturing a semiconductor device, wherein a gate insulating film is formed after the step of introducing the extremely low concentration first conductivity type impurity. 22. The ultra-low concentration first conductivity type impurity introducing step according to claim 19, wherein the semiconductor film formed before this step has a first conductivity type via a gate insulating film formed on the surface thereof. A method of manufacturing a semiconductor device, which comprises a step of introducing impurities at an extremely low concentration. 23. A first-conductivity-type thin film transistor comprising a first channel region and a first-conductivity-type high-concentration source / drain region facing the first gate electrode with a first gate insulating film interposed therebetween; A semiconductor device having a second conductivity type thin film transistor having a second channel region and a second conductivity type high-concentration source / drain region facing each other through a two-gate insulating film, wherein the first conductivity type thin film transistor is Forming an LDD structure having a first-conductivity-type low-concentration source / drain region between the first-conductivity-type high-concentration source / drain region and the first-channel region, the first-channel region being substantially intrinsic; The two-conductivity-type thin film transistor has an offset region having the same impurity concentration as that of the second channel region between the second-conductivity-type high-concentration source / drain region and the second channel region. Form an offset structure comprising, said second channel region semiconductor device, characterized in that there substantially intrinsic. 24. The semiconductor device according to claim 23, wherein the first conductivity type is N type and the second conductivity type is P type. 25. The semiconductor device according to claim 23, wherein the first conductivity type is P type and the second conductivity type is N type. 26. An active matrix substrate using the semiconductor device defined in any one of claims 23 to 25, wherein the first conductivity type thin film transistor and the second conductivity type thin film transistor are CMOS in a drive circuit region. An active matrix substrate comprising a circuit, wherein at least one of the first conductivity type thin film transistor and the second conductivity type thin film transistor forms a pixel thin film transistor in a pixel region. 27. A thin film transistor comprising a channel region facing a gate electrode via a gate insulating film and source / drain regions connected to the channel region, and a first electrode portion and a second electrode facing each other via a dielectric film. And a low-concentration source / drain region in which the source / drain region faces the end of the gate electrode via a gate insulating film, and the low-concentration source / drain region. LDD having high-concentration source / drain regions adjacent to
A semiconductor device having a structure, wherein the first electrode portion is composed of the same semiconductor film having the same conductivity type as the low-concentration source / drain regions and the same impurity concentration of the conductivity type. 28. A thin film transistor comprising a channel region facing a gate electrode via a gate insulating film and source / drain regions connected to the channel region, and a first electrode portion and a second electrode facing each other via a dielectric film. And a low-concentration source / drain region in which the source / drain region faces the end of the gate electrode via a gate insulating film, and the low-concentration source / drain region. LDD having high-concentration source / drain regions adjacent to
A semiconductor device having a structure, wherein the first electrode portion is composed of the same semiconductor film having the same conductivity type as the high-concentration source / drain regions and the same impurity concentration of the conductivity type. 29. A thin film transistor having a channel region facing the gate electrode with a gate insulating film interposed therebetween and a source / drain region containing a high concentration of a donor impurity or an acceptor impurity, and a first electrode portion facing with a dielectric film interposed therebetween. In the semiconductor device having a capacitive element including a second electrode portion, the thin film transistor includes an offset region having an impurity concentration equivalent to that of the channel region between the source / drain region end and the channel region end. The semiconductor device is characterized in that the first electrode portion is composed of the same semiconductor film having the same conductivity type as the high-concentration source / drain regions and the same impurity concentration of the conductivity type. 30. A first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor, which have a channel region facing the gate electrode via a gate insulating film and source / drain regions connected to the channel region, and face each other via a dielectric film. In the semiconductor device having the first electrode portion and the capacitive element including the second electrode portion, the first-conductivity-type and second-conductivity-type thin film transistors have a source / drain region with a gate insulating film at an end of the gate electrode. Forming a LDD structure including a low-concentration source / drain region and a high-concentration source / drain region adjacent to the low-concentration source / drain region, and the first electrode portion includes the first conductivity type and the second conductivity type. It is characterized in that it is composed of the same semiconductor film having the same conductivity type as the low-concentration source / drain regions of the conductivity type thin film transistor and having the same impurity concentration of the conductivity type. The semiconductor device according to. 31. A first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor, which have a channel region facing the gate electrode via a gate insulating film and source / drain regions connected to the channel region, and face each other via a dielectric film. In the semiconductor device having the first electrode portion and the capacitive element including the second electrode portion, the first-conductivity-type and second-conductivity-type thin film transistors have a source / drain region with a gate insulating film at an end of the gate electrode. Forming a LDD structure including a low-concentration source / drain region and a high-concentration source / drain region adjacent to the low-concentration source / drain region, and the first electrode portion includes the first conductivity type and the second conductivity type. The high-concentration source / drain regions of the conductivity type thin film transistor are formed of the same semiconductor film having the same conductivity type and the same impurity concentration of the conductivity type. The semiconductor device according to. 32. The first electrode part according to claim 30, wherein the first electrode part contains the same amount of the first conductivity type impurity as the first conductivity type impurity contained in the low concentration source / drain regions of the first conductivity type thin film transistor. A low-concentration source / drain region of the first-conductivity-type thin film transistor, the low-concentration source / drain regions of the first-conductivity-type thin film transistor being less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity. A semiconductor device comprising the same amount of impurities of the second conductivity type as a region. 33. The first electrode part according to claim 30, containing the same amount of second conductivity type impurities as the second conductivity type impurities included in the low concentration source / drain regions of the second conductivity type thin film transistor. A low-concentration source / drain region of the first-conductivity-type thin film transistor together with a first-conductivity-type impurity in an amount less than the first-conductivity-type impurity amount, and a low-concentration source / drain of the second-conductivity-type thin film transistor; A semiconductor device comprising the same amount of impurities of the second conductivity type as a region. 34. The first electrode portion according to claim 31, wherein the first electrode portion contains the same amount of first conductivity type impurities as the first conductivity type impurities included in the high-concentration source / drain regions of the first conductivity type thin film transistor. A low-concentration source / drain region of the first-conductivity-type thin film transistor, the low-concentration source / drain regions of the first-conductivity-type thin film transistor being less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity. A semiconductor device comprising the same amount of impurities of the second conductivity type as a region. 35. The first electrode portion according to claim 31, wherein the first electrode portion contains the second conductivity type impurity in the same amount as the second conductivity type impurity included in the high-concentration source / drain regions of the second conductivity type thin film transistor. A low-concentration source / drain region of the first-conductivity-type thin film transistor together with a first-conductivity-type impurity in an amount less than the first-conductivity-type impurity amount, and a low-concentration source / drain of the second-conductivity-type thin film transistor; A semiconductor device comprising the same amount of impurities of the second conductivity type as a region. 36. A first-conductivity-type thin film transistor comprising a channel region facing the gate electrode with a gate insulating film interposed therebetween and a high-concentration first-conductivity type source / drain region containing a high-concentration first-conductivity-type impurity, and a gate electrode. A second conductive type thin film transistor having a channel region facing the gate insulating film and a high-concentration second conductive type source / drain region containing a high concentration of the second conductive type impurities, and a second conductive type thin film transistor facing the thin film transistor. In a semiconductor device having one electrode part and a capacitive element composed of a second electrode part, the first conductivity type thin film transistor is located between the high concentration first conductivity type source / drain region end part and the channel region end part. An LDD structure having a low-concentration first-conductivity-type source / drain region, and the second-conductivity-type thin film transistor includes the high-concentration second-conductivity-type source / drain region. An offset region having an impurity concentration equivalent to that of the channel region is provided between an end portion and the end of the channel region, and the first electrode portion is a low concentration first conductivity type source / drain region of the first conductivity type thin film transistor. A semiconductor device comprising a semiconductor film containing the same amount of impurities of the first conductivity type. 37. A first-conductivity-type thin film transistor having a channel region facing the gate electrode with a gate insulating film interposed therebetween and a high-concentration first-conductivity type source / drain region containing a high-concentration first-conductivity-type impurity, and a gate electrode. A second conductive type thin film transistor having a channel region facing the gate insulating film and a high-concentration second conductive type source / drain region containing a high concentration of the second conductive type impurities, and a second conductive type thin film transistor facing the thin film transistor. In a semiconductor device having a capacitive element including one electrode portion and a second electrode portion, the first conductivity type thin film transistor is provided between the high concentration first conductivity type source / drain region end portion and the channel region end portion. An LDD structure having low-concentration first conductivity type source / drain regions is formed, and the second conductivity-type thin film transistor is the high-concentration second conductivity type source / drain regions. An offset region having an impurity concentration equivalent to that of the channel region between the first portion and the end of the channel region, and the first electrode portion is the same as the high concentration first conductivity type source / drain region of the first conductivity type thin film transistor. A semiconductor device comprising a semiconductor film containing an amount of impurities of the first conductivity type. 38. A first-conductivity-type thin film transistor having a channel region facing the gate electrode with a gate insulating film interposed therebetween and a high-concentration first-conductivity type source / drain region containing a high-concentration first-conductivity-type impurity, and a gate electrode. A second conductive type thin film transistor having a channel region facing the gate insulating film and a high-concentration second conductive type source / drain region containing a high concentration of the second conductive type impurities, and a second conductive type thin film transistor facing the thin film transistor. In a semiconductor device having a capacitive element including one electrode portion and a second electrode portion, the first conductivity type thin film transistor is provided between the high concentration first conductivity type source / drain region end portion and the channel region end portion. An LDD structure having low-concentration first conductivity type source / drain regions is formed, and the second conductivity-type thin film transistor is the high-concentration second conductivity type source / drain regions. An offset region having an impurity concentration equivalent to that of the channel region between the first region and the end of the channel region, and the first electrode portion is the same as the high concentration second conductivity type source / drain region of the second conductivity type thin film transistor. A semiconductor device comprising a semiconductor film containing an amount of impurities of the second conductivity type. 39. An active matrix substrate using the semiconductor device defined in claim 27, wherein the first conductivity type and the second conductivity type thin film transistors are CMOS in a drive circuit section. A circuit, wherein at least one of the first conductivity type thin film transistor and the second conductivity type thin film transistor constitutes a pixel thin film transistor in a pixel region, and the capacitive element holds a liquid crystal cell in the pixel region. An active matrix substrate characterized by comprising a capacitor. 40. An LDD thin film transistor comprising a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region conductively connected to the channel region via a low concentration source / drain region, and a dielectric film. In a method of manufacturing a semiconductor device having a capacitive element composed of a first electrode portion and a second electrode portion that face each other, a semiconductor constituting at least the channel region, the low-concentration source / drain region, and the first electrode portion. A first step of forming a film, and a second step of forming a low concentration source / drain region and the first electrode part by introducing an impurity which becomes a donor or an acceptor into a part of the semiconductor film at a low concentration A method for manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of the second step. 41. An LDD thin film transistor comprising a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region conductively connected to the channel region via a low concentration source / drain region, and a dielectric film. In a method of manufacturing a semiconductor device having a capacitive element composed of a first electrode portion and a second electrode portion that face each other, a semiconductor forming at least the channel region, the high-concentration source / drain region, and the first electrode portion. A first step of forming a film, and a second step of forming a high-concentration source / drain region and the first electrode part by introducing a high-concentration impurity serving as a donor or an acceptor into a part of the semiconductor film. A method for manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of the second step. 42. A gate electrode, a gate insulating film, a channel region, an offset region containing the same amount of impurities as the channel region, and a high-concentration source / drain region conductively connected to the channel region via the offset region. And a high-concentration source / drain region at least in the channel region and the high-concentration source / drain region. And a first step of forming a semiconductor film forming the first electrode portion, and introducing a high-concentration impurity serving as a donor or an acceptor into a part of the semiconductor film to form the high-concentration source / drain regions and the first A semiconductor device comprising: a second step of forming one electrode portion; and a third step of forming a gate electrode and a second electrode portion after the completion of the second step. Production method. 43. An LDD including a gate electrode, a gate insulating film, a channel region, and a high-concentration first conductivity type source / drain region conductively connected to the channel region through a low-concentration first conductivity type source / drain region. Type first conductivity type thin film transistor, a gate electrode, a gate insulating film, a channel region, and a high concentration second conductivity type source for conductively connecting to the channel region through a low concentration second conductivity type source / drain region.
A method for manufacturing a semiconductor device having an LDD type second conductivity type thin film transistor having a drain region and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed between them. Forming a channel region of the first conductivity type thin film transistor of the first conductivity type, a source / drain region of a low concentration first conductivity type, a channel region of the second conductivity type thin film transistor of the LDD type, and a semiconductor film forming the first electrode portion A second step of introducing a first conductivity type impurity at a low concentration into a part of the semiconductor film to form the low concentration first conductivity type source / drain region and the first electrode portion; A method of manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of two steps. 44. An LDD including a gate electrode, a gate insulating film, a channel region, and a high-concentration first conductivity type source / drain region conductively connected to the channel region through a low-concentration first conductivity type source / drain region. Type first conductivity type thin film transistor, a gate electrode, a gate insulating film, a channel region, and a high concentration second conductivity type source for conductively connecting to the channel region through a low concentration second conductivity type source / drain region.
A method for manufacturing a semiconductor device having an LDD type second conductivity type thin film transistor having a drain region and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed between them. Forming a channel region of the first-conductivity-type thin film transistor, a high-concentration first-conductivity-type source / drain region, a channel region of the LDD-type second-conductivity-type thin film transistor, and a semiconductor film forming the first electrode portion A second step of introducing a high-concentration first-conductivity-type impurity into a part of the semiconductor film to form the high-concentration first-conductivity-type source / drain regions and the first electrode portion; A method of manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of two steps. 45. The semiconductor according to any one of claims 43 to 44, wherein the first-conductivity-type impurity is doped at a low concentration to form a low-concentration first-conductivity-type source / drain region of the LDD-type first-conductivity-type thin film transistor. A low-concentration first-conductivity-type impurity introducing step into the film, or a low-concentration second-conductivity-type impurity for forming the low-concentration second-conductivity source / drain regions of the LDD-type second-conductivity-type thin film transistor. One of the low-concentration impurity introduction steps of the low-concentration second-conductivity-type impurity introduction step to be introduced into the semiconductor film is performed without forming a mask, and impurities of both the first-conductivity-type impurities and the second-conductivity-type impurities are introduced. The method for manufacturing a semiconductor device is characterized in that the conductivity type and the substantial impurity concentration of the region to be formed are defined by the difference between the introduction amounts of the first conductivity type impurity and the second conductivity type impurity. 46. A gate electrode, a gate insulating film, a first channel region, and a high-concentration first conductivity type source / drain region conductively connected to the first channel region through a low-concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor, a gate electrode, a gate insulating film, a second channel region, a high concentration second conductivity type source / drain region, and an end of the second channel region and the high concentration second conductivity type An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of the second channel region between the source / drain region ends, and a first electrode portion and a second electrode facing each other with a dielectric film interposed therebetween. A capacitive element consisting of
In a method of manufacturing a semiconductor device having: a semiconductor film forming at least the first channel region, the low-concentration first conductivity type source / drain region, the second channel region, and the first electrode portion. A first step, and a second step of forming a low concentration first conductivity type source / drain region and the first electrode portion by introducing a low concentration first conductivity type impurity into a part of the semiconductor film; A method of manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of the second step. 47. A gate electrode, a gate insulating film, a first channel region, and a high-concentration first conductivity type source / drain region which is conductively connected to the first channel region through a low-concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor, a gate electrode, a gate insulating film, a second channel region, a high concentration second conductivity type source / drain region, and an end of the second channel region and the high concentration second conductivity type An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of the second channel region between the source / drain region ends, and a first electrode portion and a second electrode facing each other with a dielectric film interposed therebetween. A capacitive element consisting of
In a method for manufacturing a semiconductor device having: a semiconductor film forming at least the first channel region, the high-concentration first conductivity type source / drain region, the second channel region, and the first electrode portion. A first step, and a second step of introducing a high-concentration first-conductivity-type source / drain region and the first electrode part by introducing a high-concentration first-conductivity-type impurity into a part of the semiconductor film; A method of manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of the second step. 48. A gate electrode, a gate insulating film, a first channel region, and a high concentration first conductivity type source / drain region conductively connected to the first channel region through a low concentration first conductivity type source / drain region. An LDD type first conductivity type thin film transistor, a gate electrode, a gate insulating film, a second channel region, a high concentration second conductivity type source / drain region, and an end of the second channel region and the high concentration second conductivity type An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as that of the second channel region between the source / drain region ends, and a first electrode portion and a second electrode facing each other with a dielectric film interposed therebetween. A capacitive element consisting of
In a method of manufacturing a semiconductor device having: a semiconductor film forming at least the first channel region, the second channel region, the high-concentration second conductivity type source / drain region, and the first electrode portion. A first step, and a second step of forming a high-concentration second-conductivity-type source / drain region and the first electrode part by introducing a second-conductivity-type impurity at a high concentration into a part of the semiconductor film; A method of manufacturing a semiconductor device, comprising: a third step of forming a gate electrode and a second electrode portion after completion of the second step.