JP3948034B2 - Semiconductor device, manufacturing method thereof, and active matrix substrate - Google Patents

Description

【０１５３】
即ち表１には、低濃度第二導電型不純物導入工程をＣ／Ｄ（Ｐ^- ）、ゲート電極形成工程をＧａｔｅ、低濃度第一導電型不純物導入工程をＮ^- 、高濃度第一導電型不純物導入工程をＮ⁺ 、及び高濃度第二導電型不純物導入工程をＰ⁺ で示してあり、その内の条件Ａは、図４を参照して説明した工程順序で有り、その内の条件Ｃは、図５を参照して説明した工程順序で有る。
【０１５４】
低濃度第二導電型不純物導入工程は、低濃度第二導電型不純物を含むドープト半導体膜を成膜する工程で作成してもよい。例えば、ボロンをドープするとき、ＣＶＤ炉にモノシラン（ＳｉＨ₄ ）やジシラン（Ｓｉ₂ Ｈ₆ ）と同時にジボラン（Ｂ₂ Ｈ₆ ）を導入する事によって得られる。ＬＰＣＰＤ法でこれらドープト半導体膜を堆積する場合、ジボラン等の添加物の濃度は、０．１ｐｐｍから１００ｐｐｍ程度が好ましく、希釈ガスは水素、ヘリウム、窒素が適して居る。一方、ＰＥＣＶＤ法で堆積する場合は、濃度は先と同じで有るが、希釈ガスは、ヘリウム、アルゴンなどが適して居る。こうして、ドープト半導体膜を堆積した後、パターニングを施し、さらにゲート絶縁膜を半導体膜の表面に形成してもよい。
【０１５５】
又不純物導入方法としては、例えば、ドーパントガスから発生した全てのイオンを質量分離せずに打ち込む方法、いわゆるイオンドーピング法を用いてもよい。この方法で、例えば、第一導電型の不純物を高濃度に打ち込む場合には、ＰＨ₃ を約１％〜約１０％含み、残部が水素ガスやヘリウムガスからなる混合ガスを用い、この混合ガスから発生する全てのイオンを質量分離せずに打ち込む。これに対して、第一導電型の不純物を低濃度に打ち込む場合には、ＰＨ₃ を約０．０１％〜約１％含み、残部が水素ガス等からなる混合ガスから発生する全てのイオンを質量分離せずに打ち込んだ後、純水素ガスから発生するイオンを質量分離せずに打ち込んで、シリコン膜中の不整結合を終端化する事が好ましい。更に不純物の導入方法については、イオン注入法やイオンドーピング法の他にも、プラズマドーピング法、レーザドーピング法などを用いてもよい。
【０１５６】
本例のアクティブマトリクス基板１では、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の第一導電型の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１の不純物濃度を約１．０×１０¹⁸ｃｍ^-3とし、第一導電型の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２の不純物濃度を約１．０×１０²⁰ｃｍ^-3としたが、かかる濃度については、アクティブマトリクス基板１の仕様などに応じて最適な値に設定されるべき性質のもので有り、上記の数値に限らない。さらに又マスクの材質についてもレジストマスクに限らない。
【０１５７】
［実施例３］
（アクティブマトリクス基板の構成）
図７は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図、図８は、液晶表示装置の構成を模式的に示すブロック図で有る。
【０１５８】
図７に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板では、その左側領域から右側領域に向かって駆動回路部、画素領域、及びこの画素領域内の保持容量形成領域を模式的に示す様に、第二導電型の駆動回路用ＴＦＴ３０、第一導電型の駆動回路用ＴＦＴ２０、第一導電型の画素用ＴＦＴ１０、及び保持容量４０が同一の絶縁基板２の上に形成されて居る。
【０１５９】
本例では、図８に示す様に、画素領域には前段の走査線９１との間に保持容量４０が形成され、この保持容量４０は液晶セル（液晶容量９４）での電荷の保持特性を高める機能を有して居る。この保持容量４０は、画素用ＴＦＴ１０を形成する為のシリコン膜Ｓ１と同時形成されたシリコン膜Ｓ２を導電化したものを下層側電極部４０ｃ（第一の電極部）とし、この下層側電極部４０ｃに対して前段の走査線９１から張り出した上層側電極部４５（第二の電極部）が重なった状態に有る。尚保持容量４０は、各画素領域に於いて前段の走査線９１との間に構成されているが、専用の容量線との間に構成される場合も有る。
【０１６０】
再び、図７に於いて、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０は、いずれも、ソース・ドレイン領域１１、１２、２１、２２、３１、３２の間にチャネルを形成する為のチャネル領域１３、２３、３３を有して居る。これらのチャネル領域１３、２３、３３は、低濃度のボロンイオンによってチャネルドープしてある為、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域で有る。従って、第一導電型の駆動回路用ＴＦＴ２０および第二導電型の駆動回路用ＴＦＴ３０のスレッショルド電圧（Ｖｔｈ）を所定の値に設定して有る。一般に、正孔の移動度は電子の移動度に比して小さい為、従来は、第二導電型の駆動回路用ＴＦＴのオン電流が第一導電型の駆動回路用ＴＦＴのオン電流に比して著しく小さい傾向にあった。かかる問題点は、本例では、Ｖｔｈを調整する事により、ほぼ解消できて居る。それ故、本例のアクティブマトリクス基板１では、ＣＭＯＳ回路を構成するＴＦＴ間に於けるオン電流のバランスがよい。
【０１６１】
第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０は、チャネル領域１３、２３、３３の表面側に対して、ゲート絶縁膜１４、２４、３４（厚さが約１２００オングストロームのシリコン酸化膜）を介して対峙するゲート電極１５、２５、３５を有する。
【０１６２】
この様に構成したアクティブマトリクス基板１に於いて、ソース・ドレイン領域１１、１２、２１、２２、３１、３２は、ゲート電極１５、２５、３５の端部に対してゲート絶縁膜１４、２４、３４を介して対峙する部分に低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１、３１１、３２１を有しており、いずれのＴＦＴもＬＤＤ構造になって居る。
【０１６３】
尚第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０のソース・ドレイン領域１１、１２、２１、２２、３１、３２の内、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１、３１１、３２１を除く領域は、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２、３１２、３２２で有る。これらの高濃度領域に対して、各ＴＦＴに対する信号線や画素電極などのソース・ドレイン電極１６、１７、２６、２７、３６、３７が層間絶縁膜４のコンタクトホールを介して電気的に接続して居る。
【０１６４】
（ＴＦＴのオン・オフリーク電流特性）
この様に構成したＴＦＴは、ゲート電極１５、２５、３５の端部に対峙する部分が低濃度領域（低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１）で有る為、ドレイン端に於ける電界強度が緩和された状態に有る。それ故、図３２に第一導電型のＴＦＴ（第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０）のドレイン電流−ゲート電圧特性を実線Ｌ３で示し、第二導電型のＴＦＴ（第二導電型の駆動回路用ＴＦＴ３０）のドレイン電流−ゲート電圧特性を点線Ｌ４で示す様に、ＴＦＴのオフリーク電流が著しく小さい。
【０１６５】
又図３１（ａ）にＬＤＤ構造の第一導電型のＴＦＴ（第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０）に於ける耐電圧特性を実線Ｌ２１で示し、図３１（ｂ）にＬＤＤ構造の第二導電型のＴＦＴに於ける耐電圧特性を実線Ｌ２２で示す様に、ＬＤＤ構造のＴＦＴは、セルフアライン構造のＴＦＴに比較して、ソース・ドレイン間の耐電圧が高いので、チャネル長を短くする事が出来る。
【０１６６】
（ＴＦＴの製造方法）
斯様な構造のアクティブマトリクス基板１は、例えば以下の方法により製造出来る。尚以下の説明に於いて、不純物濃度はいずれも活性化アニール後の不純物濃度で表して有る。
【０１６７】
まず、ＴＦＴのＶｔｈを調整する為に、半導体膜に低濃度で不純物を導入する。即ち図９（ａ）に示す様に、石英基板などの絶縁基板２の表面の内、画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域に、例えば、不純物濃度が１×１０¹⁷ｃｍ^-3の低濃度第二導電型のシリコン膜１０ａ、２０ａ、３０ａ、４０ａ、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を同時に形成する（低濃度第二導電型シリコン膜形成工程）。
【０１６８】
それには、絶縁基板２の表面に、ＬＰＣＶＤ法またはプラズマＣＶＤ法などを用いて真性のポリシリコン膜を形成した後、ポリシリコン膜をフォトリソグラフィ法によってパタニングして、それを島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａにする（シリコン膜形成工程）。
【０１６９】
尚ポリシリコン膜は、アモルファスシリコン膜を形成した後、レーザアニール法または固相成長法により結晶粒を成長させて形成する場合も有る。次に、島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａに対して、熱酸化法、ＴＥＯＳ−ＣＶＤ法、ＬＰＣＶＤ法、プラズマＣＶＤ法、ＨＴＯ法などにより、厚さが約１２００オングストロームのシリコン酸化膜からなるゲート絶縁膜１４、２４、３４、及び誘電体膜４４を同時に形成する（ゲート絶縁膜形成工程）。
【０１７０】
しかる後に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第２導電型不純物）を打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。その結果、シリコン膜１０ａ、２０ａ、３０ａ、４０ａは、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型のシリコン膜１０ａ、２０ａ、３０ａ、４０ａとなる。
【０１７１】
次に、図９（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、ゲート電極１５、２５の形成予定領域をわずか広めに覆うレジストマスク１０１を形成する（１回目のマスク形成工程）。
【０１７２】
続いて、例えば、リンイオン（第一導電型不純物／第一導電型不純物）を約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０１７３】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａの内、リンイオンが打ち込まれた領域は、導電型が反転して不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２となる。又低濃度第二導電型のシリコン膜４０ａは、導電型が反転して不純物濃度が約１×１０１９ｃｍ−３の低濃度第一導電型の下層側電極部４０ｃ（第一の電極部）となる。又不純物が導入されなかった部分がチャネル領域１３、２３となる。しかる後に、レジストマスク１０１を除去する。
【０１７４】
次に、図９（ｃ）に示す様に、ゲート絶縁膜１４、２４、３４の表面にドープドシリコンやシリサイド膜などからなるゲート電極１５、２５、３５を形成する。同時に、誘電体膜４４の表面には上層側電極部４５（第二の電極部）を形成する（ゲート電極形成工程）。この上層側電極部４５は前段の信号線の一部であってもよい。この様にして、下層側電極部４０ｃと上層側電極部４５とが誘電体膜４４を介して対向する保持容量４０を形成する。
【０１７５】
次に、第一導電型の画素用ＴＦＴ１０の形成領域、第一導電型の駆動回路用ＴＦＴ２０の形成領域、及び保持容量４０を覆うレジストマスク１０２を形成する（２回目のマスク形成工程）。
【０１７６】
続いて、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０１７７】
その結果、低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。しかる後に、レジストマスク１０２を除去する。
【０１７８】
次に、図９（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０の形成領域、第一導電型の駆動回路用ＴＦＴ２０の形成領域、及び保持容量４０を覆うと共に、ゲート電極３５を広めに覆うレジストマスク１０３を形成する（３回目のマスク形成工程）。
【０１７９】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０１８０】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク１０３で覆われていた部分はそのまま不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０１８１】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク１０３を除去する。
【０１８２】
次に、図９（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０に加えて、ゲート電極１５、２５をも広めに覆うレジストマスク１０４を形成する（４回目のマスク形成工程）。
【０１８３】
続いて、リンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０１８４】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２２１、２２２が形成される。又低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１０４で覆われていた部分はそのまま不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。
【０１８５】
この様にして、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１０４を除去する。
【０１８６】
以降、図７に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク１０１〜１０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によってアクティブマトリクス基板１等の半導体装置を製造出来る。
【０１８７】
この様に、本例のアクティブマトリクス基板１の製造方法では、図９（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｃを形成して居る。従って、従来の製造方法に比較してマスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有る。それ故、少ない製造工程数によってＴＦＴと容量素子（保持容量４０）を形成しながら、各ＴＦＴの電気的特性を向上する事が出来る。
【０１８８】
尚表２乃至表４に於いて、チャネルドープ工程を「Ｃ／Ｄ」、低濃度第１導電型不純物導入工程を「Ｎ^- 」、高濃度第一導電型不純物導入工程を「Ｎ⁺ 」、低濃度第二導電型不純物導入工程を「Ｐ^- 」、高濃度第二導電型不純物導入工程を「Ｐ⁺ 」、ゲート電極形成工程を「Ｇ」で略しながら工程順序を示す様に、図９（ｃ）に示す低濃度第二導電型不純物導入工程、図９（ｄ）に示す高濃度第二導電型不純物導入工程、及び図９（ｅ）に示す高濃度第一導電型不純物導入工程の間でその順序を入れ換えるなど、ゲート電極１５、２５、３５、および上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｃを形成するのであれば、いずれの工程順序であってもよい。
【０１８９】
【表２】

【０１９０】
【表３】

【０１９１】
【表４】

【０１９２】
［実施例４］
本例のアクティブマトリクス基板の構造については、実施例３と同じく図７を参照して説明する。
【０１９３】
図７に於いて、本例のアクティブマトリクス基板１の特徴点は、実施例３に係る製造方法と同じ工程数で製造しながら、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を保持容量４０の下層側電極部４０ｃよりも低濃度化した点に有る。
【０１９４】
即ち保持容量４０の下層側電極部４０ｃは、実施例３と同様、不純物濃度が約１×１０１９ｃｍ−３の低濃度第一導電型領域で有るが、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１は、保持容量４０の下層側電極部４０ｃと同等量のリンイオン（不純物濃度で約１×１０¹⁹ｃｍ^-3のリンイオン）で有ると共に、第二導電型の駆動回路用ＴＦＴ３０の低濃度領域３１１、３２１と同等量のボロンイオン（不純物濃度で約１．１×１０¹⁸ｃｍ^-3のボロンイオン）が導入された低濃度第第一導電型領域で有る。従って、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１の不純物濃度は、約９×１０¹⁸ｃｍ^-3で有る。
【０１９５】
斯様な構成のアクティブマトリクス基板１は、以下に説明する製造方法により製造する事が出来る。尚以下に説明する製造方法は、実施例３と共通する工程を有するので、かかる工程については簡単に説明する。
【０１９６】
まず、図１０（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０１９７】
次に、１×１０¹²ｃｍ^-2のドーズ量でボロンイオンを打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０１９８】
次に、図１０（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０のゲート電極１５、２５の形成領域をわずか広めに覆うレジストマスク２０１を形成する（１回目のマスク形成工程）。
【０１９９】
続いて、リンイオンを約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入し（２回目の不純物導入工程／低濃度第一導電型不純物導入工程）、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２、および低濃度第一導電型の下層側電極部４０ｃを形成する。
【０２００】
次に、図１０（ｃ）に示す様に、ゲート電極１５、２５、３５及び上層側電極部４５を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０２０１】
以上の各工程は、実施例３に係る製造方法と同じで有る。
【０２０２】
次に、保持容量４０の形成領域を覆うと共に、レジストマスク２０１と同様、ゲート電極１５、２５をもわずか広めに覆うレジストマスク２０２を形成する（２回目のマスク形成工程）。
【０２０３】
続いて、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０２０４】
その結果、シリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。
【０２０５】
一方、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２は、そこに打ち込まれたボロンイオンによって実質的に低濃度化し、低濃度第一導電型のソース・ドレイン領域１１、１２、１１、１２の不純物濃度は、約９×１０¹⁸ｃｍ^-3となる。しかる後に、レジストマスク２０２を除去する。
【０２０６】
以降は、実施例３と同様、図１０（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０の形成領域、第一導電型の駆動回路用ＴＦＴ２０の形成領域、及び保持容量４０を覆うと共に、ゲート電極３５を広めに覆うレジストマスク２０３を形成する（３回目のマスク形成工程）。
【０２０７】
続いて、ボロンイオン（第二導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第二導電型不純物導入工程）。 その結果、低濃度第二導電型のソース・ドレイン領域３１、３２は、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２、及び不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。この様にして第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク２０３を除去する。
【０２０８】
次に、図１０（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０に加えて、ゲート電極１５、２５をも広めに覆うレジストマスク２０４を形成する（４回目のマスク形成工程）。
【０２０９】
続いて、リンイオン（第一導電型不純物）を１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０２１０】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２は、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２、及び不純物濃度が約９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク２０４を除去する。
【０２１１】
その結果、レジストマスク２０１〜２０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０２１２】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１０（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｃを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有るなど、実施例３と同様な効果を奏する。
【０２１３】
又図１０（ｃ）に示す様に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程に於いて、このとき打ち込むボロンイオンを第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域にも打ち込んで居る。即ち低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を援用して、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の不純物濃度を変えて居る。この為、実施例３に比較して工程数を増やす事なく、保持容量４０の下層側電極部４０ｃよりも低濃度化した低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成出来る。それ故、少ない工程数で、各ＴＦＴの電気的特性をさらに向上する事が出来る。
【０２１４】
尚実施例３と同様、表２乃至表４に示す様に、図１０（ｃ）に示す低濃度第二導電型不純物導入工程、図１０（ｄ）に示す高濃度第二導電型不純物導入工程、及び図１０（ｅ）に示す高濃度第一導電型不純物導入工程の間でその順序を入れ換えるなど、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｃを形成するのであれば、いずれの工程順序であってもよい。
【０２１５】
［実施例５］
図１０（ｃ）に於いて、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を援用して、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内の一方だけの不純物濃度を変えてもよい。
【０２１６】
例えば、本例では、実施例３、４に係る製造方法と同じ工程数で製造しながら、図７に示す第一導電型の画素用ＴＦＴ１０の低濃度ソース・ドレイン領域１１１、１２１の不純物濃度を第一導電型の駆動回路用ＴＦＴの低濃度ソース・ドレイン領域２１１、２２１よりも低濃度化して居る。即ち本例のアクティブマトリクス基板１に於いて、保持容量４０の下層側電極部４０ｃ、及び第一導電型の駆動回路用ＴＦＴの低濃度ソース・ドレイン領域２１１、２２１は、実施例３と同様、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第一導電型領域で有るが、第一導電型の画素用ＴＦＴの低濃度ソース・ドレイン領域１１１、１２１は、保持容量４０の下層側電極部４０ｃと同等量のリンイオン（不純物濃度で約１×１０¹⁹ｃｍ^-3のリンイオン）とともに、第二導電型の駆動回路用ＴＦＴ３０の低濃度領域３１１、３２１と同等量のボロンイオン（不純物濃度で約１．１×１０¹⁸ｃｍ^-3のボロンイオン）が導入された低濃度第第一導電型領域で有る。従って、低濃度ソース・ドレイン領域１１１、１２１の不純物濃度は、約９×１０¹⁸ｃｍ^-3で有る。
【０２１７】
斯様な構成のアクティブマトリクス基板１を製造するにあたって、本例では、以下の製造方法を用いて居る。
【０２１８】
まず、図１１（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４及び、誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０２１９】
しかる後に、１×１０¹²ｃｍ^-2のドーズ量でボロンイオンを打ち込んでチャネルドープを行なう（１回目の不純物導入工程）。
【０２２０】
次に、図１１（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０のゲート電極１５、２５の形成領域を広めに覆うレジストマスク３０１を形成する（１回目のマスク形成工程）。
【０２２１】
続いて、リンイオンを約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入し（２回目の不純物導入工程／低濃度第一導電型不純物導入工程）、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２、および下層側電極部４０ｃを形成する。
【０２２２】
次に、図１１（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する。この様にして保持容量４０を形成する。
【０２２３】
以上の各工程は、実施例３、４に係る製造方法と同じで有る。
【０２２４】
次に、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うとともに、レジストマスク３０１と同様、ゲート電極１５をもわずか広めに覆うレジストマスク３０２を形成する（２回目のマスク形成工程）。
【０２２５】
続いて、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０２２６】
その結果、シリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。又低濃度第一導電型のソース・ドレイン領域１１、１２は、そこに打ち込まれたボロンイオンによって実質的に低濃度化し、低濃度第一導電型のソース・ドレイン領域１１、１２の不純物濃度は、約９×１０¹⁸ｃｍ^-3となる。しかる後に、レジストマスク３０２を除去する。
【０２２７】
以降は、実施例３と同様、図１１（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０の形成領域、第一導電型の駆動回路用ＴＦＴ２０の形成領域、及び保持容量４０を覆うと共に、ゲート電極３５を広めに覆うレジストマスク３０３を形成する（３回目のマスク形成工程）。
【０２２８】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０２２９】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２は、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２、及び不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク３０３を除去する。
【０２３０】
次に、図１１（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０に加えて、ゲート電極１５、２５をも広めに覆うレジストマスク３０４を形成する（４回目のマスク形成工程）。
【０２３１】
続いて、リンイオン（第一導電型不純物）を１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０２３２】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２は、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２、不純物濃度が約９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、及び不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度ソース・ドレイン領域２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ１０および第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク３０４を除去する。
【０２３３】
従って、レジストマスク３０１〜３０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０２３４】
この様に、本例のアクティブマトリクス基板１の製造方法では実施例３、４と同様な効果を奏するのに加えて、図１１（ｃ）に示した様に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を援用して低濃度第一導電型のソース・ドレイン領域１１、１２の不純物濃度を変えて居る。この為、実施例３、４に比較して工程数を増やす事なく、保持容量４０の下層側電極部４０ｃ、及び低濃度ソース・ドレイン領域２１１、２２１よりも低濃度化した低濃度ソース・ドレイン領域１１１、１２１を形成出来る。それ故、第一導電型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域２１１、２２１、及び下層側電極部４０ｃの不純物濃度をそのままにして画素用ＴＦＴ１０の低濃度ソース・ドレイン領域１１１、１２１を低濃度化し、駆動回路に於ける動作速度を犠牲にする事なく、画素用ＴＦＴ１０のオフリーク電流をさらに低減するなど、少ない工程数で、各ＴＦＴの電気的特性を領域毎に最適化する事が出来る。
【０２３５】
尚図１１（ｃ）に示す低濃度第二導電型不純物導入工程、図１１（ｄ）に示す高濃度第二導電型不純物導入工程、及び図１１（ｅ）に示す高濃度第一導電型不純物導入工程の間では、順序を入れ換えてもよい事は勿論で有る。
【０２３６】
［実施例６］
図１２は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図で有る。
【０２３７】
図１２に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板１では、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０′のチャネル領域１３、２３、３３は、低濃度のボロンイオンによってチャネルドープしてある為、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域で有る。従って、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０′のスレッショルド電圧を所定の値に設定して有る。
【０２３８】
この様に構成したアクティブマトリクス基板１に於いて、ソース・ドレイン領域１１、１２、２１、２２は、ゲート電極１５、２５の端部に対してゲート絶縁膜１４、２４を介して対峙する部分に低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を備えており、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０は、ＬＤＤ構造になって居る。
【０２３９】
これに対して、第二導電型の駆動回路用ＴＦＴ３０′は、オフセットゲート構造を有しており、ソース・ドレイン領域３１、３２に於いて、ゲート電極３５の端部に対してゲート絶縁膜３４を介して対峙する部分はオフセット領域３１１′、３２１′で有る。このオフセット領域３１１′、３２１′は、チャネル領域３３と同じく、不純物濃度が約１×１０¹⁷ｃｍ−３の低濃度第二導電型領域で有る。
【０２４０】
又保持容量４０に於いて、その下層側電極部４０ｃは、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１と同時形成された低濃度第一導電型領域で有る。
【０２４１】
尚第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０のソース領域１１、２１、及びドレイン領域１２、２２の内、低濃度ソース領域１１１、２１１、及び低濃度ドレイン領域１２１、２２１を除く領域は、不純物濃度が約１×１０２０ｃｍ−３の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２で有る。これらの高濃度領域に対して、各ＴＦＴに対する信号線や画素電極などのソース・ドレイン電極１６、１７、２６、２７が、層間絶縁膜４のコンタクトホールを介して電気的に接続して居る。又第二導電型の駆動回路用ＴＦＴ３０′のソース・ドレイン領域３１、３２では、オフセット領域３１１′、３２１′に隣接する不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２に対して、信号線などのソース・ドレイン電極３６、３７が層間絶縁膜４のコンタクトホールを介して電気的に接続して居る。
【０２４２】
（ＴＦＴのオン・オフリーク電流特性）
この様に構成したアクティブマトリクス基板１に於いて、オフセットゲート構造のＴＦＴはＬＤＤ構造のＴＦＴと同等のオン・オフリーク電流特性を有するので、いずれのＴＦＴもオフリーク電流が著しく小さい。又オフセットゲート構造のＴＦＴは、耐電圧特性に於いてもＬＤＤ構造のＴＦＴと同等の特性を示す。従って、いずれのＴＦＴもセルフアライン構造のＴＦＴに比較して耐電圧が高いので、チャネル長を短くする事が出来る。
【０２４３】
（ＴＦＴの製造方法）
斯様な構造のアクティブマトリクス基板１は、以下の方法により製造出来る。
【０２４４】
まず、実施例３と同様、図１３（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０２４５】
次に、１×１０¹²ｃｍ^-2のドーズ量でボロンイオンを打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０２４６】
次に、図１３（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′の形成領域を覆うと共に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０のゲート電極１５、２５の形成領域をわずか広めに覆うレジストマスク４０１を形成する（１回目のマスク形成工程）。
【０２４７】
続いて、リンイオンを約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入し（２回目の不純物導入工程／低濃度第一導電型不純物導入工程）、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２、および下層側電極部４０ｃを形成する。
【０２４８】
次に、図１３（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する。この様にして保持容量４０を形成する。
【０２４９】
次に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５をも広めに覆うレジストマスク４０２を形成する（２回目のマスク形成工程）。
【０２５０】
この状態で、ボロンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（高濃度第二導電型不純物導入工程／３回目の不純物導入工程）。
【０２５１】
その結果、低濃度第二導電型のシリコン膜３０ａには、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。一方、低濃度第二導電型のシリコン膜３０ａの内、レジストマスク４０２で覆われていた部分はそのまま不純物濃度が約１×１０¹⁷ｃｍ^-3のオフセット領域３１１′、３２１′となる。勿論、チャネル領域３３は不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域のままで有る。
【０２５２】
この様にして、第二導電型の駆動回路用ＴＦＴ３０′を形成する。しかる後に、レジストマスク４０２を除去する。
【０２５３】
次に、図１３（ｄ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′の形成領域に加えて、ゲート電極１５、２５をも広めに覆うレジストマスク４０３を形成する（３回目のマスク形成工程）。
【０２５４】
続いて、リンイオン（第一導電型不純物）を１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０２５５】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２は、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２、及び不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク４０３を除去する。
【０２５６】
従って、レジストマスク４０１〜４０３を形成する為の３回のマスク形成工程と、４回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０２５７】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１３（ｂ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｃを形成して居る。従って、従来の製造方法に比較してマスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０２５８】
更に本例では、図１３（ｃ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′に於いて、ゲート電極３５に対峙する部分を低濃度領域とするにあたって、ＬＤＤ構造ではなく、オフセットゲート構造として居る。この為、実施例３に比較してマスク形成工程及び不純物導入工程のいずれについても１回ずつ少ない。即ち従来の製造方法に比較してマスク形成工程及び不純物導入工程のいずれについても２回ずつ少ない。それ故、最も少ない製造工程数によって、画素領域及び駆動回路部のＴＦＴの電気的特性を向上する事が出来る。
【０２５９】
尚表５及び表６に於いて、チャネルドープ工程を「Ｃ／Ｄ」、低濃度第１導電型不純物導入工程を「Ｎ^- 」、高濃度第一導電型不純物導入工程を「Ｎ⁺ 」、高濃度第二導電型不純物導入工程を「Ｐ⁺ 」、ゲート電極形成工程を「Ｇ」で略しながら工程順序を示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｃを形成するのであれば、いずれの工程順序であってもよい。
【０２６０】
【表５】

【０２６１】
【表６】

【０２６２】
［実施例７］
図１４は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図で有る。
【０２６３】
図１４に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板１では、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０は、いずれもＬＤＤ構造を有し、いずれのＴＦＴに於いても、チャネル領域１３、２３、３３は、低濃度のボロンイオンによってチャネルドープしてある為、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域で有る。
【０２６４】
本例では、保持容量４０の下層側電極部４０ｄ（第一の電極部）は、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２と同時形成された不純物濃度が１×１０²⁰ｃｍ^-3の高濃度第一導電型領域で有る。
【０２６５】
斯様な構造のアクティブマトリクス基板１は、例えば以下の方法により製造出来る。
【０２６６】
まず、図１５（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０２６７】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んでチャネルドープを行ない（チャネルドープ工程／１回目の不純物導入工程）。
【０２６８】
次に、図１５（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、後に形成するゲート電極１５、２５の形成予定領域を広めに覆うレジストマスク５０１を形成する（１回目のマスク形成工程）。
【０２６９】
続いて、例えば、リンイオン（第一導電型不純物／第一導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０２７０】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａの内、リンイオンが打ち込まれた領域は、導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２となる。又低濃度第二導電型のシリコン膜４０ａも導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第一導電型の下層側電極部４０ｄとなる。しかる後に、レジストマスク５０１を除去する。
【０２７１】
次に、図１５（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５（第二の電極部）を形成する（ゲート電極形成工程）。この様にして、下層側電極部４０ｄと上層側電極部４５とが誘電体膜４４を介して対向する保持容量４０を形成する。
【０２７２】
次に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うレジストマスク５０２を形成する（２回目のマスク形成工程）。
【０２７３】
続いて、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０２７４】
その結果、低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。しかる後に、レジストマスク５０２を除去する。
【０２７５】
次に、図１５（ｄ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うレジストマスク５０３を形成する（３回目のマスク形成工程）。
【０２７６】
続いて、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０２７７】
その結果、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２に挟まれた低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域２１１、２２１が形成される。尚不純物が導入されなかった部分がチャネル領域２３、３３となる。この様にして、第一導電型の画素用ＴＦＴ１０、および第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク５０３を除去する。
【０２７８】
次に、図１５（ｅ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５を広めに覆うレジストマスク５０４を形成する（４回目のマスク形成工程）。ここで、レジストマスク５０４の端部とゲート電極３５の端部との距離は、０．５μｍ〜２μｍ程度が適して居る。
【０２７９】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０２８０】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク５０４で覆われていた部分はそのまま不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０２８１】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク５０４を除去する。
【０２８２】
以降、図１４に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク５０１〜５０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０２８３】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１５（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｄを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有る。それ故、少ない製造工程数によってＴＦＴと容量素子（保持容量４０）を形成しながら、各ＴＦＴの電気的特性を向上する事が出来る。
【０２８４】
尚表７に於いて、チャネルドープ工程を「Ｃ／Ｄ」、低濃度第一導電型不純物導入工程を「Ｎ^- 」、高濃度第一導電型不純物導入工程を「Ｎ⁺ 」、低濃度第二導電型不純物導入工程を「Ｐ^- 」、高濃度第二導電型不純物導入工程を「Ｐ⁺ 」、ゲート電極形成工程を「Ｇ」で略して工程順序を示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｄを形成するのであれば、いずれの工程順序であってもよい。
【０２８５】
【表７】

【０２８６】
［実施例８］
本例のアクティブマトリクス基板の構造については実施例７と同じく図１４を参照して説明する。
【０２８７】
図１４に於いて、本例のアクティブマトリクス基板１の特徴点は、実施例７に係る製造方法に比してマスク形成工程が１回少ない点にあり、その製造方法は以下に説明するとおりで有る。
【０２８８】
まず、図１６（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０２８９】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０２９０】
次に、図１６（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、後に形成するゲート電極１５、２５の形成予定領域を広めに覆うレジストマスク６０１を形成する（１回目のマスク形成工程）。
【０２９１】
続いて、例えばリンイオン（第一導電型不純物／第一導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０２９２】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａの内、リンイオンが打ち込まれた領域は、導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２となる。又低濃度第二導電型のシリコン膜４０ａも、導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第一導電型の下層側電極部４０ｄとなる。しかる後に、レジストマスク６０１を除去する。
【０２９３】
次に、図１６（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０２９４】
次に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うレジストマスク６０２を形成する（２回目のマスク形成工程）。
【０２９５】
続いて、ボロンイオンを約３×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０２９６】
その結果、低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約３．１×１０¹⁸ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。しかる後に、レジストマスク６０２を除去する。
【０２９７】
次に、図１６（ｄ）に示す様に、レジストマスクを形成する事なく、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０２９８】
その結果、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２に挟まれた低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１が形成される。尚不純物が導入されなかった部分がチャネル領域２３、３３となる。この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。
【０２９９】
ここで、低濃度第二導電型のソース・ドレイン領域３１、３２にも、リンイオンが１×１０¹³ｃｍ^-2のドーズ量でイオン注入されるが、この低濃度第二導電型のソース・ドレイン領域３１、３２の不純物濃度は、約３．１×１０¹⁸ｃｍ^-3で有る。従って、低濃度第二導電型のソース・ドレイン領域３１、３２は、実質的にアクセプター型不純物濃度が約２．１×１０¹⁸ｃｍ^-3に低濃度化するだけで有り、導電型は反転しない。
【０３００】
次に、図１６（ｅ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５を広めに覆うレジストマスク６０３を形成する（３回目のマスク形成工程）。
【０３０１】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０３０２】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク６０３で覆われていた部分はそのまま不純物濃度が約２．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０３０３】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク６０３を除去する。
【０３０４】
以降、図１４に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク６０１〜６０３を形成する為の３回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０３０５】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１６（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｄを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０３０６】
しかも、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の工程では、マスクを形成せずに、リンイオンの注入を行う。それ故、３回のマスク形成工程と５回の不純物導入工程によって、各ＴＦＴ及び保持容量４０を製造する事が出来る。
【０３０７】
尚実施例７と同様、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｄを形成するのであれば、表７に示すいずれの工程順序であってもよい。
【０３０８】
［実施例９］
本例のアクティブマトリクス基板の構造については、実施例７と同じく図１４を参照して説明する。本例の特徴点は、実施例８と同様、実施例７に係る製造方法に比してマスク形成工程が１回少ない点にあり、その製造方法は、以下に説明するとおりで有る。
【０３０９】
まず、図１７（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程。）
次に、約１×１０１２ｃｍ−２のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０３１０】
次に、図１７（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０の形成領域を覆うと共に、後に形成するゲート電極１５、２５の形成予定領域を広めに覆うレジストマスク７０１を形成する（１回目のマスク形成工程）。
【０３１１】
続いて、例えば、リンイオン（第一導電型不純物／第一導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０３１２】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａの内、リンイオンが打ち込まれた領域は、導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２となる。又低濃度第二導電型のシリコン膜４０ａも、導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第一導電型の下層側電極部４０ｄとなる。しかる後に、レジストマスク７０１を除去する。
【０３１３】
次に、図１７（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０３１４】
次に、ｐ型の駆動回路用ＴＦＴ３０の形成領域を覆うレジストマスク７０２を形成する（２回目のマスク形成工程）。
【０３１５】
続いて、リンイオンを約３×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０３１６】
その結果、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２に挟まれた低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約２．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１が形成される。尚不純物が導入されなかった部分がチャネル領域２３、３３となる。この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。
【０３１７】
次に、図１７（ｄ）に示す様に、レジストマスク７０２を除去し、そのままレジストマスクを形成する事なく、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０３１８】
その結果、低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ｐ型領域３１，３２が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。
【０３１９】
ここで、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の側にも、ボロンイオンが１×１０¹³ｃｍ^-2のドーズ量でイオン注入されるが、その低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１の不純物濃度は、約２．９×１０¹⁸ｃｍ^-3で有る。従って、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１は、実質的にドナー型不純物濃度が約１．９×１０¹⁸ｃｍ^-3に低濃度化するだけで有り、導電型は反転しない。又高濃度ドース・ドレイン領域１１２、１２２、２１２、２２２も、わずかに低濃度化するだけで有り、導電型は反転せず、いぜんとして高濃度で有る。
【０３２０】
次に、図１７（ｅ）に示す様に、第一導電型の画素用ＴＦＴ１０の形成領域、第一導電型の駆動回路用ＴＦＴ２０の形成領域、及び保持容量４０を覆うと共に、ゲート電極３５を広めに覆うレジストマスク７０３を形成する（３回目のマスク形成工程）。
【０３２１】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０３２２】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク７０３で覆われていた部分は、そのまま不純物濃度が約２．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０３２３】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク７０３を除去する。
【０３２４】
以降、図１４に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク７０１〜７０３を形成する為の３回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０３２５】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１７（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｄを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０３２６】
しかも、低濃度ソース・ドレイン領域３１１、３２１を形成する為の工程では、マスクを形成せずに、ボロンイオンの注入を行う。それ故、３回のマスク形成工程と５回の不純物導入工程によって、各ＴＦＴ及び保持容量４０を製造する事が出来る。
【０３２７】
尚実施例７と同様、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｄを形成するのであれば、表７に示すいずれの工程順序であってもよい。
【０３２８】
［実施例１０］
図１８は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図で有る。
【０３２９】
図１８に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板１では、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０は、ＬＤＤ構造になって居る。これに対して、第二導電型の駆動回路用ＴＦＴ３０′は、オフセットゲート構造を有して居る。
【０３３０】
本例では、保持容量４０２の下層側電極部４０ｄは、第一導電型の駆動回路用ＴＦＴ２０、及び第一導電型の画素用ＴＦＴ１０の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２と同時形成された不純物濃度が１×１０²⁰ｃｍ^-3の高濃度の第一導電型領域で有る。
【０３３１】
斯様な構造のアクティブマトリクス基板１は、以下の方法により製造出来る。
【０３３２】
まず、図１９（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０３３３】
しかる後に、１×１０¹²ｃｍ^-2のドーズ量でボロンイオンを打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０３３４】
次に、図１９（ｂ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′の形成領域を覆うと共に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０のゲート電極１５、２５の形成予定領域を広めに覆うレジストマスク８０１を形成する（１回目のマスク形成工程）。
【０３３５】
続いて、第一導電型不純物、例えばリンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０３３６】
その結果、シリコン膜１０ａ、２０ａの内、リンイオンが打ち込まれた領域は導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１１、２２１となる。又シリコン膜４０ａは導電型が反転して不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第一導電型の下層側電極部４０ｄとなる。しかる後に、レジストマスク８０１を除去する。
【０３３７】
次に、図１９（ｃ）に示す様に、ゲート絶縁膜１４、２４、３４の表面にドープドシリコンやシリサイド膜などからなるゲート電極１５、２５、３５を形成する（ゲート電極形成工程）。同時に、誘電体膜４４の表面には、上層側電極部４５を形成する。この上層側電極部４５は、前段の信号線の一部であってもよい。この様にして、下層側電極部４０ｃと上層側電極部４５とが誘電体膜４４を介して対向する保持容量４０を形成する。
【０３３８】
次に、第二導電型の駆動回路用ＴＦＴ３０を覆うレジストマスク８０２を形成する（２回目のマスク形成工程）。
【０３３９】
この状態で、リンイオンを１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（低濃度第一導電型不純物導入工程／３回目の不純物導入工程）。
【０３４０】
その結果、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２に挟まれた低濃度第二導電型のシリコン膜２０ａ、３０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ−３の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１が形成される。尚不純物が導入されなかった部分がチャネル領域２３、３３となる。この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。
【０３４１】
次に、図１９（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５を広めに覆うレジストマスク８０３を形成する（３回目のマスク形成工程）。
【０３４２】
この状態で、ボロンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（高濃度第二導電型不純物導入工程／４回目の不純物導入工程）。
【０３４３】
その結果、低濃度第二導電型のシリコン膜３０ａには、不純物濃度が１×１０２０ｃｍ−３の高濃度ソース・ドレイン領域３１２、３２２が形成される。一方、低濃度第二導電型のシリコン膜３０ａの内、レジストマスク８０３で覆われていた部分は、そのまま不純物濃度が約１×１０¹⁷ｃｍ^-3のオフセット領域３１１′、３２１′と成る。チャンネル領域３３は、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域のままで有る。
【０３４４】
この様にして、第二導電型の駆動回路用ＴＦＴ３０′を形成する。しかる後に、レジストマスク８０３を除去する。
【０３４５】
従って、レジストマスク８０１〜８０３を形成する為の３回のマスク形成工程と、４回の不純物導入工程によって、アクティブマトリクス基板１を製造出来る。
【０３４６】
この様に、本例のアクティブマトリクス基板１の製造方法では、図１９（ｂ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の高濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｄを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０３４７】
更に本例では、図１９（ｃ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′に於いて、ゲート電極３５の端部に対峙する部分を低濃度領域とするにあたって、ＬＤＤ構造ではなく、オフセットゲート構造として居る。この為、実施例３に比較して、マスク形成工程及び不純物導入工程のいずれについても１回ずつ少ない。即ち従来の製造方法に比較して、マスク形成工程及び不純物導入工程のいずれについても２回ずつ少ない。それ故、最も少ない製造工程数によって、画素領域及び駆動回路部のＴＦＴの電気的特性を向上する事が出来る。
【０３４８】
尚表８に於いて、チャネルドープ工程を「Ｃ／Ｄ」、低濃度第一導電型不純物導入工程を「Ｎ− 」、高濃度第一導電型不純物導入工程を「Ｎ⁺ 」、高濃度第二導電型不純物導入工程を「Ｐ⁺ 」、ゲート電極形成工程を「Ｇ」で略しながら工程順序を示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｄを形成するのであれば、いずれの工程順序であってもよい。
【０３４９】
【表８】

【０３５０】
［実施例１１］
図２０に示す様に、本例のアクティブマトリクス基板１では、第二導電型の駆動回路用ＴＦＴ３０、第一導電型の駆動回路用ＴＦＴ２０、及び第一導電型の画素用ＴＦＴ１０は、いずれもＬＤＤ構造になって居る。
【０３５１】
又本例のアクティブマトリクス基板１では、保持容量４０の下層側電極部４０ｅ（第一の電極部）は、第二導電型の駆動回路用ＴＦＴ３０の低濃度ソース・ドレイン領域３１１、３１２と同時形成された不純物濃度が１×１０¹⁹ｃｍ^-3の低濃度第二導電型領域で有る。
【０３５２】
斯様な構造のアクティブマトリクス基板１は、例えば、以下の方法により製造出来る。
【０３５３】
まず、図２１（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０３５４】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０３５５】
次に、図２１（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、後に形成するゲート電極３５の形成領域をわずか広めに覆うレジストマスク９０１を形成する（１回目のマスク形成工程）。
【０３５６】
続いて、例えば、ボロンリンイオン（第二導電型不純物／第二導電型不純物）を約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０３５７】
その結果、低濃度第二導電型のシリコン膜３０ａには、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。又低濃度第二導電型のシリコン膜４０ａは、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第二導電型の下層側電極部４０ｅとなる。しかる後に、レジストマスク９０１を除去する。
【０３５８】
次に、図２１（ｃ）に示す様に、ゲート絶縁膜１４、２４、３４の表面に、ドープドシリコンやシリサイド膜などからなるゲート電極１５、２５、３５を形成する。同時に、誘電体膜４４の表面には、上層側電極部４５（第二の電極部）を形成する（ゲート電極形成工程）。この上層側電極部４５は、前段の信号線の一部であってもよい。この様にして、下層側電極部４０ｅと上層側電極部４５とが誘電体膜４４を介して対向する保持容量４０を形成する。
【０３５９】
次に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うレジストマスク９０２を形成する（２回目のマスク形成工程）。
【０３６０】
続いて、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０３６１】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。しかる後に、レジストマスク９０２を除去する。
【０３６２】
次に、図２１（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５を広めに覆うレジストマスク９０３を形成する（３回目のマスク形成工程）。
【０３６３】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０３６４】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク１０３で覆われていた部分は、そのまま不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０３６５】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク９０３を除去する。
【０３６６】
次に、図２１（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０を覆うとともに、ゲート電極１５、２５を広めに覆うレジストマスク９０４を形成する（４回目のマスク形成工程）。
【０３６７】
続いて、リンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０３６８】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２が形成される。又低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク９０４で覆われていた部分は、そのまま不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。
【０３６９】
この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク９０４を除去する。
【０３７０】
以降、図２０に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク９０１〜９０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０３７１】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２１（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｅを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有る。それ故、少ない製造工程数によって、ＴＦＴと容量素子（保持容量４０）を形成しながら、画素領域および駆動回路部の各ＴＦＴの電気的特性を向上する事が出来る。
【０３７２】
尚本例の製造方法は、表２乃至表４に示した実施例３に係る製造方法に於いて、「Ｎ^- 」で示す低濃度第一導電型不純物導入工程と、「Ｐ^- 」で示す低濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｅを形成するのであれば、６０通りの工程順序の内、いずれの工程順序であってもよい。
【０３７３】
［実施例１２〕
本例のアクティブマトリクス基板１の特徴点は、実施例１１に係る製造方法と同じ工程数で製造しながら、第二導電型の駆動回路用ＴＦＴ３０の低濃度ソース・ドレイン領域３１１、３２１を保持容量４０の下層側電極部４０ｅよりも低濃度化した点に有る。
【０３７４】
即ち図２０に於いて、保持容量４０の下層側電極部４０ｅは、実施例１１と同様、第二導電型の駆動回路用ＴＦＴ３０の低濃度ソース・ドレイン領域３１１、３２１と同時に形成されたもので有るが、下層側電極部４０ｅの不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第二導電型領域で有るのに対し、第二導電型の駆動回路用ＴＦＴ３０の低濃度ソース・ドレイン領域３１１、３２１は不純物濃度が約９×１０¹⁸ｃｍ^-3で有る。
【０３７５】
尚本例のアクティブマトリクス基板１では、第二導電型の駆動回路用ＴＦＴ３０、第一導電型の駆動回路用ＴＦＴ２０、第一導電型の画素用ＴＦＴ１０のいずれもが、ゲート電極１５、２５、３５の端部に対してゲート絶縁膜１４、２４、３４を介して対峙する部分に低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１、３１１、３２１を備えるＬＤＤ構造になって居る。
【０３７６】
斯様な構造のアクティブマトリクス基板１は、例えば以下の方法により製造出来る。尚以下の説明に於いて、不純物濃度はいずれも活性化アニール後の不純物濃度で表して有る。
【０３７７】
まず、図２２（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０３７８】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んでチャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０３７９】
次に、図２２（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、後に形成する第二導電型の駆動回路用ＴＦＴ３０のゲート電極３５の形成予定領域をわずか広めに覆うレジストマスク１１０１を形成する（１回目のマスク形成工程）。
【０３８０】
続いて、例えば、ボロンイオン（第二導電型不純物／第二導電型不純物）を約１×１０¹⁴ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／低濃度第２導電型不純物導入工程）。
【０３８１】
その結果、低濃度第二導電型のシリコン膜３０ａには、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第二導電型のソース・ドレイン領域３１、３２が形成される。又低濃度第二導電型のシリコン膜４０ａは、不純物濃度が約１×１０¹⁹ｃｍ^-3の低濃度第二導電型の下層側電極部４０ｅとなる。しかる後にレジストマスク１１０１を除去する。
【０３８２】
次に、図２２（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０３８３】
次に、保持容量４０の形成領域を覆うレジストマスク１１０２を形成する（２回目のマスク形成工程）。
【０３８４】
続いて、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０３８５】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。
【０３８６】
ここで、低濃度第二導電型のシリコン膜３１、３２にも、リンイオンが約１×１０¹³ｃｍ^-2のドーズ量でイオン注入されるが、低濃度第二導電型のシリコン膜３１、３２の不純物濃度は、約１×１０¹⁹ｃｍ^-3で有る。従って、低濃度第二導電型のシリコン膜３１、３２は、実質的にアクセプター型不純物濃度が約９×１０¹⁸ｃｍ^-3にまで低濃度化するが、導電型は反転しない。
【０３８７】
しかる後に、レジストマスク１１０２を除去する。
【０３８８】
次に、図２２（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うと共に、ゲート電極３５を広めに覆うレジストマスク１１０３を形成する（３回目のマスク形成工程）。
【０３８９】
続いて、ボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０３９０】
その結果、低濃度第二導電型のソース・ドレイン領域３１、３２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。又低濃度第二導電型のソース・ドレイン領域３１、３２の内、レジストマスク１１０３で覆われていた部分は、そのまま不純物濃度が約９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１となる。
【０３９１】
この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク１１０３を除去する。
【０３９２】
次に、図２２（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０及び保持容量４０の形成領域を覆うと共に、ゲート電極１５、２５を広めに覆うレジストマスク１１０４を形成する（４回目のマスク形成工程）。
【０３９３】
続いて、リンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０３９４】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２２２、２２２が形成される。又低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１１０４で覆われていた部分は、そのまま不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。
【０３９５】
この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１１０４を除去する。
【０３９６】
以降、図２０に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク１１０１〜１１０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０３９７】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２２（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第一導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｅを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有るなど、実施例１２と同様な効果を奏する。
【０３９８】
又図２２（ｃ）に示した様に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の低濃度第一導電型不純物導入工程において、このとき打ち込むリンイオンを第二導電型の駆動回路用ＴＦＴ３０の形成領域にも打ち込んで居る。即ち低濃度第一導電型不純物導入工程を援用して、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型のソース・ドレイン領域３１、３２の不純物濃度を変えて居る。この為、実施例１１に比較して工程数を増やす事なく、保持容量４０の下層側電極部４０ｅよりも低濃度化した低濃度ソース・ドレイン領域３１１、３２１を形成出来る。
【０３９９】
尚本例の製造方法は、実施例４に係る製造方法に於いて、低濃度第一導電型不純物導入工程と、低濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の低濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｅを形成するのであれば、表２乃至表４に示す６０通りの工程順序の内、「Ｎ^- 」で示す低濃度第一導電型不純物導入工程と、「Ｐ^- 」で示す低濃度第二導電型不純物導入工程とを入れ換えたいずれの工程順序であってもよい。
【０４００】
［実施例１３］
図２３は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図で有る。尚本例のアクティブマトリクス基板では、各ＴＦＴの基本的な構造が図７に示したアクティブマトリクス基板と略同じで有る。
【０４０１】
図２３に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板１では、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び第二導電型の駆動回路用ＴＦＴ３０は、いずれもＬＤＤ構造を有し、いずれのＴＦＴに於いても、チャネル領域１３、２３、３３は、低濃度のボロンイオンによってチャネルドープしてある為、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域で有る。
【０４０２】
本例では、保持容量４０２の下層側電極部４０ｆ（第一の電極部）は、第二導電型の駆動回路用ＴＦＴ３０の高濃度ソース・ドレイン領域３１１、３１２と同時形成された不純物濃度が１×１０²⁰ｃｍ^-3の高濃度第二導電型領域で有る。
【０４０３】
斯様な構造のアクティブマトリクス基板１は、例えば、以下の方法により製造出来る。
【０４０４】
まず、図２４（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、誘電体膜４４を同時に形成する（ゲート絶縁膜形成工程）。
【０４０５】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０４０６】
次に、図２４（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、後に形成する第二導電型の駆動回路用ＴＦＴ３０のゲート電極３５の形成予定領域をわずか広めに覆うレジストマスク１２０１を形成する（１回目のマスク形成工程）。
【０４０７】
続いて、例えば、ボロンイオン（第二導電型不純物／第二導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第２導電型不純物導入工程）。
【０４０８】
その結果、低濃度第二導電型のシリコン膜３０ａの内、高濃度のボロンイオンが打ち込まれた領域は、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２となる。又低濃度第二導電型のシリコン膜４０ａも、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第二導電型の下層側電極部４０ｆとなる。しかる後に、レジストマスク１２０１を除去する。
【０４０９】
次に、図２４（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５（第二の電極部）を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０４１０】
次に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うレジストマスク１２０２を形成する（２回目のマスク形成工程）。
【０４１１】
続いて、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０４１２】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。しかる後に、レジストマスク１２０２を除去する。
【０４１３】
次に、図２４（ｄ）に示す様に、第一導電型の画素用ＴＦＴ１０、第一導電型の駆動回路用ＴＦＴ２０、及び保持容量４０の形成領域を覆うレジストマスク１２０３を形成する（３回目のマスク形成工程）。
【０４１４】
続いて、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０４１５】
その結果、高濃度ソース・ドレイン領域３１２、３２２に挟まれた低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク１２０３を除去する。
【０４１６】
次に、図２４（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うと共に、ゲート電極１５、２５を広めに覆うレジストマスク１２０４を形成する（４回目のマスク形成工程）。
【０４１７】
続いて、リンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０４１８】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２が形成される。又低濃度第二導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１２０４で覆われていた部分は、そのまま不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１２０４を除去する。
【０４１９】
以降、図２３に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク１２０１〜１２０４を形成する為の４回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０４２０】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２４（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｆを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を１回ずつ減らす事が可能で有る。それ故、少ない製造工程数によって、ＴＦＴと容量素子（保持容量４０）を形成しながら、各ＴＦＴの電気的特性を向上する事が出来る。
【０４２１】
尚本例の製造方法は、実施例７に係る製造方法に於いて、高濃度第一導電型不純物導入工程と、高濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｆを形成するのであれば、表７に示す２４通りの工程順序の内、「Ｎ⁺ 」で示す高濃度第１導電型不純物導入工程と、「Ｐ⁺ 」で示す高濃度第二導電型不純物導入工程とを入れ換えたいずれの工程順序であってもよい。
【０４２２】
［実施例１４］
本例のアクティブマトリクス基板１の特徴点は、実施例１３に係る製造方法に比してマスク形成工程が１回少ない点にあり、その製造方法は、以下に説明するとおりで有る。
【０４２３】
まず、図２５（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０４２４】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０４２５】
次に、図２５（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、後に形成する第二導電型の駆動回路用ＴＦＴ３０のゲート電極３５の形成予定領域をわずか広めに覆うレジストマスク１３０１を形成する（１回目のマスク形成工程）。
【０４２６】
続いて、例えば、ボロンイオン（第二導電型不純物／第二導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第２導電型不純物導入工程）。
【０４２７】
その結果、低濃度第二導電型のシリコン膜３０ａの内、高濃度のボロンイオンが打ち込まれた領域は、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２となる。又低濃度第二導電型のシリコン膜４０ａも、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第二導電型の下層側電極部４０ｆとなる。しかる後に、レジストマスク１３０１を除去する。
【０４２８】
次に、図２５（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する（ゲート電極形成工程）。この様にして保持容量４０を形成する。
【０４２９】
次に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うレジストマスク１３０２を形成する（２回目のマスク形成工程）。
【０４３０】
続いて、リンイオンを約３×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０４３１】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約２．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。しかる後に、レジストマスク１３０２を除去する。
【０４３２】
次に、図２５（ｄ）に示す様に、マスクを形成する事なく、ボロンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０４３３】
その結果、高濃度ソース・ドレイン領域３１２、３２２に挟まれた低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約１．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。
【０４３４】
一方、低濃度第一導電型のシリコン膜１１、１２、２１、２２にも、ボロンイオンが約１×１０¹³ｃｍ^-2のドーズ量でイオン注入されるが、低濃度第一導電型のシリコン膜１１、１２、２１、２２の不純物濃度は、約２．９×１０¹⁸ｃｍ^-3で有る。従って、低濃度第一導電型のシリコン膜１１、１２、２１、２２は、実質的にドナー型不純物濃度が約１．９×１０¹⁸ｃｍ^-3にまで低濃度化されるが、導電型は反転しない。
【０４３５】
次に、図２５（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うと共に、ゲート電極１５、２５を広めに覆うレジストマスク１３０３を形成する（３回目のマスク形成工程）。
【０４３６】
続いて、リンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０４３７】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２が形成される。又低濃度第二導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１２０４で覆われていた部分は、そのまま不純物濃度が約１．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１３０３を除去する。
【０４３８】
以降、図２３に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク１３０１〜１３０３を形成する為の３回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０４３９】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２５（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｆを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０４４０】
しかも、図２５（ｄ）に示す様に、低濃度ソース・ドレイン領域３１１、３２１を形成する為の工程では、マスクを形成せずに、ボロンイオンの注入を行う。それ故、３回のマスク形成工程と５回の不純物導入工程によって、各ＴＦＴ及び保持容量４０を製造する事が出来る。
【０４４１】
尚本例の製造方法は、実施例８に係る製造方法に於いて、高濃度第一導電型不純物導入工程と、高濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｆを形成するのであれば、表７に示す２４通りの工程順序の内、「Ｎ⁺ 」で示す高濃度第１導電型不純物導入工程と、「Ｐ⁺ 」で示す高濃度第二導電型不純物導入工程とを入れ換えたいずれの工程順序であってもよい。
【０４４２】
［実施例１５］
本例のアクティブマトリクス基板及びその製造方法は、基本的な部分が実施例１４と同じで有る。本例の特徴点は、実施例１４と同様、実施例１３に係る製造方法に比してマスク形成工程が１回少ない点にあり、その製造方法は、以下に説明するとおりで有る。
【０４４３】
まず、図２６（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０４４４】
次に、約１×１０¹²ｃｍ^-2のドーズ量でボロンイオン（第二導電型不純物／第二導電型不純物）を打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０４４５】
その結果、シリコン膜１０ａ、２０ａ、３０ａ、４０ａは、不純物濃度が約１×１０１７ｃｍ−３の低濃度第二導電型のシリコン膜１０ａ、２０ａ、３０ａ、４０ａとなる。
【０４４６】
次に、図２６（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、後に形成する第二導電型の駆動回路用ＴＦＴ３０のゲート電極３５の形成予定領域を広めに覆うレジストマスク１４０１を形成する（１回目のマスク形成工程）。
【０４４７】
続いて、例えば、ボロンイオン（第二導電型不純物／第二導電型不純物）を約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第２導電型不純物導入工程）。
【０４４８】
その結果、低濃度第二導電型のシリコン膜３０ａの内、高濃度のボロンイオンが打ち込まれた領域は、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２となる。又低濃度第二導電型のシリコン膜４０ａも、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第二導電型の下層側電極部４０ｆとなる。しかる後に、レジストマスク１４０１を除去する。
【０４４９】
次に、図２６（ｃ）に示す様に、ゲート絶縁膜１４、２４、３４の表面に、ドープドシリコンやシリサイド膜などからなるゲート電極１５、２５、３５を形成する。同時に、誘電体膜４４の表面には、上層側電極部４５を形成する（ゲート電極形成工程）。この上層側電極部４５は、前段の信号線の一部であってもよい。この様にして、下層側電極部４０ｆと上層側電極部４５とが誘電体膜４４を介して対向する保持容量４０を形成する。
【０４５０】
次に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うレジストマスク１４０２を形成する（２回目のマスク形成工程）。
【０４５１】
続いて、ボロンイオンを約３×１０¹³ｃｍ^-2のドーズ量でイオン注入する（３回目の不純物導入工程／低濃度第二導電型不純物導入工程）。
【０４５２】
その結果、高濃度ソース・ドレイン領域３１２、３２２に挟まれた低濃度第二導電型のシリコン膜３０ａには、ゲート電極３５に対して自己整合的に不純物濃度が約３．１×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域３１１、３２１が形成される。尚不純物が導入されなかった部分がチャネル領域３３となる。この様にして、第二導電型の駆動回路用ＴＦＴ３０を形成する。しかる後に、レジストマスク１４０２を除去する。
【０４５３】
次に、図２６（ｄ）に示す様に、マスクを形成する事なく、リンイオンを約１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（４回目の不純物導入工程／低濃度第一導電型不純物導入工程）。
【０４５４】
その結果、低濃度第二導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。
【０４５５】
ここで、低濃度ソース・ドレイン領域３１１、３２１にも、リンイオンが約１×１０１３ｃｍ−２のドーズ量でイオン注入されるが、低濃度ソース・ドレイン領域３１１、３２１の不純物濃度は、約３．１×１０¹⁸ｃｍ^-3で有る。従って、低濃度ソース・ドレイン領域３１１、３２１は、実質的にアクセプター型不純物濃度が約２．１×１０¹⁸ｃｍ^-3にまで低濃度化するが、導電型は反転しない。
【０４５６】
次に、図２６（ｅ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うと共に、ゲート電極１５、２５を広めに覆うレジストマスク１４０３を形成する（３回目のマスク形成工程）。
【０４５７】
続いて、リンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（５回目の不純物導入工程／高濃度第一導電型不純物導入工程）。
【０４５８】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２が形成される。又低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１４０３で覆われていた部分は、そのまま不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ１０、及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１４０３を除去する。
【０４５９】
以降、図２３に示す様に、層間絶縁膜４を形成した後、活性化の為のアニールを行い、しかる後に、コンタクトホールを形成してソース・ドレイン電極１６、１７、２６、２７、３６、３７を形成すれば、レジストマスク１４０１〜１４０３を形成する為の３回のマスク形成工程と、５回の不純物導入工程によって、アクティブマトリクス基板１等の半導体装置を製造出来る。
【０４６０】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２６（ｂ）に示した様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して下層側電極部４０ｆを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０４６１】
しかも、図２６（ｄ）に示す様に、低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１を形成する為の工程では、マスクを形成せずに、リンイオンの注入を行う。それ故、３回のマスク形成工程と５回の不純物導入工程によって、各ＴＦＴ及び保持容量４０を製造する事が出来る。
【０４６２】
尚本例の製造方法は、実施例９に係る製造方法に於いて、高濃度第一導電型不純物導入工程と、高濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｆを形成するのであれば、表７に示す２４通りの工程順序の内、「Ｎ⁺ 」で示す高濃度第１導電型不純物導入工程と、「Ｐ⁺ 」で示す高濃度第二導電型不純物導入工程とを入れ換えたいずれの工程順序であってもよい。
【０４６３】
［実施例１６］
図２７は、本例の液晶表示装置に於ける駆動回路内蔵型のアクティブマトリクス基板の構造を模式的に示す断面図で有る。尚本例のアクティブマトリクス基板では、各ＴＦＴの基本的な構造が図７に示したアクティブマトリクス基板と略同じで有る。
【０４６４】
図２７に於いて、本例の液晶表示装置の駆動回路内蔵型のアクティブマトリクス基板１でも、第一導電型の駆動回路用ＴＦＴ２０、及び第一導電型の画素用ＴＦＴ１０は、いずれもＬＤＤ構造になって居る。
【０４６５】
これに対して、第二導電型の駆動回路用ＴＦＴ３０′は、オフセットゲート構造を有しており、オフセット領域３１１′、３２１′は、チャネル領域３３と同じく、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域で有る。
【０４６６】
本例では、保持容量４０２の下層側電極部４０ｄは、第二導電型の駆動回路用ＴＦＴ３０′の高濃度ソース・ドレイン領域３１２、３２２と同時形成された不純物濃度が１×１０²⁰ｃｍ^-3の高濃度第二導電型領域で有る。
【０４６７】
斯様な構造のアクティブマトリクス基板１は、以下の方法により製造出来る。
【０４６８】
まず、図２８（ａ）に示す様に、絶縁基板２の表面に島状のシリコン膜１０ａ、２０ａ、３０ａ、４０ａを形成した後（シリコン膜形成工程）、ゲート絶縁膜１４、２４、３４、及び誘電体膜４４を形成する（ゲート絶縁膜形成工程）。
【０４６９】
次に、１×１０¹²ｃｍ^-2のドーズ量でボロンイオンを打ち込んで、チャネルドープを行なう（チャネルドープ工程／１回目の不純物導入工程）。
【０４７０】
次に、図２８（ｂ）に示す様に、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０の形成領域を覆うと共に、第二導電型の駆動回路用ＴＦＴ３０′の形成領域の内、後に形成するゲート電極３５の形成予定領域を広めに覆うレジストマスク１５０１を形成する（１回目のマスク形成工程）。
【０４７１】
続いて、第二導電型不純物、例えばボロンイオンを約１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（２回目の不純物導入工程／高濃度第二導電型不純物導入工程）。
【０４７２】
その結果、低濃度第二導電型のシリコン膜３０ａには、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域３１２、３２２が形成される。一方、低濃度第二導電型のシリコン膜３０ａの内、レジストマスク１５０１で覆われていた部分は、そのまま不純物濃度が約１×１０¹⁷ｃｍ^-3のオフセット領域３１１′、３２１′となる。勿論、チャネル領域３３は、不純物濃度が約１×１０¹⁷ｃｍ^-3の低濃度第二導電型領域のままで有る。又シリコン膜４０ａは、不純物濃度が約１×１０²⁰ｃｍ^-3の高濃度第二導電型の下層側電極部４０ｆとなる。しかる後に、レジストマスク１５０１を除去する。
【０４７３】
次に、図２８（ｃ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極部４５を形成する。この様にして保持容量４０を形成する。
【０４７４】
次に、第二導電型の駆動回路用ＴＦＴ３０及び保持容量４０の形成領域を覆うレジストマスク１５０２を形成する（２回目のマスク形成工程）。
【０４７５】
この状態で、リンイオンを１×１０¹³ｃｍ^-2のドーズ量でイオン注入する（低濃度第一導電型不純物導入工程／３回目の不純物導入工程）。
【０４７６】
その結果、低濃度第一導電型のシリコン膜１０ａ、２０ａには、ゲート電極１５、２５に対して自己整合的に不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２が形成される。尚不純物が導入されなかった部分がチャネル領域１３、２３となる。この様にして、第一導電型の画素用ＴＦＴ１０及び第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１５０２を除去する。
【０４７７】
次に、図２８（ｄ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０、及び保持容量４０の形成領域を覆うと共に、ゲート電極１５、２５をも広めに覆うレジストマスク１５０３を形成する（３回目のマスク形成工程）。
【０４７８】
この状態で、リンイオンを１×１０¹⁵ｃｍ^-2のドーズ量でイオン注入する（高濃度第一導電型不純物導入工程／４回目の不純物導入工程）。
【０４７９】
その結果、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２には、不純物濃度が１×１０²⁰ｃｍ^-3の高濃度ソース・ドレイン領域１１２、１２２、２１２、２２２が形成される。一方、低濃度第一導電型のソース・ドレイン領域１１、１２、２１、２２の内、レジストマスク１５０３で覆われていた部分は、そのまま不純物濃度が約０．９×１０¹⁸ｃｍ^-3の低濃度ソース・ドレイン領域１１１、１２１、２１１、２２１となる。この様にして、第一導電型の画素用ＴＦＴ1 ０および第一導電型の駆動回路用ＴＦＴ２０を形成する。しかる後に、レジストマスク１５０３を除去する。
【０４８０】
従って、レジストマスク１５０３〜１５０３を形成する為の３回のマスク形成工程と、４回の不純物導入工程によって、アクティブマトリクス基板１を製造出来る。
【０４８１】
この様に、本例のアクティブマトリクス基板１の製造方法では、図２８（ｂ）に示す様に、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１１、３２１を形成する為の高濃度第２導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｆを形成して居る。従って、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０４８２】
更に本例では、図２８（ｃ）に示す様に、第二導電型の駆動回路用ＴＦＴ３０′に於いて、ゲート電極３５に対峙する部分を低濃度領域とするにあたって、ＬＤＤ構造ではなく、オフセットゲート構造として居る。この為、実施例３に比較して、マスク形成工程及び不純物導入工程のいずれについても１回ずつ少ない。即ち従来の製造方法に比較して、マスク形成工程及び不純物導入工程のいずれについても２回ずつ少ない。それ故、最も少ない製造工程数によって、画素領域及び駆動回路部のＴＦＴの電気的特性を向上する事が出来る。
【０４８３】
尚本例の製造方法は、実施例１０に係る製造方法に於いて、高濃度第一導電型不純物導入工程と、高濃度第二導電型不純物導入工程とを入れ換えた方法に相当するので、ゲート電極１５、２５、３５、及び上層側電極４５を形成する前に、高濃度ソース・ドレイン領域３１２、３２２を形成する為の高濃度第二導電型不純物導入工程を行い、この工程を援用して、下層側電極部４０ｆを形成するのであれば、表８に示す１０通りの工程順序の内、「Ｎ⁺ 」で示す高濃度第一導電型不純物導入工程と、「Ｐ⁺ 」で示す高濃度第二導電型不純物導入工程とを入れ換えたいずれの工程順序であってもよい。
【０４８４】
［実施例３乃至実施例１６の変形例］
尚不純物導入方法としては、例えば、ドーパントガスから発生した全てのイオンを質量分離せずに打ち込む方法、いわゆるイオンドーピング法を用いてもよい。この方法で、例えば、第一導電型の不純物を高濃度に打ち込む場合には、ＰＨ３ を約５％含み、残部が水素ガスからなる混合ガスを用い、この混合ガスから発生する全てのイオンを質量分離せずに打ち込む。これに対して、第一導電型の不純物を低濃度に打ち込む場合には、ＰＨ₃ を約５％含み、残部が水素ガスからなる混合ガスから発生する全てのイオンを質量分離せずに打ち込んだ後、純水素ガスから発生するイオンを質量分離せずに打ち込んで、シリコン膜中の不整結合を終端する事が好ましい。更に不純物の導入方法については、イオン注入法やイオンドーピング法の他にも、プラズマドーピング法、レーザドーピング法などを用いてもよい。更にマスクの材質についてもレジストマスクに限定されない。いずれの形態でも第一導電型をＮ型とし、第二導電型をＰ型としたが、逆にしてもよい。即ち画素用ＴＦＴをＰ型で構成してもよい。
【０４８５】
【発明の効果】
以上説明した様に、本発明に係る半導体装置では、いずれのＴＦＴも、ゲート電極の端部に対峙する部分が低濃度領域で有る為、オフ電流が小さい。又ＴＦＴのソース・ドレイン間に於ける耐電圧が高い為、チャネル長を短く出来るので、高速動作が可能で有る。更に第二導電型の駆動回路用ＴＦＴにおいて、ゲート電極の端部に対峙する低濃度領域は、チャネル領域と同じ不純物濃度をもつオフセット領域として形成して有る。従って、総てのＴＦＴをＬＤＤ構造で製造する場合よりもマスク形成工程及び不純物導入工程を其々１回分ずつ少なくする事が出来る。それ故、最小限の製造工程数によって、各ＴＦＴの電気的特性を向上可能な半導体装置を実現する事が出来る。
【０４８６】
特に、本発明に係る半導体装置を駆動回路内蔵型のアクティブマトリクス基板に適用した場合には、画素領域では、表示むらなどが発生しにくいＴＦＴを形成出来る一方、駆動回路部では、誤動作が発生しにくいと共に、ＣＭＯＳ回路の電源端子間を貫通する電流が小さいＴＦＴを形成出来るなど、画素領域及び駆動回路部毎にＴＦＴの電気的特性を向上する事が出来る。
【０４８７】
本発明に於いて、オフセット構造で有る第二導電型ＴＦＴを弱いデプレーション・モードとして構成し、ＬＤＤ構造で有る第一導電型ＴＦＴを弱いエンハンス・モードとして構成する様に、第二導電型薄膜トランジスタのチャネル領域およびオフセット領域に於ける第二導電型の不純物濃度を設定した場合には、一般的には、オフセット構造のＴＦＴは、ＬＤＤ構造のＴＦＴよりもオン状態が小さい傾向にあるが、本発明によれば、同じ絶対値のゲート電圧を印加したときでも、第二導電型ＴＦＴには、第一導電型ＴＦＴに比して大きなゲート・バイアス電圧が印加される事になる為、両ＴＦＴのオン電流バランスを確保する事が出来る。しかも、第二導電型薄膜トランジスタのチャネル領域及びオフセット領域に於ける第二導電型の不純物濃度によって実現する為、トランジスタ容量のバランスを確保する事も出来る。それ故、高速動作が可能なＣＭＯＳ回路を構成する事が出来る。
【０４８８】
本発明に於いて、第一導電型ＴＦＴのチャネル領域が含む第二導電型不純物の濃度と、第二導電型ＴＦＴのチャネル領域が含む第二導電型不純物濃度と、第２導電型ＴＦＴのオフセット領域が含む第二導電型不純物濃度とを総て等しくすると、即ち第二導電型ＴＦＴのチャネル領域に第二導電型不純物を導入する際に、第一導電型ＴＦＴのチャネル領域にも第二導電型不純物を導入すると、マスクを用いずに、チャネル領域に第二導電型不純物を導入出来るので、工程数を削減出来る。
【０４８９】
又本発明では、半導体膜の上層に容量素子の一方の電極を形成する前に、ＴＦＴの低濃度ソース・ドレイン領域または高濃度ソース・ドレイン領域を形成する為の不純物導入工程を行うと共に、この工程を利用して、容量素子を形成する為の半導体膜に不純物を導入し、容量素子の他方の電極を構成する事に特徴を有する。従って、本発明によれば、従来の製造方法に比較して、マスク形成工程の数及び不純物導入工程の数を減らす事が可能で有る。
【０４９０】
ＴＦＴの低濃度ソース・ドレイン領域を形成するにあたって、オフセットゲート構造とした場合には、ＬＤＤ構造に比較して、マスク形成工程及び不純物導入工程を１回ずつ少なくする事が出来る。
【０４９１】
第一導電型薄膜トランジスタの低濃度ソース・ドレイン領域を、第一導電型不純物と共に、第二導電型薄膜トランジスタの低濃度ソース・ドレイン領域と同等の第二導電型不純物を導入した低濃度第一導電型領域として構成した場合には、この低濃度ソース・ドレイン領域と第一の電極部との間で実質的な不純物濃度を変える事が出来る。
【０４９２】
第一導電型薄膜トランジスタの低濃度ソース・ドレイン領域を形成する為に低濃度の第一導電型不純物を導入する工程、及び第二導電型薄膜トランジスタの低濃度ソース・ドレイン領域を形成する為に低濃度の第二導電型不純物を導入する工程の内の一方の工程をマスクを形成せずに行い、第一及び第二導電型の不純物の双方が導入される領域の導電型及び不純物濃度については第１及び第二導電型の不純物の導入量の差によって規定した場合には、マスク形成工程をさらに減らす事が出来る。
【図面の簡単な説明】
【図１】 本発明の実施例１に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図２】 （ａ）は、図１に示すＴＦＴを用いた液晶表示装置のアクティブマトリクス基板等の半導体装置の説明図、（ｂ）は、その駆動回路に用いたＣＭＯＳ回路の説明図で有る。
【図３】 図１に示すアクティブマトリクス基板等の半導体装置上の各ＴＦＴのオン・オフ電流特性を比較して示すグラフ図で有る。
【図４】 （ａ）〜（ｄ）は、図１に示すアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図５】 （ａ）〜（ｄ）は、図１に示すアクティブマトリクス基板等の半導体装置の別の製造方法を示す工程断面図で有る。
【図６】 本発明の実施例２に係る液晶表示装置のアクティブマトリクス基板等の半導体装置に形成した各ＴＦＴのオン・オフ電流特性を比較して示すグラフ図で有る。
【図７】 本発明の実施例３乃至５に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図８】 液晶表示装置のアクティブマトリクス基板等の半導体装置に構成されている保持容量の構造を示す説明図で有る。
【図９】 （ａ）〜（ｅ）は、本発明の実施例３に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１０】 （ａ）〜（ｅ）は、本発明の実施例４に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１１】 （ａ）〜（ｅ）は、本発明の実施例５に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１２】 本発明の実施例６に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図１３】 （ａ）〜（ｄ）は、本発明の実施例６に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１４】 本発明の実施例７に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図１５】 （ａ）〜（ｅ）は、本発明の実施例７に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１６】 （ａ）〜（ｅ）は、本発明の実施例８に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１７】 （ａ）〜（ｅ）は、本発明の実施例９に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図１８】 本発明の実施例１０に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図１９】 （ａ）〜（ｄ）は、本発明の実施例１０に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２０】 本発明の実施例１１に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図２１】 （ａ）〜（ｅ）は、本発明の実施例１１に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２２】 （ａ）〜（ｅ）は、本発明の実施例１２に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２３】 本発明の実施例１３に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図２４】 （ａ）〜（ｅ）は、本発明の実施例１３に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２５】 （ａ）〜（ｅ）は、本発明の実施例１４に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２６】 （ａ）〜（ｅ）は、本発明の実施例１５に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２７】 本発明の実施例１６に係る液晶表示装置のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図２８】 （ａ）〜（ｄ）は、本発明の実施例１６に係る液晶表示装置のアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【図２９】 従来のアクティブマトリクス基板等の半導体装置を模式的に示す断面図で有る。
【図３０】 セルフアライン構造のＴＦＴのオン・オフリーク電流特性を示すグラフ図で有る。
【図３１】 （ａ）は、Ｎ型のＴＦＴに於けるチャネル長とソース・ドレイン間の耐電圧との関係を示すグラフ図、（ｂ）は、Ｐ型のＴＦＴに於けるチャネル長とソース・ドレイン間の耐電圧との関係を示すグラフ図で有る。
【図３２】 ＬＤＤ構造のＴＦＴのオン・オフリーク電流特性を示すグラフ図で有る。
【図３３】 （ａ）〜（ｆ）は、図２９に示すアクティブマトリクス基板等の半導体装置の製造方法を示す工程断面図で有る。
【符号の説明】
１、１″・・・アクティブマトリクス基板（半導体装置）
２・・・絶縁基板
１０、１０″・・・Ｎ型の画素用ＴＦＴ
２０、２０″・・・Ｎ型の駆動回路用ＴＦＴ
３０、３０′、３０″・・・Ｐ型の駆動回路用ＴＦＴ
ｎ１、ｎ２・・・Ｎ型のＴＦＴ
ｐ１、ｐ２・・・Ｐ型のＴＦＴ
１１、１２、２１、２２、３１、３２・・・ソース・ドレイン領域
１３、２３、３３・・・チャネル領域
１４、２４、３４・・・ゲート絶縁膜
１５、２５、３５・・・ゲート電極
８２・・・データドライバ部（駆動回路）
８３・・・走査ドライバ部（駆動回路）
８４、８８・・・シフトレジスタ
８５、８９・・・レベルシフタ
９０・・・信号線
９１・・・走査線
９２・・・画素用ＴＦＴ
１１１、１２１、２１１、２２１、３１１、３２１・・・低濃度ソース・ドレイン領域
３１１′、３２１′・・・オフセット領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as an active matrix substrate including different conductive thin film transistors (hereinafter abbreviated as TFTs), TFTs and capacitive elements, and a method for manufacturing the same. More specifically, the present invention relates to a technique for optimizing the electrical characteristics of the TFT while simplifying the manufacturing process of these semiconductor devices.
[0002]
[Prior art]
As a semiconductor device using a TFT, there is an active matrix substrate with a built-in driving circuit of a liquid crystal display device. In the active matrix substrate, as schematically shown in FIG. 29, the drive circuit portion and the pixel region from the left region to the right region, a P-type drive circuit TFT 30 ″, an N-type drive circuit TFT 20 ″, And the N-type pixel TFT 10 ″ are formed on the same insulating substrate 2. Here, when each TFT is formed in a self-aligned structure, the on / off leakage current characteristics of the N-type TFT are shown in FIG. There is a problem that the off-leakage current is large as indicated by L1 and the on / off-leakage current characteristic of the P-type TFT is indicated by a dotted line L2. This is likely to cause unevenness, etc. Also, even if the TFT for the drive circuit has a large off-leakage current, it tends to cause unnecessary power consumption and malfunction. In the in-structure TFT, the withstand voltage characteristic in the N-type TFT is shown by a solid line L23 in FIG. 31A, and the withstand voltage characteristic in the P-type TFT is shown by a solid line L24 in FIG. Since the withstand voltage between the source and drain of the TFT is not sufficient, the channel length must be set longer.
[0003]
Therefore, in the active matrix substrate shown in FIG. 29, each TFT has an LDD structure. (In the present application, this may be abbreviated as LDD TFT.) Any of the TFTs formed on the active matrix substrate has inner gate electrodes 15 in source / drain regions 11, 12, 21, 22, 31, 32. The portions facing the end portions of 25 and 35 are low-concentration source / drain regions 111, 121, 211, 221, 311, and 321. For this reason, as shown in FIG. 32, the on / off leakage current characteristic of the N-type TFT is indicated by a solid line L3, and the on / off leakage current characteristic of the P-type TFT is indicated by a dotted line L4. Therefore, it is possible to prevent the occurrence of display unevenness and flicker, and to suppress malfunctions and wasteful power consumption. In the LDD structure TFT, the withstand voltage characteristic of the N-type TFT is shown by a solid line L21 in FIG. 31A, and the withstand voltage characteristic of the P-type TFT is shown by a solid line L22 in FIG. Similarly, since the withstand voltage between the source and the drain is high, there is an advantage that the channel length can be shortened.
[0004]
On the other hand, when the above-described semiconductor device is applied to an active matrix substrate, a storage capacitor 40 ″ may be formed on the same insulating substrate 2 in order to improve charge retention characteristics in the liquid crystal cell (FIG. 29). (Reference) Conventionally, the storage capacitor 40 ″ has a low-concentration N-type silicon film obtained by making a silicon film conductive as a lower electrode part 40g. Here, a silicon oxide film formed simultaneously with the gate insulating films 14, 24, and 34 of the TFT is formed as a dielectric film 44 on the surface side of the lower layer side electrode portion 40 g. On the surface side of the dielectric film 44, a part of a dedicated capacity line or a part of a signal line in the previous stage formed simultaneously with the gate electrodes 15, 25, and 35 of the TFT is formed as the upper layer side electrode part 45. .
[0005]
The active matrix substrate 1 ″ having such a structure has been conventionally manufactured by the following method.
[0006]
First, as shown in FIG. 33A, the gate insulating films 14, 24, 34 and the dielectric film 44 are formed on the island-shaped silicon films 10a, 20a, 30a, 40a formed on the surface of the insulating substrate 2. About 1 × 10¹²cm^-2Boron ions are implanted at a dose of. This is for channel doping (first impurity introduction step). As a result, each silicon film 10a, 20a, 30a, 40a becomes a low concentration P-type. This is performed to adjust the threshold voltage (Vth) of the thin film transistor. (In this application, this may be abbreviated as channel dope, C / D.)
Next, as shown in FIG. 33B, each TFT formation region is covered with a resist mask 151 (first mask formation step). Then about 3 × 1014cm^-2Phosphorus ions are implanted at a dose of 2 nm to invert the silicon film 40a to N-type to form a lower electrode portion 40g for forming the storage capacitor 40 ″ (second impurity introduction step).
[0007]
Next, as shown in FIG. 33 (c), the gate electrodes 15, 25, and 35 and the upper layer side electrode portion 45 are formed, the storage capacitor 40 ″ is formed, and then the N-type pixel TFT 10 ″ and the N-type are formed. The drive circuit TFT 20 ″ formation region is covered with a resist mask 152 (second mask formation step).¹³cm^-2The boron ion is implanted at a dose of about 2.1 × 10¹⁸cm^-3Low concentration P-type source / drain regions 31 and 32 are formed (third impurity introduction step). A portion where no impurity is introduced becomes a channel region 33.
[0008]
Next, as shown in FIG. 33 (d), the formation region of the P-type driving circuit TFT 30 ″ is covered with a resist mask 153 (third mask formation step).¹³cm^-2Impurity concentration is about 0.9 × 10 5 by implanting phosphorus ions at a dose of¹⁸cm^-3Low concentration N-type source / drain regions 11, 12, 21, and 22 are formed (fourth impurity introduction step).
[0009]
Next, as shown in FIG. 33 (e), in addition to the formation region of the N-type pixel TFT 10 ″, the formation region of the N-type drive circuit TFT 20 ″, and the storage capacitor 40 ″, the gate electrode 35 is also provided. A resist mask 154 is formed to cover a wider area (fourth mask formation step), followed by approximately 1 × 10.¹⁵cm^-2Boron ions are implanted at a dose of about 1 × 10²⁰cm^-3High concentration source / drain regions 312 and 322 are formed (fifth impurity introduction step). As a result, in the low concentration P-type source / drain regions 31, 32, the portion covered with the resist mask 154 has an impurity concentration of about 2.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321. In this way, a P-type driving circuit TFT 30 ″ is formed.
[0010]
Next, as shown in FIG. 33F, in addition to the formation region of the P-type driving circuit TFT 30 ″, a resist mask 155 that covers the gate electrodes 15 and 25 is formed (fifth mask formation). Step) Subsequently, about 1 × 10¹⁵cm^-2Impurity concentration is about 1 × 10 5 by implanting phosphorus ions at a dose of²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed (sixth impurity introduction step). Of the low-concentration N-type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 155 has an impurity concentration of about 0.9 × 10 18 cm.^-3Low concentration source / drain regions 111, 121, 211, and 221. In this manner, an N-type pixel TFT 10 ″ and an N-type drive circuit TFT 20 ″ are formed.
[0011]
Thereafter, after forming the interlayer insulating film 4 as shown in FIG. 29, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, 37. Thus, the active matrix substrate 1 ″ is completed. Thus, in the prior art, five mask formation steps (formation of the resist masks 151 to 155) and six impurity introductions are performed only for adding donor or acceptor impurities to the semiconductor film. However, if the storage capacitor 40 ″ is not formed, four mask formation steps (formation of resist masks 152 to 155) are performed only for adding donor or acceptor impurities to the semiconductor film. Five impurity introduction steps are performed.
[0012]
[Problems to be solved by the invention]
However, since the manufacturing cost of the active matrix substrate is largely governed by the number of mask forming steps and the number of impurity introduction steps, the number of manufacturing steps will increase significantly when trying to optimize the TFT as in the prior art. There is a problem. For example, when a CMOS structure is formed with LDD TFTs and a storage capacitor 40 ″ is formed as in the manufacturing method described with reference to FIGS. 33A to 33F, donor or acceptor impurities are added to the semiconductor film. The addition of 5 mask formation steps and 6 impurity introduction steps are necessary only for the addition, and this leads to a problem that the manufacturing cost of the active matrix substrate is significantly increased. Not only the matrix substrate but also other semiconductor devices having TFTs of different conductivity types and other semiconductor devices having both TFTs and capacitive elements exist.
[0013]
  In view of the above problems, the subject of the present invention is at least a TFT and a TF having a different conductivity type from that of the TFT, like an active matrix substrate with a built-in drive circuit.TIn the provided semiconductor device,While simplifying the manufacturing process of the semiconductor device, the electrical characteristics of the TFT were optimized and a high-performance circuit was achieved.A semiconductor device, a manufacturing method thereof, and an active matrix substrate are provided.
[0014]
[Means for solving the problems]
In order to solve the above-described problems, the present invention configures a semiconductor device as follows. Each invention described below has a common purpose and problem of a semiconductor device and a manufacturing method thereof in which the electrical characteristics of each TFT are improved by a minimum number of manufacturing steps. If they are further classified, The invention according to the first group is roughly divided into the invention according to the second group.
[0015]
The invention according to the first group is a semiconductor device having first and second conductivity type TFTs on the same substrate, an active matrix substrate for a liquid crystal display device adapted to the same, and a method of manufacturing these semiconductor devices. Invention.
[0016]
On the other hand, the invention according to the second group relates to a semiconductor device having a TFT and a capacitive element on the same substrate, an invention relating to an active matrix substrate for a liquid crystal display device and the like adapted thereto, and a method for manufacturing these semiconductor devices. It is an invention.
[0017]
(Invention related to Group 1)
The invention relating to an example of the first group includes a first conductivity type thin film transistor comprising a first channel region and a first conductivity type high concentration source / drain region facing a first gate electrode through a first gate insulating film, In a semiconductor device having a second channel region facing a second gate electrode through a second gate insulating film and a second conductivity type thin film transistor having a second conductivity type high concentration source / drain region, the first conductivity The thin film transistor has an LDD structure including a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region, and the first channel region is extremely low. The second conductivity type thin film transistor is the same as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. Form an offset structure comprising an offset region having a net things concentration, said second channel region, characterized in that there comprises a second conductivity type impurity of very low concentration.
[0018]
When configured in this manner, each TFT has a low concentration region because the portion facing the end of the gate electrode is a low concentration region. In addition, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Accordingly, the on-current increases and the transistor capacity can be further reduced, so that there is an advantage that high-speed operation is possible. Further, in the second conductivity type driving circuit TFT, the low concentration region facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, the mask formation process and the impurity introduction process can be reduced by one time each, compared with the case where all TFTs are manufactured with the LDD structure. The second conductivity type impurity introduced at an extremely low concentration adjusts Vth in the channel and acts as a low concentration majority carrier in the offset region. Thus, a semiconductor device in which the electrical characteristics of each TFT are optimized can be realized with a minimum number of manufacturing steps.
[0019]
The source-drain voltage of the first conductivity type thin film transistor is V_DS1, The gate voltage is V_GS1Source / drain current I_DS1And the source-drain voltage of the second conductivity type thin film transistor is V_DS2, The gate voltage is V_GS2Source / drain current I_DS2| V_DS1| = | V_DS2｜ and V_GS1= V_GS2I under the condition of = 0_DS2> I_DS1As described above, the second conductivity type impurity concentration of the second channel region and the offset region is determined.
[0020]
With this configuration, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the on-current and transistor capacity of the first conductivity type TFT and the second conductivity type TFT are made substantially equal. Things are possible. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and is less likely to malfunction. At the same time, the circuit configuration and layout are simplified. (In order to make the size and dimensions of the first conductivity type TFT and the second conductivity type TFT the same.)
The source-drain voltage of the first conductivity type thin film transistor is V_DS1, The gate voltage is V_GS1Source / drain current I_DS1And the source-drain voltage of the second conductivity type thin film transistor is V_DS2, The gate voltage is V_GS2Source / drain current I_DS2| V_DS1| = | V_DS2｜ and V_GS1= V_GS2Under the conditions of_DS2= I_DS1The second conductivity type impurity concentration of the second channel region and the offset region is determined so that the gate voltage is shifted from 0V to the direction in which the first conductivity type thin film transistor is turned on. It is characterized by things.
[0021]
With this configuration, the second conductivity type TFT having the offset structure can be reduced by simply optimizing the second conductivity type impurity concentration in the channel region and the offset region of the second conductivity type TFT. The first conductivity type TFT having the LDD structure can be set to a weak enhancement mode. In this way, it is possible to minimize the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region, and to substantially equalize the on-current and transistor capacity of the first conductivity type TFT and the second conductivity type TFT. . Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and is less likely to malfunction. At the same time, the circuit configuration and layout are simplified. (In order to make the size and dimensions of the first conductivity type TFT and the second conductivity type TFT the same.)
Further, the second conductivity type impurity concentration contained in the first channel region, the second conductivity type impurity concentration contained in the second channel region, and the second conductivity type impurity concentration contained in the offset region are all equal. Features.
[0022]
That is, when the second conductivity type impurity is introduced into the channel region of the second conductivity type TFT, the second conductivity type impurity is also introduced into the channel region of the first conductivity type TFT, and at the same time, the second conductivity type impurity is also introduced into the offset region. Can be introduced. Therefore, the number of processes can be reduced.
[0023]
The first conductivity type and the second conductivity type mean that they are opposite to each other. When the first conductivity type is N type, the second conductivity type is P type. Conversely, when the first conductivity type is P type, the second conductivity type is N type.
[0024]
In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductive type and the second conductive type thin film transistor constitute a CMOS circuit in a drive circuit, and the first conductive type and the second conductive type thin film transistor. One of the conductive thin film transistors constitutes a pixel thin film transistor in the pixel region.
[0025]
In the manufacture of the semiconductor device according to the above example of the first group invention, the second conductivity type impurity is formed at a very low concentration in order to form the first channel region, the second channel region, and the offset region. Forming an ultra-low concentration second conductivity type impurity introduction step to be introduced into the film; forming a gate electrode forming step of forming the first gate electrode and the second gate electrode; and forming the first conductivity type low concentration source / drain region. For this purpose, a low-concentration first-conductivity-type impurity introduction step for introducing the first-conductivity-type impurity into the semiconductor film at a low concentration, and a first-conductivity-type impurity to form the first-conduction type high-concentration source / drain region High concentration first conductivity type impurity introduction step for introducing high concentration into semiconductor film, and second conductivity type impurity at high concentration to form said second conductivity type high concentration source / drain region High concentration A two-conductivity type impurity introduction step, wherein the very low concentration second conductivity type impurity introduction step is performed before the gate electrode formation step, and the low concentration first conductivity type impurity introduction step is performed after the gate electrode formation. It is characterized by being.
[0026]
  In the ultra-low concentration second conductivity type impurity introduction step, the source-drain voltage of the first conductivity type thin film transistor is set to V _DS1 , The gate voltage is V _GS1 Source / drain current I _DS1 And the source-drain voltage of the second conductivity type thin film transistor is V _DS2 , The gate voltage is V _GS2 Source / drain current I _DS2 | V _DS1 | = | V _DS2 ｜ and V _GS1 = V _GS2 I under the condition of = 0 _DS2 > I _DS1 Or | V _DS1 | = | V _DS2 ｜ and V _GS1 = V _GS2 Under the conditions of _DS2 = I _DS1 The second conductivity type impurity concentration of the second channel region and the offset region is determined so that the gate voltage is shifted from 0V to the direction in which the first conductivity type thin film transistor is turned on. Features.
  In addition, the very low concentration second conductivity type impurity introduction step is performed as a step of forming a doped semiconductor film containing the second conductivity type impurity in an extremely low concentration, and after this step is performed, a gate insulating film is formed on the surface of the semiconductor film. There is a thing.
[0027]
Also, the very low concentration second conductivity type impurity introduction step is performed as a step of introducing the second conductivity type impurity at a low concentration to the semiconductor film formed before this step is performed, and the semiconductor film is formed after this step is performed. A gate insulating film may be formed on the surface.
[0028]
Also, the very low concentration second conductivity type impurity introduction step introduces the second conductivity type impurity at an extremely low concentration through a gate insulating film formed on the surface of the semiconductor film formed before this step. There are things to do as a process.
[0029]
The invention relating to the second example of the first group includes a first conductivity type thin film transistor comprising a first channel region facing a first gate electrode through a first gate insulating film, and a first conductivity type high concentration source / drain region, In a semiconductor device having a second channel region facing a second gate electrode through a second gate insulating film and a second conductivity type thin film transistor having a second conductivity type high concentration source / drain region, The one conductivity type thin film transistor has an LDD structure having a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region. The second conductivity type thin film transistor includes an extremely low concentration of the first conductivity type impurity, and the second conductivity type thin film transistor is the same as the second channel region between the second conductivity type high concentration source / drain region and the second channel region. Form an offset structure comprising an offset region having an impurity concentration, said second channel region, characterized in that there comprises a first conductivity type impurity of very low concentration.
[0030]
When configured in this manner, each TFT has a low concentration region because the portion facing the end of the gate electrode is a low concentration region. In addition, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Accordingly, the on-current increases and the transistor capacity can be further reduced, so that there is an advantage that high-speed operation is possible. Further, in the second conductivity type driving circuit TFT, the low concentration region facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, the mask formation process and the impurity introduction process can be reduced by one time each compared with the case where all TFTs are manufactured with the LDD structure. The first conductivity type impurity introduced at a very low concentration adjusts Vth in the channel and acts as a low concentration majority carrier in the offset region. Thus, a semiconductor device in which the electrical characteristics of each TFT are optimized can be realized with a minimum number of manufacturing steps.
[0031]
The source-drain voltage of the first conductivity type thin film transistor is V_DS1, The gate voltage is V_GS1Source / drain current I_DS1And the source-drain voltage of the second conductivity type thin film transistor is V_DS2, The gate voltage is V_GS2Source / drain current I_DS2| V_DS1| = | V_DS2｜ and V_GS1= V_GS2I under the condition of = 0_DS2> I_DS1As described above, the first conductivity type impurity concentrations of the second channel region and the offset region are determined.
[0032]
With this configuration, the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region is minimized, and the on-current and transistor capacity of the first conductivity type TFT and the second conductivity type TFT are made substantially equal. Things are possible. Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and is less likely to malfunction. At the same time, the circuit configuration and layout are simplified. (In order to make the size and dimensions of the first conductivity type TFT and the second conductivity type TFT the same.)
The source-drain voltage of the first conductivity type thin film transistor is V_DS1, The gate voltage is V_GS1Source / drain current I_DS1And the source-drain voltage of the second conductivity type thin film transistor is V_DS2, The gate voltage is V_GS2Source / drain current I_DS2| V_DS1| = | V_DS2｜ and V_GS1= V_GS2Under the conditions of_DS2= I_DS1The first conductivity type impurity concentration of the second channel region and the offset region is determined so that the gate voltage is shifted from 0V to the direction in which the first conductivity type thin film transistor is turned on. It is characterized by things.
[0033]
With this configuration, the second conductivity type TFT having the offset structure can be weakened by simply optimizing the impurity concentration of the first conductivity type in the channel region and offset region of the second conductivity type TFT. The first conductivity type TFT having the LDD structure can be set to a weak enhancement mode. In this way, it is possible to minimize the decrease in the on-current of the second conductivity type TFT due to the parasitic resistance in the offset region, and to substantially equalize the on-current and transistor capacity of the first conductivity type TFT and the second conductivity type TFT. . Therefore, when a CMOS circuit is configured with such TFTs, the circuit operates at high speed and is less likely to malfunction. At the same time, the circuit configuration and layout are simplified. (In order to make the size and dimensions of the first conductivity type TFT and the second conductivity type TFT the same.)
The first conductivity type impurity concentration contained in the first channel region, the first conductivity type impurity concentration contained in the second channel region, and the first conductivity type impurity concentration contained in the offset region are all equal. Features.
[0034]
That is, when the first conductivity type impurity is introduced into the channel region of the second conductivity type TFT, the first conductivity type impurity is also introduced into the channel region of the first conductivity type TFT, and at the same time, the first conductivity type impurity is also introduced into the offset region. Can be introduced. Therefore, the number of processes can be reduced.
[0035]
The first conductivity type and the second conductivity type mean that they are opposite to each other. When the first conductivity type is N type, the second conductivity type is P type. Conversely, when the first conductivity type is P type, the second conductivity type is N type.
[0036]
In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductive type and the second conductive type thin film transistor constitute a CMOS circuit in a drive circuit, and the first conductive type and the second conductive type thin film transistor. One of the conductive thin film transistors constitutes a pixel thin film transistor in the pixel region.
[0037]
In a method of manufacturing a semiconductor device according to the second example of the first group, a first conductivity type impurity is formed in a semiconductor film at an extremely low concentration in order to form the first channel region, the second channel region, and the offset region. In order to form a very low concentration first conductivity type impurity introduction step to be introduced, a gate electrode formation step to form the first gate electrode and the second gate electrode, and the first conductivity type low concentration source / drain region A low-concentration first-conductivity-type impurity introduction step for introducing the first-conductivity-type impurity into the semiconductor film at a low concentration; and a high-concentration of the first-conductivity-type impurity to form the first-conduction-type high-concentration source / drain region A high concentration first conductivity type impurity introduction step for introducing the second conductivity type impurity into the semiconductor film at a high concentration to form the second conductivity type high concentration source / drain region. Concentration second conductivity type impurity And the step of introducing the very low concentration first conductivity type impurity is performed before the gate electrode forming step, and the step of introducing the low concentration first conductivity type impurity is performed after the formation of the gate electrode. And
[0038]
  Further, in the step of introducing the very low concentration first conductivity type impurity, the source / drain voltage of the first conductivity type thin film transistor is set to_DS1, The gate voltage is V_GS1Source / drain current I_DS1And the source-drain voltage of the second conductivity type thin film transistor is V_DS2, The gate voltage is V_GS2Source / drain current I_DS2| V_DS1| = | V_DS2｜ and V_GS1= V_GS2I under the condition of = 0_DS2> I_DS1Or | V_DS1| = | V_DS2｜ and V_GS1= V_GS2Under the conditions of_DS2= I_DS1The first conductivity type impurity concentration of the second channel region and the offset region is determined so that the gate voltage is shifted from 0V to the direction in which the first conductivity type thin film transistor is turned on. It is characterized by introduction.
  Also, the very low concentration first conductivity type impurity introduction step is performed as a step of forming a doped semiconductor film containing the first conductivity type impurity at a very low concentration, and after this step is performed, a gate insulating film is formed on the surface of the semiconductor film. There is a thing.
[0039]
The very low concentration first conductivity type impurity introduction step is performed as a step of introducing the first conductivity type impurity at a low concentration with respect to the semiconductor film formed before this step is performed. A gate insulating film may be formed on the surface.
[0040]
In addition, in the very low concentration first conductivity type impurity introduction step, the first conductivity type impurity is introduced at a very low concentration through a gate insulating film formed on the surface of the semiconductor film formed before this step. There are things to do as a process.
[0041]
The invention relating to the third example of the first group is a first conductivity type thin film transistor comprising a first channel region and a first conductivity type high concentration source / drain region facing the first gate electrode through a first gate insulating film. And a second conductivity type thin film transistor comprising a second channel region facing the second gate electrode through a second gate insulating film and a second conductivity type high concentration source / drain region, The first conductivity type thin film transistor has an LDD structure including a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region. The second conductivity type thin film transistor has the same impurity concentration as that of the second channel region between the second conductivity type high concentration source / drain region and the second channel region. Form an offset structure comprising a that offset region, said second channel region, characterized in that there substantially intrinsic.
[0042]
When configured in this manner, each TFT has a low concentration region because the portion facing the end of the gate electrode is a low concentration region. In addition, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Accordingly, the on-current increases and the transistor capacity can be further reduced, so that there is an advantage that high-speed operation is possible. Furthermore, in the second conductivity type driving circuit TFT, the semiconductor facing the end of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Therefore, the mask forming process can be reduced once and the impurity introducing process can be reduced twice compared with the case where all TFTs are manufactured with the LDD structure. Thus, a semiconductor device in which the electrical characteristics of each TFT are optimized can be realized with a minimum number of manufacturing steps.
[0043]
The first conductivity type and the second conductivity type mean that they are opposite to each other. When the first conductivity type is N type, the second conductivity type is P type. Conversely, when the first conductivity type is P type, the second conductivity type is N type.
[0044]
In an active matrix substrate for a liquid crystal display device to which such a semiconductor device is applied, the first conductive type and the second conductive type thin film transistor constitute a CMOS circuit in a drive circuit, and the first conductive type and the second conductive type thin film transistor. One of the conductive thin film transistors constitutes a pixel thin film transistor in the pixel region.
[0045]
The invention according to an example of the second group of the present invention is opposed to a thin film transistor having a channel region facing a gate electrode through a gate insulating film and a source / drain region connected to the channel region, and a dielectric film. In the semiconductor device having the first electrode portion and the capacitive element including the second electrode portion, the thin film transistor has a low concentration source / drain region in which the source / drain region faces the end portion of the gate electrode through the gate insulating film. And an LDD structure having a high concentration source / drain region adjacent to the low concentration source / drain region, wherein the first electrode portion has the same conductivity type as the low concentration source / drain region, and the impurity of the conductivity type. It is characterized by being composed of the same semiconductor film having the same concentration.
[0046]
With such a configuration, it becomes possible to simultaneously produce a low concentration source / drain region and a first electrode portion, and such a semiconductor device can be manufactured with a small number of steps by taking advantage of the LDD TFT. .
[0047]
The present invention according to the second example of the second group of the present invention includes a thin film transistor including a channel region facing a gate electrode through a gate insulating film, a source / drain region connected to the channel region, and a dielectric film. In the semiconductor device having the first electrode portion and the capacitive element composed of the second electrode portion opposed to each other, the thin film transistor has a low concentration source in which the source / drain regions are opposed to the end portion of the gate electrode through the gate insulating film. An LDD structure having a drain region and a high concentration source / drain region adjacent to the low concentration source / drain region, wherein the first electrode portion has the same conductivity type as the high concentration source / drain region; It is characterized in that it is composed of the same semiconductor film having the same type impurity concentration.
[0048]
With such a configuration, it becomes possible to simultaneously create a high concentration source / drain region and a first electrode portion, and by utilizing the advantages of LDD TFT, such a semiconductor device can be manufactured with a small number of processes. . Further, the low concentration source / drain regions can be formed in a self-aligned manner with respect to the gate electrode, and a good TFT with little parasitic capacitance can be obtained.
[0049]
The invention according to the third example of the second group of the present invention includes a thin film transistor including a channel region facing a gate electrode through a gate insulating film and a source / drain region containing a high concentration of donor impurities or acceptor impurities, and a dielectric In a semiconductor device having a capacitor element composed of a first electrode portion and a second electrode portion facing each other through a film, the thin film transistor has a channel region between the end portion of the source / drain region and the end portion of the channel region. And the first electrode portion is made of the same semiconductor film having the same conductivity type and the same impurity concentration as the high concentration source / drain region. It is characterized by.
[0050]
With such a configuration, it becomes possible to simultaneously create a high concentration source / drain region and a first electrode portion, and by taking advantage of the offset TFT, such a semiconductor device can be manufactured with a small number of processes. . Further, the low concentration source / drain regions can be formed in a self-aligned manner with respect to the gate electrode, and a good TFT with little parasitic capacitance can be obtained.
[0051]
The invention according to the fourth example of the second group of the present invention includes a first conductivity type and a second conductivity type comprising a channel region facing a gate electrode through a gate insulating film, and a source / drain region connected to the channel region. In a semiconductor device having a thin film transistor and a capacitive element composed of a first electrode portion and a second electrode portion opposed via a dielectric film, the first and second conductivity type thin film transistors have source / drain regions. An LDD structure comprising a low concentration source / drain region facing each other through a gate insulating film at an end of the gate electrode and a high concentration source / drain region adjacent to the low concentration source / drain region is formed. The same conductivity type as the low-concentration source / drain regions of the first conductivity type and second conductivity type thin film transistors and the same impurity concentration of the conductivity type. , Characterized in that it is configured.
[0052]
With such a configuration, it becomes possible to simultaneously create a low concentration source / drain region and a first electrode portion, and by taking advantage of the LDD CMOS TFT, such a semiconductor device can be manufactured with a small number of processes. The
[0053]
The invention relating to the second group of the fifth example of the present invention is a first conductive type and second conductive type thin film transistor comprising a channel region facing a gate electrode through a gate insulating film and a source / drain region connected to the channel region. And a capacitor element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film interposed therebetween, wherein the source / drain regions of the first and second conductivity type thin film transistors are gates An LDD structure comprising a lightly doped source / drain region facing a gate insulating film at an end of an electrode and a heavily doped source / drain region adjacent to the lightly doped source / drain region is formed, and the first electrode part Are the same semiconductor film having the same conductivity type as that of the high-concentration source / drain regions of the first conductivity type and second conductivity type thin film transistors, and having the same impurity concentration of the conductivity type. Made is possible and said that.
[0054]
With such a configuration, it becomes possible to simultaneously create a high concentration source / drain region and a first electrode portion, and by taking advantage of the LDD CMOS TFT, such a semiconductor device can be manufactured with a small number of processes. The Further, the low concentration source / drain regions can be formed in a self-aligned manner with respect to the gate electrode, and a good TFT with little parasitic capacitance can be obtained.
[0055]
Further, the first electrode portion is composed of a semiconductor film containing a first conductivity type impurity in the same amount as the first conductivity type impurity of the low-concentration source / drain region of the first conductivity type thin film transistor. The low-concentration source / drain region of the thin-film transistor has a second conductivity-type impurity that is less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity and the same amount as the low-concentration source / drain region of the second-conduction-type thin film transistor It is characterized by including.
[0056]
With such a configuration, the advantage of the LDD CMOS TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0057]
The first electrode portion is formed of a semiconductor film containing a second conductivity type impurity in the same amount as the second conductivity type impurity of the low-concentration source / drain region of the second conductivity type thin film transistor. The low-concentration source / drain region of the thin-film transistor has a second conductivity-type impurity that is less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity and the same amount as the low-concentration source / drain region of the second-conduction-type thin film transistor It is characterized by including.
[0058]
With such a configuration, the advantage of the LDD CMOS TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0059]
Further, the first electrode portion is composed of a semiconductor film containing the same amount of first conductivity type impurities as the first conductivity type impurities included in the high concentration source / drain regions of the first conductivity type thin film transistor. The low-concentration source / drain region of the thin-film transistor has a second conductivity-type impurity that is less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity and the same amount as the low-concentration source / drain region of the second-conduction-type thin film transistor It is characterized by including.
[0060]
With such a configuration, the advantage of the LDD CMOS TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0061]
The first electrode portion is formed of a semiconductor film containing a second conductivity type impurity in the same amount as the second conductivity type impurity included in the high-concentration source / drain region of the second conductivity type thin film transistor. The low-concentration source / drain region of the thin-film transistor has a second conductivity-type impurity that is less than the first-conductivity-type impurity amount together with the first-conductivity-type impurity and the same amount as the low-concentration source / drain region of the second-conduction-type thin film transistor It is characterized by including.
[0062]
With such a configuration, the advantage of the LDD CMOS TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0063]
The invention according to the sixth example of the second group of the present invention includes a channel region facing the gate electrode through a gate insulating film and a high concentration first conductivity type source / drain region containing a high concentration of first conductivity type impurities. A first conductivity type thin film transistor, a second conductivity type thin film transistor comprising a channel region facing the gate electrode through a gate insulating film and a high concentration second conductivity type source / drain region containing a high concentration of second conductivity type impurities; In a semiconductor device having a first electrode portion and a capacitive element composed of a second electrode portion facing each other with a dielectric film interposed therebetween, the first conductivity type thin film transistor has a high concentration first conductivity type source / drain region end. An LDD structure having a low-concentration first conductivity type source / drain region between the channel region end and the channel region end, and the second conductivity type thin film transistor comprises the high-concentration second conductivity type. An offset region having an impurity concentration equivalent to that of the channel region is provided between an end portion of the source / drain region and the end portion of the channel region, and the first electrode portion is a low concentration first conductivity type source of the first conductivity type thin film transistor -It is comprised from the semiconductor film containing the 1st conductivity type impurity of the same quantity as a drain region, It is characterized by the above-mentioned.
[0064]
In such a configuration, the advantages of the LDD TFT and the offset TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0065]
The invention according to the seventh example of the second group of the present invention includes a channel region facing the gate electrode through a gate insulating film and a high concentration first conductivity type source / drain region containing a high concentration of first conductivity type impurities. A first conductivity type thin film transistor, a second conductivity type thin film transistor comprising a channel region facing the gate electrode through a gate insulating film and a high concentration second conductivity type source / drain region containing a high concentration of second conductivity type impurities; In a semiconductor device having a first electrode portion and a capacitive element composed of a second electrode portion facing each other with a dielectric film interposed therebetween, the first conductivity type thin film transistor comprises the end portion of the high concentration first conductivity type source / drain region. And an LDD structure having a low concentration first conductivity type source / drain region between the channel region end and the second conductivity type thin film transistor. An offset region having an impurity concentration equivalent to that of the channel region is provided between an end portion of the source / drain region and the end portion of the channel region, and the first electrode portion has a high concentration first conductivity type of the first conductivity type thin film transistor. It is characterized by being composed of a semiconductor film containing the same amount of first conductivity type impurities as the source / drain regions.
[0066]
In such a configuration, the advantages of the LDD TFT and the offset TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0067]
The invention according to Group 8 of the second group of the present invention includes a channel region facing the gate electrode through a gate insulating film and a high concentration first conductivity type source / drain region containing a high concentration of first conductivity type impurities. A first conductivity type thin film transistor, a second conductivity type thin film transistor comprising a channel region facing the gate electrode through a gate insulating film, a high concentration second conductivity type source / drain region containing a high concentration of second conductivity type impurities, and a dielectric In a semiconductor device having a first electrode portion and a capacitive element composed of a second electrode portion facing each other through a body film, the first conductivity type thin film transistor includes the high concentration first conductivity type source / drain region end portion and An LDD structure having a low-concentration first conductivity type source / drain region between end portions of the channel region is formed, and the second conductivity type thin film transistor includes the high concentration second conductivity type saw. An offset region having an impurity concentration equivalent to that of the channel region is provided between the drain region end and the channel region end, and the first electrode portion is a high concentration second conductivity type source of the second conductivity type thin film transistor. It is characterized by being composed of a semiconductor film containing the same amount of second conductivity type impurities as the drain region.
[0068]
In such a configuration, the advantages of the LDD TFT and the offset TFT can be utilized to further reduce the photo process by one process, and such a semiconductor device can be manufactured with a smaller number of processes.
[0069]
An active matrix substrate using the semiconductor device according to any one of the second group, wherein the first conductivity type and the second conductivity type thin film transistor constitute a CMOS circuit in a drive circuit portion, and At least one of the one-conductivity-type and second-conductivity-type thin film transistors constitutes a pixel thin film transistor in the pixel region, and the capacitive element constitutes a storage capacitor for the liquid crystal cell in the pixel region. It is characterized by.
[0070]
As a method for manufacturing the semiconductor device related to the second group, there are various examples listed below. For example, an LDD thin film transistor having a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region electrically connected to the channel region via a low concentration source / drain region is opposed to the channel region via a dielectric film. Forming a semiconductor film comprising at least the channel region, the low-concentration source / drain region, and the first electrode portion in a method of manufacturing a semiconductor device having a capacitive element comprising a first electrode portion and a second electrode portion A first step of forming a low-concentration source / drain region and the first electrode portion by introducing an impurity serving as a donor or acceptor at a low concentration into a part of the semiconductor film; And a third step of forming a gate electrode and a second electrode portion after the completion of the two steps.
[0071]
Further, an LDD type thin film transistor having a gate electrode, a gate insulating film, a channel region, and a high concentration source / drain region electrically connected to the channel region via a low concentration source / drain region is opposed to the channel region via a dielectric film. Forming a semiconductor film comprising at least the channel region, the high-concentration source / drain region, and the first electrode portion in a method of manufacturing a semiconductor device having a capacitive element comprising a first electrode portion and a second electrode portion A first step of forming a high-concentration source / drain region and the first electrode portion by introducing an impurity which becomes a donor or an acceptor at a high concentration into a part of the semiconductor film; And a third step of forming a gate electrode and a second electrode portion after the completion of the two steps.
[0072]
An offset type comprising a gate electrode, a gate insulating film, a channel region, an offset region containing the same amount of impurities as the channel region, and a high concentration source / drain region conductively connected to the channel region through the offset region In a method of manufacturing a semiconductor device having a thin film transistor and a capacitive element composed of a first electrode portion and a second electrode portion facing each other with a dielectric film therebetween, at least the channel region, the high concentration source / drain region, and the first A first step of forming a semiconductor film constituting one electrode portion, and introducing a dopant or acceptor impurity at a high concentration into a part of the semiconductor film to form the high concentration source / drain region and the first electrode portion And a third step of forming a gate electrode and a second electrode portion after the second step is completed.
[0073]
The LDD type first comprising a gate electrode, a gate insulating film, a channel region, and a high concentration first conductivity type source / drain region electrically connected to the channel region via a low concentration first conductivity type source / drain region. LDD comprising a conductive thin film transistor, a gate electrode, a gate insulating film, a channel region, and a high concentration second conductivity type source / drain region electrically connected to the channel region via a low concentration second conductivity type source / drain region In a method of manufacturing a semiconductor device having a type second conductivity type thin film transistor and a capacitive element composed of a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween, at least the LDD type first conductivity type thin film transistor A channel region, a low concentration first conductivity type source / drain region, a channel region of the LDD type second conductivity type thin film transistor, A first step of forming a semiconductor film constituting an electrode portion; and introducing a first conductivity type impurity at a low concentration into a part of the semiconductor film to form the low concentration first conductivity type source / drain region and the first The method includes a second step of forming the electrode portion and a third step of forming the gate electrode and the second electrode portion after completion of the second step.
[0074]
The LDD type first comprising a gate electrode, a gate insulating film, a channel region, and a high concentration first conductivity type source / drain region electrically connected to the channel region via a low concentration first conductivity type source / drain region. LDD comprising a conductive thin film transistor, a gate electrode, a gate insulating film, a channel region, and a high concentration second conductivity type source / drain region electrically connected to the channel region via a low concentration second conductivity type source / drain region In a method of manufacturing a semiconductor device having a type second conductivity type thin film transistor and a capacitive element composed of a first electrode part and a second electrode part facing each other with a dielectric film interposed therebetween, at least the LDD type first conductivity type thin film transistor A channel region, a high concentration first conductivity type source / drain region, a channel region of the LDD type second conductivity type thin film transistor, A first step of forming a semiconductor film constituting an electrode portion; and introducing a first conductivity type impurity at a high concentration into a part of the semiconductor film to form the high concentration first conductivity type source / drain region and the first The method includes a second step of forming the electrode portion and a third step of forming the gate electrode and the second electrode portion after completion of the second step.
[0075]
In the manufacturing method according to any one of the second groups, in order to form the low-concentration first-conductivity-type source / drain regions of the LDD-type first-conductivity thin-film transistor, the first-conductivity-type impurity is present at a low concentration in the semiconductor. A low-concentration first-conductivity-type impurity introduction step to be introduced into the film, or a second-concentration-type impurity at a low-concentration in order to form a low-concentration second-conductivity type source / drain region of the LDD-type second-conductivity thin-film transistor One low concentration impurity introduction step of the low concentration second conductivity type impurity introduction step to be introduced into the semiconductor film is performed without forming a mask, and both the first conductivity type impurity and the second conductivity type impurity are introduced. The conductivity type and the substantial impurity concentration of the region to be formed are defined by the difference in the introduction amount of the first conductivity type impurity and the second conductivity type impurity.
[0076]
A gate electrode; a gate insulating film; a first channel region; and a high concentration first conductivity type source / drain region electrically connected to the first channel region via a low concentration first conductivity type source / drain region. LDD type first conductivity type thin film transistor, gate electrode, gate insulating film, second channel region, high concentration second conductivity type source / drain region, and second channel region end and high concentration second conductivity type source / drain An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as the second channel region between the region end and a first electrode portion and a second electrode portion facing each other through a dielectric film In a method of manufacturing a semiconductor device having a capacitive element, at least the first channel region, the low-concentration first conductivity type source / drain region, and the second channel. A first step of forming a semiconductor film constituting the region and the first electrode portion; and introducing a first conductivity type impurity at a low concentration into a part of the semiconductor film to form the low concentration first conductivity type source / drain The method includes a second step of forming the region and the first electrode portion, and a third step of forming the gate electrode and the second electrode portion after the second step is completed.
[0077]
A gate electrode; a gate insulating film; a first channel region; and a high concentration first conductivity type source / drain region electrically connected to the first channel region via a low concentration first conductivity type source / drain region. LDD type first conductivity type thin film transistor, gate electrode, gate insulating film, second channel region, high concentration second conductivity type source / drain region, and second channel region end and high concentration second conductivity type source / drain An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as the second channel region between the region end and a first electrode portion and a second electrode portion facing each other through a dielectric film In a method of manufacturing a semiconductor device having a capacitive element, at least the first channel region, the high-concentration first conductivity type source / drain region, and the second channel. A first step of forming a semiconductor film constituting the region and the first electrode portion; and introducing a first conductivity type impurity at a high concentration into a part of the semiconductor film to thereby form the high concentration first conductivity type source / drain The method includes a second step of forming the region and the first electrode portion, and a third step of forming the gate electrode and the second electrode portion after the second step is completed.
[0078]
A gate electrode; a gate insulating film; a first channel region; and a high concentration first conductivity type source / drain region electrically connected to the first channel region via a low concentration first conductivity type source / drain region. LDD type first conductivity type thin film transistor, gate electrode, gate insulating film, second channel region, high concentration second conductivity type source / drain region, and second channel region end and high concentration second conductivity type source / drain An offset type second conductivity type thin film transistor having an offset region having the same impurity concentration as the second channel region between the region end and a first electrode portion and a second electrode portion facing each other through a dielectric film In a method of manufacturing a semiconductor device having a capacitive element, at least the first channel region, the second channel region, and the high concentration second conductivity type source / drain A first step of forming a semiconductor film constituting the region and the first electrode portion; and introducing a second conductivity type impurity at a high concentration into a part of the semiconductor film to thereby form the high concentration second conductivity type source / drain The method includes a second step of forming the region and the first electrode portion, and a third step of forming the gate electrode and the second electrode portion after the second step is completed.
[0079]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings. In any of the embodiments described below, the semiconductor device according to the present invention is applied to an active matrix substrate with a built-in drive circuit in a liquid crystal display device. However, the semiconductor device of the present invention can be applied to a semiconductor device formed on an LSI or a ceramic substrate in addition to the active matrix substrate. In addition, since any of the active matrix substrates described below has the same basic structure as the active matrix substrate shown in FIG. 29, the portions having the corresponding functions are denoted by the same reference numerals in the following description. There is. In this example, the first conductivity type is described as N-type and the second conductivity type is described as P-type. Of course, the first conductivity type may be P-type and the second conductivity type may be N-type.
[0080]
Each of the embodiments discloses a semiconductor device in which the electrical characteristics of each TFT are improved with a minimum number of manufacturing steps and a method of manufacturing the semiconductor device. It can be roughly divided into groups and groups of Examples 3 to 16.
[0081]
  Examples 1 and 2 correspond to the invention according to the first group of the present invention. That is, the configuration has a first conductive type and a second conductive type TFT on the same substrate. On the other hand, Examples 3 to 16Is the firstThis corresponds to the invention according to Group 2. That is, it is based on a configuration having a TFT and a capacitor on the same substrate.
[0082]
[Example 1]
(Configuration of active matrix substrate)
FIG. 1 is a cross-sectional view schematically showing a structure when a semiconductor device according to the present invention is applied to an active matrix substrate with a built-in driving circuit in a liquid crystal display device.
[0083]
In FIG. 1, three types of TFTs are formed on the surface side of an insulating substrate 2 which is a base of an active matrix substrate 1, and a right-side pixel TFT 10 (first conductivity type) is shown on the right side. The first conductivity type TFT) is represented by the first conductivity type drive circuit TFT 20 (first conductivity type TFT), and the left side is represented by the second conductivity type drive. This is a circuit TFT 30 '(second conductivity type TFT). Among these TFTs, the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT 30 ′ constitute an inverter of the drive circuit as a CMOS circuit. That is, the active matrix substrate 1 shown in FIG. 1 is a semiconductor device having a first conductivity type TFT and a second conductivity type TFT.
[0084]
As shown in FIG. 2A, the liquid crystal display device has a pixel region partitioned and formed by a signal line 90 and a scanning line 91 on the active matrix substrate. There is a liquid crystal capacitor 94 of the liquid crystal cell to which a signal is input. For the signal line 90, a data driver unit 82 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is formed on an active matrix substrate. For the scanning line 91, a scanning driver unit 83 including a shift register 88 and a level shifter 89 is formed on an active matrix substrate. In the pixel region, a storage capacitor 40 is also formed between the preceding scanning line. Here, the TFT for the driving circuit is used for a shift register, a level shifter, an analog switch, and the like. The shift register will be described as an example. In the shift registers 84 and 88, as shown in FIG. 2B, a CMOS circuit is configured by the first conductivity type TFTs n1 and n2 and the second conductivity type TFTs p1 and p2, respectively. There is. Among these TFTs, the first conductivity type TFTs n1 and n2 correspond to the first conductivity type drive circuit TFT 20 shown in FIG. 1, and the second conductivity type TFTs p1 and p2 are the second conductivity type TFTs shown in FIG. The pixel TFT 92 corresponds to the first driving type TFT 30 ', and the pixel TFT 92 corresponds to the first conductivity type pixel TFT 10 shown in FIG.
[0085]
In FIG. 1 again, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are channels for forming a channel between the source / drain regions 11, 12, 21, 22. The channel regions 13 and 23 have low-concentration second conductivity type impurities (in this example, boron (B), aluminum (Al), gallium (Ga) exhibiting P-type conductivity). Acceptor impurities such as indium (In). Further, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are low in the first conductivity type facing the end portions of the gate electrodes 15 and 25 through the gate insulating films 14 and 24. Concentration source / drain region 111_,121, 211, and 221, and high-concentration source / drain regions 112, 122, 212, 222 of the first conductivity type to which the source / drain electrodes 16, 17, 26, 27 are electrically connected. In this example, since an N-type TFT is used as the first conductivity type TFT, the N-type impurities contained in the source / drain regions are phosphorus (P) and arsenic (As) indicating N-type conductivity. And antimony (Sb).
[0086]
On the other hand, the second conductivity type driving circuit TFT 30 ′ includes a channel region 33 containing a low concentration second conductivity type impurity and a gate insulating film 34 with respect to the end of the gate electrode 35 with the same impurity concentration as the channel region. And high concentration source / drain regions 312 and 322 of the second conductivity type to which the source / drain electrodes 36 and 37 are electrically connected.
[0087]
The channel regions 13, 23, 33 and the source / drain regions 11, 12, 21, 22, 31, 32 of both conductivity type TFTs are made of a semiconductor film such as silicon (Si) or germanium (Ge). As a kind of semiconductor film, in addition to the film made of these group 4 elements alone, silicon-germanium (Si_x  Ge_1-x  ; 0 <x <1), silicon carbide (Si_x  C_1-x  ; 0 <x <1), germanium carbide (Ge_x  C_1-x  A group 4 element complex such as 0 <x <1), a group 3 element such as gallium arsenic (GaAs) and indium antimony (InSb) and a group 5 element, and cadmium selenium (CdSe); A complex of a Group 2 element and a Group 5 element is also possible. The physical state of these semiconductors can be a single crystal state, a polycrystalline state, a microcrystalline state, a mixed crystal state, an amorphous state, or the like. In this example, a polycrystalline silicon film (poly-Si film) is used as a semiconductor film.
[0088]
In the active matrix substrate 1 configured in this manner, the channel regions 13, 23, and 33 are all channel-doped with low-concentration boron ions, so that the impurity concentration is about 1 × 10.¹⁶cm^-3To about 5 × 10¹⁷cm^-3It is a low-concentration second conductivity type region.
[0089]
In the drive circuit section of the present invention, even when CMOS circuits are connected in multiple stages, a TFT having an offset type or LDD structure is adopted, so that there is a parasitic capacitance between the gate electrode and the source / drain region. Therefore, high-speed operation is possible. Further, by reducing the transistor size (shortening the channel length), the on-current increases. Along with this, the transistor capacitance between the gate and the channel is reduced, and an extremely high-speed operation is realized. In addition, as will be described later, since the impurity for forming the low concentration region is introduced into the source / drain region in the same process as the channel doping, the number of manufacturing steps of the active matrix substrate 1 can be reduced. There is also.
[0090]
In this example, the channel doping is performed with the second conductivity type impurity. However, even when the first conductivity type impurity is channel doped, high-speed operation and a reduction in the number of manufacturing steps can be achieved.
[0091]
The first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 ′ have a gate insulating film on the surface side of the channel regions 13, 23, 33. 14, 24, 34 (silicon oxide films having a thickness of about 1200 angstroms), and gate electrodes 15, 25, 35 facing each other. Between each TFT, the length and width of the channel regions 13, 23, 33, etc. May be the same size to ensure balance of transistor capacity and the like.
[0092]
In the active matrix substrate 1, the source / drain regions 11, 12, 21, 22 are of the first conductivity type at portions facing the end portions of the gate electrodes 15, 25 via the gate insulating films 14, 24. The low-concentration source / drain regions 111, 121, 211, and 221 are provided, and the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 have an LDD structure.
[0093]
On the other hand, the source / drain regions 31 and 32 are offset regions 311 ′ and 321 ′ that face the end of the gate electrode 35 via the gate insulating film 34. 321 ′ has an impurity concentration of about 1 × 10 5 like the channel region 33.¹⁶cm^-3To about 5 × 10¹⁷cm^-3It is a low-concentration second conductivity type region.
[0094]
In the source / drain regions 11, 12, 21, and 22 of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20, the first conductivity type low-concentration source / drain regions 111 and 121 are provided. , 211 and 221 have an impurity concentration of about 5 × 10¹⁹cm^-3To about 5 × 10²⁰cm^-3High-concentration source / drain regions 112, 122, 212, and 222 of the first conductivity type, and for these high-concentration regions, source / drain electrodes 16, 17, such as signal lines and pixel electrodes for each TFT, 26 and 27 are electrically connected through the contact hole of the interlayer insulating film 4.
[0095]
Further, in the source / drain regions 31 and 32 of the second conductivity type driving circuit TFT 30 ′, the portion adjacent to the offset regions 311 ′ and 321 ′ has an impurity concentration of about 5 × 10 × 10.¹⁹cm^-3To about 5 × 10²⁰cm^-3The second conductivity type high-concentration source / drain regions 312 and 322 of the same level, and the source / drain electrodes 36 and 37 such as signal lines and pixel electrodes are contact holes of the interlayer insulating film 4 with respect to these high-concentration regions. It is electrically connected via.
[0096]
In the present invention, the second conductivity type TFT has the same conductivity (P-type conductivity) in the source / drain region, the offset region, and the channel region. The channel region is opposite in conductivity (P-type conductivity) to the source / drain region and the LDD region (N-type conductivity). On the contrary, in the second conductivity type TFT, the offset region and the channel region have opposite conductivity (N-type conductivity) with respect to the source / drain region (P-type conductivity), and the first conductivity type. The type TFT may have the same conductivity (N-type conductivity) in the source / drain region, the LDD region, and the channel region. However, in this case, when the transistor is turned on, the channel of the second conductivity type TFT (inverted and second conductivity / P type conductivity), the offset region, and the source / drain region (first conductivity / N type conductivity) A weak PN junction can be formed between them and the off current is limited.
[0097]
(TFT on / off current characteristics)
In the on / off current characteristics of the TFT configured as described above, in any TFT, the portion facing the end of the gate electrode 15, 25, 35 is a low-concentration region (first-concentration type low-concentration source / drain region). 111, 121, 211, 221 or offset regions 311 ′, 321 ′), the electric field strength at the drain end is relaxed. Therefore, FIG. 3 shows the drain current-gate voltage characteristics of the first conductivity type TFT having the LDD structure (first conductivity type pixel TFT 10 and first conductivity type driving circuit TFT 20) by a solid line L3. As compared, the drain current-gate voltage characteristics of the second conductivity type TFT having the offset gate structure (second conductivity type driving circuit TFT 30 ′) are indicated by a dotted line L 4 ′. The off current of the TFT is extremely small.
[0098]
FIG. 31A shows the withstand voltage characteristics of the first conductivity type TFT (the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20) of the LDD structure by a solid line L21. As shown by the solid line L22 in FIG. 31 (b), the withstand voltage characteristic of the second conductivity type TFT having the LDD structure is higher in the withstand voltage than the TFT having the self-aligned structure. In addition to the fact that the channel length can be shortened, the withstand voltage characteristics of the offset gate structure TFT (second conductivity type TFT 30 'for the drive circuit) are more than the withstand voltage characteristics of the LDD structure TFT. It is even better. Accordingly, the second conductivity type driving circuit TFT 30 ′ also has a significantly higher withstand voltage than the self-aligned TFT, so that the channel length can be further shortened. Therefore, high speed operation can be realized by reducing the transistor capacity.
[0099]
In this example, the first conductivity type is the first conductivity type, and the second conductivity type is the second conductivity type. That is, the pixel TFT may be configured of the second conductivity type. Further, the impurity concentration in the offset regions 311 ′ and 321 ′ and the channel region 33 of the second conductivity type driving circuit TFT 30 ′ is about 1 × 10 5.¹⁶cm^-3To about 5 × 10¹⁷cm^-3However, the concentration should be set to an optimum value according to the specifications of the active matrix substrate 1 and the channel length dimension, and is not limited to the above numerical values.
[0100]
(TFT manufacturing method)
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.
[0101]
As shown in FIG. 4A, among the surfaces of the insulating substrate 2 such as a quartz substrate, the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit. Low concentration second conductivity type silicon films 10a, 20a, 30a and gate insulating films 14, 24, 34 are formed in the formation region of the TFT 30 '.
[0102]
For this purpose, an intrinsic polysilicon film is first formed on the surface of an insulating substrate 2 such as a glass substrate or a quartz substrate by using an LPCVD method or a plasma CVD method, and then the polysilicon film is patterned by a photolithography method. These are made into island-shaped silicon films 10a, 20a, 30a (silicon film forming step). The polysilicon film may be formed by growing crystal grains by laser annealing or solid phase growth after forming an amorphous silicon film.
[0103]
Next, the island-shaped silicon films 10a, 20a, and 30a are formed to have a thickness of about 200 angstroms to about 1500 angstroms by thermal oxidation, TEOS-CVD, LPCVD, plasma CVD, HTO, or the like. As an example, gate insulating films 14, 24, and 34 made of a silicon oxide film of about 1200 angstroms are formed (gate insulating film forming step).
[0104]
Thereafter, for example, the thickness of the gate insulating films 14, 24, 34 is about 1200 angstroms and 1 × 10 5.¹⁷cm^-3In the case of about an impurity, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions (second conductivity type impurities) at a dose of (channel doping step / low concentration second conductivity type impurity introduction step / first impurity introduction step).
[0105]
As a result, the island-like silicon films 10a, 20a, and 30a are all low-concentration second conductivity type silicon films 10a, 20a, and 30a.
[0106]
Next, as shown in FIG. 4B, gate electrodes 15, 25, and 35 made of doped silicon, silicide film, metal thin film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34 (gates). Electrode forming step).
[0107]
Next, the formation region of the second conductivity type pixel TFT 30 ′ is covered with a resist mask 61, while the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 is open. (First mask formation process)
In this state, a dose of about 1.0 × 10 13 cm −2 of first conductivity type impurities, for example, phosphorus ions, is formed on the formation regions of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20. The impurity concentration is about 1.0 × 10 5 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low-concentration source / drain regions 11, 12, 21, and 22 are formed (low-concentration first conductivity type impurity introduction step / second impurity introduction step). The portions where impurities are not introduced become channel regions 13 and 23.
[0108]
Thereafter, the resist mask 61 is removed.
[0109]
Next, as shown in FIG. 4C, in addition to the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20, the gate electrode 35 of the second conductivity type drive circuit TFT 30 'is formed. A resist mask 62 that covers a wider area is formed (second mask formation step). Here, the distance between the end portion of the resist mask 62 and the end portion of the gate electrode 35 is suitably about 0.5 μm to 2.0 μm.
[0110]
In this state, impurities of the second conductivity type, such as boron ions, are added at 1.0 × 10¹⁵cm^-2Are implanted at a dose of (high concentration second conductivity type impurity introduction step / third impurity introduction step).
[0111]
As a result, the low conductivity second conductivity type silicon film 30a has a second conductivity type impurity concentration of 1.0 × 10 6.²⁰cm^-3High concentration source / drain regions 312, 322 of the second conductivity type are formed. On the other hand, in the low-concentration second conductivity type silicon film 30a, the portion covered with the resist mask 62 has the second conductivity type impurity concentration of about 1.0 × 10.¹⁷cm^-3Offset regions 311 'and 321'. Of course, the channel region 33 has a second conductivity type impurity concentration of about 1.0 × 10 10.¹⁷cm^-3The low-concentration second conductivity type region remains.
[0112]
In this manner, the second conductivity type driving circuit TFT 30 'is formed. Thereafter, the resist mask 62 is removed.
[0113]
Next, as shown in FIG. 4D, in addition to the formation region of the second conductivity type driving circuit TFT 30 ′, the gates of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. A resist mask 63 that covers the electrodes 15 and 25 so as to be wider is formed (third mask formation step). Also here, the distance between the end of the resist mask 63 and the ends of the gate electrodes 15 and 25 is suitably about 0.5 μm to 2.0 μm.
[0114]
In this state, impurities of the first conductivity type, for example, phosphorus ions are added at 1.0 × 10¹⁵cm^-2Are implanted at a high dose (high-concentration first conductivity type impurity introduction step / fourth impurity introduction step).
[0115]
As a result, in the low concentration source / drain regions 11, 12, 21, 22, the first conductivity type impurity concentration is 1.0 × 10 6.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 of the first conductivity type are formed. On the other hand, in the low concentration source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 63 has the first conductivity type impurity concentration of about 1.0 × 10 5 as it is.¹⁸cm^-3The first conductivity type low-concentration source / drain regions 111, 121, 211, and 222 are formed. Of course, the channel regions 13 and 23 have a second conductivity type impurity concentration of about 1.0 × 10 10.¹⁷cm^-3The low-concentration second conductivity type region remains.
[0116]
In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 63 is removed.
[0117]
Thereafter, as shown in FIG. 1, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, 37, the source / drain region and the channel region of the TFT having the CMOS structure can be formed by three mask formation steps for forming the resist masks 61 to 63 and four impurity introduction steps. The active matrix substrate 1 can be manufactured.
[0118]
As described above, in the manufacturing method of the active matrix substrate 1 of this example, in the second conductivity type driving circuit TFT 30 ′, when the portion facing the gate electrode 35 is set to the low concentration region, the LDD structure is not used. The offset gate structure has the same conductivity type and the same concentration as the channel. Therefore, compared with the conventional manufacturing method described with reference to FIGS. 33A to 33E, both the mask formation step and the impurity introduction step are less each time. That is, in this example, since the low concentration second conductivity type impurity introduction step is performed simultaneously with the channel doping for the channel region of each TFT before the gate electrode formation step, all TFTs are manufactured with an LDD structure. In addition, the impurity introduction step can be reduced by one time. Also, the low concentration second conductivity type impurity introduction step is performed at the same time as the channel doping, and in the low concentration second conductivity type region formed in this step, the region to be the source / drain region of the first conductivity type is A higher concentration of impurities of the first conductivity type is introduced. Therefore, since the mask is not required in the low concentration second conductivity type impurity introducing step, the mask forming step can be reduced by one time as compared with the case where all TFTs are manufactured with the LDD structure. Therefore, the electrical characteristics of the TFTs in the pixel region and the drive circuit portion can be improved with a minimum number of manufacturing steps.
[0119]
(Another manufacturing method of TFT)
The active matrix substrate 1 of this example can also be manufactured by the method described below.
[0120]
As shown in FIG. 5A, out of the surface of the insulating substrate 2 such as a glass substrate or a quartz substrate, the pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 ′ are provided. Low concentration second conductivity type silicon films 10a, 20a, 30a and gate insulating films 14, 24, 34 are formed in the formation region.
[0121]
For this purpose, an intrinsic polysilicon film is first formed on the surface of an insulating substrate 2 such as a quartz substrate by using LPCVD or plasma CVD, and then the polysilicon film is patterned by photolithography, The island-shaped silicon films 10a, 20a, and 30a are formed (silicon film forming step).
[0122]
Next, the island-shaped silicon films 10a, 20a, and 30a are formed by a thermal oxidation method, a TEOS-CVD method, an LPCVD method, a plasma CVD method, an HTO method, etc., to a thickness of about 200 angstroms to about 1500 angstroms. As an example, gate insulating films 14, 24, and 34 made of a silicon oxide film of about 1200 angstroms are formed (gate insulating film forming step).
[0123]
After that, 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / low concentration second conductivity type impurity introduction step / first impurity introduction step).
[0124]
As a result, the island-like silicon films 10a, 20a, and 30a are all low-concentration second conductivity type silicon films 10a, 20a, and 30a.
[0125]
Next, as shown in FIG. 5B, gate electrodes 15, 25, and 35 made of doped silicon, silicide films, metal thin films, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34 (gates). Electrode forming step).
[0126]
The above process is the same as the manufacturing method described with reference to FIGS.
[0127]
Next, in addition to the formation region of the second conductivity type drive circuit TFT 30 ′, a resist that covers the gate electrodes 15 and 25 of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 more widely. A mask 71 is formed (first mask formation step). Again, the distance between the end portion of the resist mask 71 and the end portions of the gate electrodes 15 and 25 is suitably about 0.5 μm to 2.0 μm.
[0128]
In this state, impurities of the first conductivity type, for example, phosphorus ions are added at 1.0 × 10¹⁵cm^-2Are implanted at a high dose (high concentration first conductivity type impurity introduction step / second impurity introduction step).
[0129]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have a first conductivity type impurity concentration of 1.0 × 10 6.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 of the first conductivity type are formed. On the other hand, the portion of the low-concentration second conductivity type silicon film 10a, 20a covered with the resist mask 71 has a second conductivity type impurity concentration of about 1.0 × 10.¹⁷cm^-3The low-concentration second conductivity type region remains.
[0130]
Thereafter, the resist mask 71 is removed.
[0131]
Next, as shown in FIG. 5C, in addition to the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20, the gate electrode 35 of the second conductivity type drive circuit TFT 30 'is formed. A resist mask 72 that covers a wider area is formed (second mask formation step). Here, the distance between the end of the resist mask 72 and the end of the gate electrode 35 is suitably about 0.5 μm to 2.0 μm.
[0132]
In this state, for example, boron ions are 1.0 × 10 6.¹⁵cm^-2Are implanted at a dose of (high concentration second conductivity type impurity introduction step / third impurity introduction step). As a result, the low conductivity second conductivity type silicon film 30a has a second conductivity type impurity concentration of 1.0 × 10 6.²⁰cm^-3High concentration source / drain regions 312, 322 of the second conductivity type are formed. On the other hand, the portion of the low-concentration second conductivity type silicon film 30a covered with the resist mask 72 has the second conductivity type impurity concentration of about 1.0 × 10 5 as it is.¹⁷cm^-3Offset regions 311 'and 321'. Of course, the channel region 33 has a second conductivity type impurity concentration of about 1.0 × 10 10.¹⁷cm^-3The low-concentration second conductivity type region remains.
[0133]
In this manner, the second conductivity type driving circuit TFT 30 'is formed. Thereafter, the resist mask 72 is removed.
[0134]
Next, the formation region of the second conductivity type pixel TFT 30 ′ is covered with a resist mask 73, while the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 is open. (Third mask formation step). In this state, for example, about 1.0 × 10 6 of phosphorus ions are formed on the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20.¹³cm^-2Are implanted at a low dose (low concentration first conductivity type impurity introduction step / fourth impurity introduction step).
[0135]
As a result, the source / drain regions 10 and 20 have a first conductivity type impurity concentration of about 1.0 × 10 10 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3The first conductivity type low concentration source / drain regions 111, 121, 211, and 221 are formed. The portions where impurities are not introduced become channel regions 13 and 23.
[0136]
In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 73 is removed.
[0137]
Thereafter, as shown in FIG. 1, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, 37, the source / drain region and the channel region of the TFT having the CMOS structure can be formed by three mask formation steps for forming the resist masks 71 to 73 and four impurity introduction steps. The active matrix substrate 1 can be manufactured.
[0138]
Even in such a manufacturing method, in making the portion facing the gate electrode 35 in the second conductivity type TFT 30 'for the second conductivity type, not the LDD structure but the same conductivity type and the same concentration as the channel. It has an offset gate structure. Therefore, compared with the conventional manufacturing method described with reference to FIGS. 33A to 33E, both the mask formation step and the impurity introduction step are less each time. Therefore, the electrical characteristics of the TFTs in the pixel region and the drive circuit portion can be improved with a minimum number of manufacturing steps.
[0139]
[Example 2]
This example relates to an invention that improves the on-current balance between the first conductivity type TFT and the second conductivity type TFT by optimizing the channel doping conditions for each TFT. Since the basic structure and the manufacturing method are substantially the same as those of the first embodiment, the basic structure is briefly described with reference to FIG. 1 and the description of the manufacturing method is omitted.
[0140]
Also in this example, as shown in FIG. 1, the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are connected between the source / drain regions 11, 12, 21, and 22. The channel regions 13 and 23 are formed of low-concentration second conductivity type impurities (in this example, boron (B), aluminum (Al , Acceptor impurities such as gallium (Ga) and indium (In). The first-conductivity-type pixel TFT 10 and the first-conductivity-type driver circuit TFT 20 face the end portions of the gate electrodes 15, 25 through the gate insulating films 14, 24 through the first conductivity-type low concentration. Source / drain regions 111, 121, 121, 122 and first-conductivity type high concentration source / drain regions 112, 122, 212, 222 in which source / drain electrodes 16, 17, 26, 27 are electrically connected, Have. In this example, since the N-type TFT is used as the first conductivity type TFT, the first conductivity type impurities contained in the source / drain regions are phosphorus (P), arsenic (N) As), antimony (Sb), and the like.
[0141]
On the other hand, the second conductivity type driving circuit TFT 30 ′ includes a channel region 33 containing a low concentration second conductivity type impurity and a gate insulating film 34 with respect to the end of the gate electrode 35 with the same impurity concentration as the channel region. And high concentration source / drain regions 312 and 322 of the second conductivity type to which the source / drain electrodes 36 and 37 are electrically connected.
[0142]
In the active matrix substrate 1 configured in this way, the channel regions 13, 23, and 33 are all channel-doped with low-concentration boron ions and are low-concentration second conductivity type regions, as in the first embodiment. The impurity concentration is set so as to satisfy the conditions described below, for example, about 5 × 10¹⁶cm^-3~ 1x10¹⁸cm^-3It is. In general, the second conductive type drive circuit TFT 30 ′ having the offset structure tends to have a slightly smaller on-current than the first conductive type drive circuit TFT 20 having the LDD structure. The main reason is the difference in specific resistance between the offset structure and the LDD structure. Furthermore, when the second conductivity type is the second conductivity type and the first conductivity type is the first conductivity type, the hole conductivity is further increased. This is because the mobility is smaller than the mobility of electrons.
[0143]
Therefore, in this example, by setting a larger amount of channel-doped impurities, the second conductivity type (which is the second conductivity type) drive circuit TFT 30 ′ is set to a weak depletion mode, and the first conductivity type is set. The driving circuit TFT 20 (which is of the first conductivity type) is set to a weak enhancement mode. As a result, the offset regions 311 ′ and 312 ′ of the second conductivity type driving circuit TFT 30 ′ are substantially LDD regions having a low resistance. Moreover, in the ON state (for example, in the second conductivity type driving circuit TFT 30 ′, the source-drain voltage V_DS= -5V, gate voltage V_GS= −10 V, in the first conductivity type driving circuit TFT 20, the source-drain voltage V_DS= + 5V, gate voltage V_GS= 10V), the on-current level can be made uniform between the two conductivity type TFTs.
[0144]
That is, as shown in FIG. 6, the drain current-gate voltage characteristics of the first conductivity type TFT (first conductivity type pixel TFT 10 and first conductivity type drive circuit TFT 20) are indicated by a solid line L5, The drain current-gate voltage characteristic of the conductive type TFT (second conductive type driving circuit TFT 30 ') is indicated by a dotted line L6, and the source / drain of the first conductive type TFT (first conductive type driving circuit TFT 20) is shown. The voltage is VDS1, the gate voltage is VGS1, the source / drain current is IDS1, and the source / drain voltage of the second conductivity type TFT (second conductivity type drive circuit TFT 30 ') is V_DS2 , The gate voltage is V_GS2 Source / drain current I_DS2 When | V_DS1 | = | V_DS2 |, V_GS1 = V_GS2 = 0 under the condition_DS2> I_DS1 The second conductivity type in the offset regions 311 ′ and 321 ′ of the second conductivity type TFT (second conductivity type drive circuit TFT 30 ′) and the channel regions 13, 23 and 33 of the TFTs. Impurity concentration is set.
[0145]
In other words, | V_DS1 | = | V_DS2 The source / drain current I of the first conductivity type TFT under the condition |_DS1 And a source / drain current I of the second conductivity type TFT._DS2 Point of intersection R (V_GS1 = V_GS2At I_DS1 = I_DS2 ) Corresponds to the source / drain current I in the first conductivity type driving circuit TFT 20._DS1 Of the gate voltage region corresponding to the ON region side of the second-conductivity-type driving circuit TFT 30 '._DS2 Gate voltage region corresponding to the off region side), that is, in the positive gate voltage region.
[0146]
For reference, FIG. 6 shows drain currents of the first conductivity type TFTs (first conductivity type pixel TFT 10 and first conductivity type drive circuit TFT 20) according to the first embodiment shown in FIG. The gate voltage characteristic is indicated by a one-dot chain line L3, and the drain current-gate voltage characteristic of the second conductivity type TFT (second conductivity type driving circuit TFT 30 ') is indicated by the one-dot chain line L4' in Example 1.
[0147]
In this way, in this example, by setting the offset regions 311 'and 312' of the second conductivity type driving circuit TFT 30 'to be LDD regions having a substantially small resistance, the parasitic resistance caused by this portion is reduced. There is. When comparing the offset region and the LDD region, the LDD region generally has a smaller resistance value. In this example, the second conductivity type driving circuit TFT 30 ′ having the offset structure is weakly depleted. The mode and the first conductivity type driving circuit TFT 20 with the LDD structure is in a weak enhancement mode, so that the gate bias value in the ON state of the second conductivity type driving circuit TFT 30 ′ with the offset structure Can be made larger than the gate bias value in the ON state of the TFT 20 for the drive circuit of the first conductivity type having the LDD structure. In the example shown in FIG. 6, for example, the position of the intersection R is V_GS= + 2V, ON state | V_GS| = 10V. In this case, the gate bias value in the ON state of the second conductivity type driving circuit TFT 30 'having the offset structure corresponds to about -12V in the characteristic represented by the alternate long and short dash line L4', and the first conductivity type having the LDD structure. Since the gate bias value in the on state of the driving circuit TFT 20 corresponds to about +8 V in the characteristics represented by the alternate long and short dash line L3, it is possible to balance the on-current. In this method, it is also possible to equalize the transistor capacitance between the second conductivity type driving circuit TFT 30 ′ having the offset structure and the first conductivity type driving circuit TFT 20 having the LDD structure. . That is, the balance of on-current between the second conductivity type driving circuit TFT 30 'and the first conductivity type driving circuit TFT 20 is determined by channel doping (doping amount in the offset regions 311' and 321 '). Therefore, by making the channel length / channel width equal between the two TFTs, it is possible to ensure the balance of the transistor capacitances between the two TFTs. Therefore, since the transistor capacitance is equivalent and the on-current is equivalent, a CMOS circuit that operates stably at high speed can be obtained.
[0148]
Since the manufacturing method of the TFT having such a configuration is substantially the same as that of the first embodiment, the description of the manufacturing method is omitted, but the amount of impurities introduced into each region is optimum corresponding to the channel doping amount. Set to a value. The optimum channel doping amount varies depending on the quality of the gate insulating film and the quality of the base protective film (protective film between the semiconductor layer and the substrate).
[0149]
[Modification of Embodiments 1 and 2]
As in this example, if the method of forming the offset regions 311 ′ and 321 ′ so that the portion facing the gate electrode 35 is a low concentration region, the gate insulating film 14 is formed on the silicon films 10a, 20a, and 30a. , 24, and 34, instead of implanting boron ions (low-concentration second-conductivity type impurities) in the low-concentration second-conductivity-type silicon film forming step, the silicon films 10a, 20a, and 30a are formed. Before forming the gate insulating films 14, 24, 34, boron ions may be implanted in the low-concentration second conductivity type silicon film forming step, and then the gate insulating films 14, 24, 34 may be formed. .
[0150]
In addition, after forming the intrinsic silicon films 10a, 20a, and 30a, a mixed gas of B2H6 and SiH6 is used instead of the method of implanting low concentration second conductivity type impurities in the low concentration second conductivity type silicon film forming step. A silicon film doped with a low concentration of boron (doped silicon film / doped semiconductor film) is formed as a low-concentration second conductivity type silicon film 10a, 20a, 30a by a CVD method, and then a gate insulating film 14 is formed thereon. 24, 34 may be formed, and then the steps shown in FIGS. 4B to 4D or the steps shown in FIGS. 5B to 5D may be performed.
[0151]
Further, in any case, in the manufacturing method of the active matrix substrate of this example, at least the low concentration second conductivity type impurity introduction step, the gate electrode formation step, the low concentration first conductivity type impurity introduction step, the high concentration first conductivity In this process, the low-concentration second conductivity type impurity introduction step is performed before the gate electrode formation step. If the gate electrode is used as a mask after the low-concentration first conductivity type impurity introduction step is performed after the gate electrode formation step is performed simultaneously with channel doping for the channel region of each TFT, conditions A to conditions shown in Table 1 are satisfied. Any process sequence of T may be used.
[0152]
[Table 1]

[0153]
That is, Table 1 shows the low-concentration second conductivity type impurity introduction step as C / D (P^-), The gate electrode forming step is Gate, and the low concentration first conductivity type impurity introducing step is N^- , High concentration first conductivity type impurity introduction step N⁺ And high concentration second conductivity type impurity introduction step P⁺ The condition A is the process order described with reference to FIG. 4, and the condition C is the process order described with reference to FIG.
[0154]
The low-concentration second conductivity type impurity introduction step may be created by a step of forming a doped semiconductor film containing the low-concentration second conductivity type impurity. For example, when boron is doped, the CVD furnace uses monosilane (SiH_Four ) And disilane (Si₂ H₆ ) And diborane (B₂ H₆ ). When depositing these doped semiconductor films by the LPCPD method, the concentration of the additive such as diborane is preferably about 0.1 ppm to 100 ppm, and hydrogen, helium, and nitrogen are suitable as the dilution gas. On the other hand, when depositing by PECVD, the concentration is the same as before, but helium, argon, etc. are suitable as the dilution gas. Thus, after the doped semiconductor film is deposited, patterning may be performed, and a gate insulating film may be formed on the surface of the semiconductor film.
[0155]
As an impurity introduction method, for example, a method of implanting all ions generated from the dopant gas without mass separation, a so-called ion doping method may be used. In this method, for example, when implanting the first conductivity type impurity at a high concentration, PH_Three Using a mixed gas comprising about 1% to about 10% and the balance being hydrogen gas or helium gas, all ions generated from this mixed gas are implanted without mass separation. On the other hand, when the impurity of the first conductivity type is implanted at a low concentration, PH_Three About 0.01% to about 1%, and the rest of the ions generated from the mixed gas composed of hydrogen gas or the like are implanted without mass separation, and then the ions generated from the pure hydrogen gas without mass separation. It is preferable to terminate the asymmetric bond in the silicon film by implanting. In addition to the ion implantation method or the ion doping method, a plasma doping method, a laser doping method, or the like may be used as the impurity introduction method.
[0156]
In the active matrix substrate 1 of this example, the impurity concentrations of the first conductivity type low concentration source / drain regions 111, 121, 211, and 221 of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 are set. About 1.0 × 10¹⁸cm^-3And the impurity concentration of the high-concentration source / drain regions 112, 122, 212, and 222 of the first conductivity type is about 1.0 × 10²⁰cm^-3However, such a density is of a property that should be set to an optimum value according to the specifications of the active matrix substrate 1, and is not limited to the above numerical values. Furthermore, the mask material is not limited to a resist mask.
[0157]
[Example 3]
(Configuration of active matrix substrate)
FIG. 7 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example, and FIG. 8 is a block diagram schematically showing the configuration of the liquid crystal display device.
[0158]
7, in the active matrix substrate with a built-in drive circuit of the liquid crystal display device of this example, the drive circuit portion, the pixel region, and the storage capacitor forming region in the pixel region are arranged from the left side region to the right side region. As schematically shown, a second conductivity type driving circuit TFT 30, a first conductivity type driving circuit TFT 20, a first conductivity type pixel TFT 10, and a storage capacitor 40 are formed on the same insulating substrate 2. It has been done.
[0159]
In this example, as shown in FIG. 8, a storage capacitor 40 is formed in the pixel region between the scanning line 91 in the previous stage, and the storage capacitor 40 has a charge holding characteristic in a liquid crystal cell (liquid crystal capacitor 94). It has a function to enhance. The storage capacitor 40 is obtained by making the silicon film S2 formed simultaneously with the silicon film S1 for forming the pixel TFT 10 conductive to be a lower electrode part 40c (first electrode part), and this lower electrode part The upper layer side electrode portion 45 (second electrode portion) protruding from the preceding scanning line 91 overlaps 40c. Note that the storage capacitor 40 is formed between the scanning line 91 in the previous stage in each pixel region, but may be formed between the storage capacitor 40 and a dedicated capacitor line.
[0160]
Referring again to FIG. 7, the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 all have source / drain regions 11, 12, Channel regions 13, 23 and 33 for forming a channel are provided between 21, 22, 31 and 32. Since these channel regions 13, 23 and 33 are channel-doped with low-concentration boron ions, the impurity concentration is about 1 × 10¹⁷cm^-3It is a low-concentration second conductivity type region. Therefore, the threshold voltage (Vth) of the first conductivity type driving circuit TFT 20 and the second conductivity type driving circuit TFT 30 is set to a predetermined value. In general, since the mobility of holes is smaller than the mobility of electrons, conventionally, the on-current of the second conductivity type driving circuit TFT is larger than the on-current of the first conductivity type driving circuit TFT. Tend to be extremely small. In this example, this problem can be almost eliminated by adjusting Vth. Therefore, the active matrix substrate 1 of this example has a good balance of on-current between TFTs constituting the CMOS circuit.
[0161]
The first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30 are formed on the surface of the channel regions 13, 23, 33 with respect to the gate insulating film 14, Gate electrodes 15, 25, and 35 are opposed to each other through 24 and 34 (a silicon oxide film having a thickness of about 1200 angstroms).
[0162]
In the active matrix substrate 1 configured in this manner, the source / drain regions 11, 12, 21, 22, 31, and 32 are formed with gate insulating films 14, 24, 34, low concentration source / drain regions 111, 121, 211, 221, 311 and 321 are provided in a portion facing each other through 34, and any of the TFTs has an LDD structure.
[0163]
Of the source / drain regions 11, 12, 21, 22, 31, and 32 of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the second conductivity type drive circuit TFT 30, low In regions other than the concentration source / drain regions 111, 121, 211, 221, 311, 321, the impurity concentration is about 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, 222, 312, 322. Source / drain electrodes 16, 17, 26, 27, 36, 37 such as signal lines and pixel electrodes for each TFT are electrically connected to these high concentration regions through contact holes in the interlayer insulating film 4. It is.
[0164]
(TFT on / off leakage current characteristics)
The TFT configured in this manner has a low concentration region (low concentration source / drain regions 111, 121, 211, and 221) at the ends of the gate electrodes 15, 25, and 35. The electric field strength is in a relaxed state. Therefore, FIG. 32 shows the drain current-gate voltage characteristics of the first conductivity type TFT (the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20) by a solid line L3. As shown by the dotted line L4 in the drain current-gate voltage characteristics of the TFT (second conductivity type driving circuit TFT 30), the off-leak current of the TFT is extremely small.
[0165]
FIG. 31A shows the withstand voltage characteristics of the first conductivity type TFT (the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20) of the LDD structure by a solid line L21. As shown by the solid line L22 in FIG. 31 (b), the withstand voltage characteristic of the second conductivity type TFT having the LDD structure is indicated by a solid line L22. Since the voltage is high, the channel length can be shortened.
[0166]
(TFT manufacturing method)
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.
[0167]
First, in order to adjust the Vth of the TFT, impurities are introduced into the semiconductor film at a low concentration. That is, as shown in FIG. 9A, among the surface of the insulating substrate 2 such as a quartz substrate, the pixel TFT 10, the first conductivity type drive circuit TFT 20, the second conductivity type drive circuit TFT 30, and the storage capacitor For example, in the formation region of 40, the impurity concentration is 1 × 10¹⁷cm^-3The low concentration second conductivity type silicon films 10a, 20a, 30a, 40a, the gate insulating films 14, 24, 34, and the dielectric film 44 are formed simultaneously (low concentration second conductivity type silicon film forming step).
[0168]
For this purpose, an intrinsic polysilicon film is formed on the surface of the insulating substrate 2 using the LPCVD method or the plasma CVD method, and then the polysilicon film is patterned by a photolithography method to form the island-like silicon film 10a. , 20a, 30a, 40a (silicon film forming step).
[0169]
The polysilicon film may be formed by growing crystal grains by laser annealing or solid phase growth after forming an amorphous silicon film. Next, a silicon oxide film having a thickness of about 1200 angstroms is formed on the island-like silicon films 10a, 20a, 30a, and 40a by thermal oxidation, TEOS-CVD, LPCVD, plasma CVD, HTO, or the like. The gate insulating films 14, 24, 34 and the dielectric film 44 are simultaneously formed (gate insulating film forming step).
[0170]
After that, about 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions (second conductivity type impurities / second conductivity type impurities) at a dose of (channel doping step / first impurity introduction step). As a result, the silicon films 10a, 20a, 30a, and 40a have an impurity concentration of about 1 × 10.¹⁷cm^-3Low-concentration second conductivity type silicon films 10a, 20a, 30a and 40a.
[0171]
Next, as shown in FIG. 9B, a resist mask 101 is formed which covers the formation region of the second conductivity type driving circuit TFT 30 and covers the formation regions of the gate electrodes 15 and 25 slightly wider (see FIG. 9B). First mask formation step).
[0172]
Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are about 1 × 10 5.¹⁴cm^-2(2nd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0173]
As a result, in the low-concentration second conductivity type silicon films 10a and 20a, the region where the phosphorus ions are implanted has the conductivity type inverted and the impurity concentration is about 1 × 10.¹⁹cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, 22. The low-concentration second-conductivity-type silicon film 40a becomes a low-concentration first-conductivity-type lower-layer-side electrode portion 40c (first electrode portion) whose conductivity type is inverted and the impurity concentration is about 1 × 1019 cm−3. . Further, the portions where impurities are not introduced become channel regions 13 and 23. Thereafter, the resist mask 101 is removed.
[0174]
Next, as shown in FIG. 9C, gate electrodes 15, 25, and 35 made of doped silicon, silicide film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34. At the same time, an upper electrode portion 45 (second electrode portion) is formed on the surface of the dielectric film 44 (gate electrode forming step). The upper layer side electrode portion 45 may be a part of the previous signal line. In this way, the storage capacitor 40 is formed in which the lower layer side electrode part 40 c and the upper layer side electrode part 45 are opposed to each other with the dielectric film 44 interposed therebetween.
[0175]
Next, a resist mask 102 is formed to cover the formation region of the first conductivity type pixel TFT 10, the formation region of the first conductivity type drive circuit TFT 20, and the storage capacitor 40 (second mask formation step).
[0176]
Subsequently, boron ions are about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0177]
As a result, the low-concentration second conductivity type silicon film 30 a has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. A portion where no impurity is introduced becomes a channel region 33. Thereafter, the resist mask 102 is removed.
[0178]
Next, as shown in FIG. 9D, the formation region of the first conductivity type pixel TFT 10, the formation region of the first conductivity type drive circuit TFT 20, and the storage capacitor 40 are covered, and the gate electrode 35 is covered. A resist mask 103 that covers a wider area is formed (third mask formation step).
[0179]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0180]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Further, in the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 103 has an impurity concentration of about 1.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0181]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 103 is removed.
[0182]
Next, as shown in FIG. 9E, in addition to the second conductivity type driving circuit TFT 30, a resist mask 104 that covers the gate electrodes 15 and 25 is formed (fourth mask forming step). .
[0183]
Subsequently, phosphorus ion is 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0184]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 221, 222 are formed. Further, in the low concentration first conductivity type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 104 has an impurity concentration of about 1 × 10 as it is.¹⁹cm^-3Low concentration source / drain regions 111, 121, 211, and 221.
[0185]
In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 104 is removed.
[0186]
Thereafter, as shown in FIG. 7, after the interlayer insulating film 4 is formed, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 101 to 104 and five impurity introduction steps.
[0187]
Thus, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 9B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A low-concentration first conductivity type impurity introduction step for forming the drain regions 111, 121, 211, and 221 is performed, and this step is used to form the lower layer side electrode portion 40c. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps one by one as compared with the conventional manufacturing method. Therefore, the electrical characteristics of each TFT can be improved while forming the TFT and the capacitor (retention capacitor 40) with a small number of manufacturing steps.
[0188]
In Tables 2 to 4, the channel doping process is “C / D” and the low concentration first conductivity type impurity introduction process is “N”.^- "High concentration first conductivity type impurity introduction process" N⁺ "Low concentration second conductivity type impurity introduction process" P^- "High concentration second conductivity type impurity introduction process" P⁺ As shown in FIG. 9C, the low concentration second conductivity type impurity introduction step shown in FIG. 9C and the high concentration second conductivity type shown in FIG. Prior to forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, such as changing the order between the impurity introduction step and the high concentration first conductivity type impurity introduction step shown in FIG. As long as the low-concentration first conductivity type impurity introduction step for forming the concentration source / drain regions 111, 121, 211, and 221 is performed and the lower layer side electrode portion 40c is formed by using this step, It may be a process order.
[0189]
[Table 2]

[0190]
[Table 3]

[0191]
[Table 4]

[0192]
[Example 4]
The structure of the active matrix substrate of this example will be described with reference to FIG.
[0193]
In FIG. 7, the feature of the active matrix substrate 1 of this example is that the first conductivity type pixel TFT 10 and the first conductivity type drive circuit are manufactured in the same number of steps as the manufacturing method according to the third embodiment. The low concentration source / drain regions 111, 121, 211, and 221 of the TFT 20 for use are lower in concentration than the lower layer side electrode portion 40 c of the storage capacitor 40.
[0194]
That is, the lower electrode portion 40c of the storage capacitor 40 is a low-concentration first conductivity type region having an impurity concentration of about 1 × 10 19 cm −3, as in the third embodiment. The low-concentration source / drain regions 111, 121, 211, and 221 of the one-conductivity-type driving circuit TFT 20 have the same amount of phosphorus ions (impurity concentration of about 1 × 10 6 as the lower electrode portion 40 c of the storage capacitor 40¹⁹cm^-3The amount of boron ions (impurity concentration is about 1.1 × 10 5) equivalent to the low concentration regions 311 and 321 of the second conductivity type driving circuit TFT 30.¹⁸cm^-3In the first conductivity type region with a low concentration. Therefore, the impurity concentration of the low concentration source / drain regions 111, 121, 211, and 221 is about 9 × 10.¹⁸cm^-3It is.
[0195]
The active matrix substrate 1 having such a configuration can be manufactured by a manufacturing method described below. In addition, since the manufacturing method demonstrated below has a process in common with Example 3, this process is demonstrated easily.
[0196]
First, as shown in FIG. 10A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0197]
Next, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions at a dose of (channel doping step / first impurity introduction step).
[0198]
Next, as shown in FIG. 10B, the formation area of the second conductivity type driving circuit TFT 30 is covered, and the gate electrodes of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are covered. A resist mask 201 is formed to cover the formation regions 15 and 25 slightly wider (first mask formation step).
[0199]
Subsequently, phosphorus ion is about 1 × 10¹⁴cm^-2(2nd impurity introduction step / low-concentration first conductivity type impurity introduction step), and the impurity concentration is about 1 × 10.¹⁹cm^-3The low-concentration first conductivity type source / drain regions 11, 12, 21, 22 and the low-concentration first conductivity type lower electrode portion 40c are formed.
[0200]
Next, as shown in FIG. 10C, the gate electrodes 15, 25 and 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0201]
Each process described above is the same as the manufacturing method according to the third embodiment.
[0202]
Next, a resist mask 202 that covers the formation region of the storage capacitor 40 and covers the gate electrodes 15 and 25 slightly wider is formed similarly to the resist mask 201 (second mask formation step).
[0203]
Subsequently, boron ions are about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0204]
As a result, the silicon film 30 a has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed.
[0205]
On the other hand, the low-concentration first conductivity type source / drain regions 11, 12, 21, and 22 are substantially reduced in concentration by boron ions implanted therein, and the low-concentration first conductivity type source / drain regions 11, The impurity concentration of 12, 11, 12 is about 9 × 10¹⁸cm^-3It becomes. Thereafter, the resist mask 202 is removed.
[0206]
Thereafter, as in the third embodiment, as shown in FIG. 10D, the formation region of the first conductivity type pixel TFT 10, the formation region of the first conductivity type driving circuit TFT 20, and the storage capacitor 40 are covered. At the same time, a resist mask 203 that covers the gate electrode 35 wider is formed (third mask formation step).
[0207]
Subsequently, boron ions (second conductivity type impurities) are about 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration second conductivity type impurity introduction step). As a result, the low concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 5.²⁰cm^-3High-concentration source / drain regions 312, 322 and an impurity concentration of about 1.1 × 10¹⁸cm^-3Low concentration source / drain regions 311 and 321. In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 203 is removed.
[0208]
Next, as shown in FIG. 10E, in addition to the second conductivity type driving circuit TFT 30, a resist mask 204 that covers the gate electrodes 15 and 25 is formed (fourth mask forming step). .
[0209]
Subsequently, phosphorus ions (first conductivity type impurities) are 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0210]
As a result, the low concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1 × 10 5.²⁰cm^-3High-concentration source / drain regions 112, 122, 212, 222, and an impurity concentration of about 9 × 10¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this way, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 204 is removed.
[0211]
As a result, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 201 to 204 and five impurity introduction steps.
[0212]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 10B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A low-concentration first conductivity type impurity introduction step for forming the drain regions 111, 121, 211, and 221 is performed, and this step is used to form the lower layer side electrode portion 40c. Therefore, as compared with the conventional manufacturing method, the same effects as those of the third embodiment can be obtained, such that the number of mask forming steps and the number of impurity introducing steps can be reduced by one.
[0213]
Further, as shown in FIG. 10C, in the low concentration second conductivity type impurity introduction step for forming the low concentration source / drain regions 311 and 321, boron ions implanted at this time are converted into the first conductivity type pixels. The TFT 10 for driving and the TFT 20 for driving circuit of the first conductivity type are also formed. That is, the impurity concentration of the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is introduced by using the low concentration second conductivity type impurity introduction step for forming the low concentration source / drain regions 311, 321. Has changed. Therefore, the low concentration source / drain regions 111, 121, 211, and 221 having a lower concentration than the lower layer side electrode portion 40 c of the storage capacitor 40 can be formed without increasing the number of steps as compared with the third embodiment. Therefore, the electrical characteristics of each TFT can be further improved with a small number of steps.
[0214]
As in Example 3, as shown in Tables 2 to 4, the low concentration second conductivity type impurity introduction step shown in FIG. 10 (c) and the high concentration second conductivity type impurity introduction step shown in FIG. 10 (d). And before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, such as changing the order between the high concentration first conductivity type impurity introduction steps shown in FIG. As long as the low-concentration first conductivity type impurity introduction step for forming the drain regions 111, 121, 211, and 221 is performed and the lower layer side electrode portion 40c is formed by using this step, the order of the steps is not limited. May be.
[0215]
[Example 5]
In FIG. 10C, the low-concentration first conductivity type source / drain region 11, by using the low-concentration second conductivity-type impurity introduction step for forming the low-concentration source / drain regions 311, 321, The impurity concentration of only one of 12, 21, and 22 may be changed.
[0216]
For example, in this example, the impurity concentration of the low concentration source / drain regions 111 and 121 of the first conductivity type pixel TFT 10 shown in FIG. The concentration is lower than that of the low-concentration source / drain regions 211 and 221 of the drive circuit TFT of the first conductivity type. That is, in the active matrix substrate 1 of this example, the lower layer side electrode portion 40c of the storage capacitor 40 and the low-concentration source / drain regions 211 and 221 of the first conductivity type driving circuit TFT are the same as in the third embodiment. Impurity concentration is about 1 × 10¹⁹cm^-3However, the low-concentration source / drain regions 111 and 121 of the first-conductivity-type pixel TFT have the same amount of phosphorus ions (impurity concentration as the lower electrode portion 40c of the storage capacitor 40). About 1 × 10¹⁹cm^-3In addition to the low-concentration regions 311 and 321 of the second conductivity type driving circuit TFT 30, boron ions (impurity concentration is about 1.1 × 10 6).¹⁸cm^-3In the first conductivity type region having a low concentration. Therefore, the impurity concentration of the low concentration source / drain regions 111 and 121 is about 9 × 10 5.¹⁸cm^-3It is.
[0217]
In manufacturing the active matrix substrate 1 having such a configuration, the following manufacturing method is used in this example.
[0218]
First, as shown in FIG. 11A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, and 34 and Then, the dielectric film 44 is formed (gate insulating film forming step).
[0219]
After that, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions at a dose of (first impurity introduction step).
[0220]
Next, as shown in FIG. 11B, the second conductive type driving circuit TFT 30 is covered, and the gate electrodes of the first conductive type pixel TFT 10 and the first conductive type driving circuit TFT 20 are covered. A resist mask 301 is formed to cover the formation regions 15 and 25 broadly (first mask formation step).
[0221]
Subsequently, phosphorus ion is about 1 × 10¹⁴cm^-2Ion implantation (second impurity introduction step / low-concentration first conductivity type impurity introduction step) with an impurity concentration of about 1 × 10¹⁹cm^-3The low-concentration first conductivity type source / drain regions 11, 12, 21, 22, and the lower layer side electrode portion 40 c are formed.
[0222]
Next, as shown in FIG. 11C, the gate electrodes 15, 25 and 35 and the upper layer side electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.
[0223]
Each process described above is the same as the manufacturing method according to Examples 3 and 4.
[0224]
Next, a resist mask 302 is formed to cover the formation region of the first conductivity type driving circuit TFT 20 and the storage capacitor 40 and to cover the gate electrode 15 slightly wider like the resist mask 301 (second mask). Forming step).
[0225]
Subsequently, boron ions are about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0226]
As a result, the silicon film 30 a has an impurity concentration of about 1.1 × 10 6 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. The low concentration first conductivity type source / drain regions 11, 12 are substantially reduced in concentration by boron ions implanted therein, and the impurity concentration of the low concentration first conductivity type source / drain regions 11, 12 is as follows. , About 9 × 10¹⁸cm^-3It becomes. Thereafter, the resist mask 302 is removed.
[0227]
Thereafter, as in Example 3, as shown in FIG. 11D, the formation region of the first conductivity type pixel TFT 10, the formation region of the first conductivity type driving circuit TFT 20, and the storage capacitor 40 are covered. At the same time, a resist mask 303 is formed to cover the gate electrode 35 wider (third mask formation step).
[0228]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0229]
As a result, the low concentration second conductivity type source / drain regions 31 and 32 have an impurity concentration of 1 × 10 5.²⁰cm^-3High-concentration source / drain regions 312, 322 and an impurity concentration of about 1.1 × 10¹⁸cm^-3Low concentration source / drain regions 311 and 321. In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 303 is removed.
[0230]
Next, as shown in FIG. 11E, in addition to the second conductivity type driving circuit TFT 30, a resist mask 304 is formed to cover the gate electrodes 15 and 25 (fourth mask formation step). .
[0231]
Subsequently, phosphorus ions (first conductivity type impurities) are 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0232]
As a result, the low concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1 × 10 5.²⁰cm^-3High-concentration source / drain regions 112, 122, 212, 222, and an impurity concentration of about 9 × 10¹⁸cm^-3Low concentration source / drain regions 111 and 121, and an impurity concentration of about 1 × 10¹⁹cm^-3Low concentration source / drain regions 211 and 221. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 304 is removed.
[0233]
Therefore, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 301 to 304 and five impurity introduction steps.
[0234]
As described above, the manufacturing method of the active matrix substrate 1 of the present example has the same effects as those of the third and fourth embodiments. In addition, as shown in FIG. The impurity concentration of the low-concentration first conductivity type source / drain regions 11 and 12 is changed by using the low-concentration second conductivity-type impurity introduction step for forming 321. Therefore, the lightly doped source / drain having a lower concentration than the lower electrode portion 40c of the storage capacitor 40 and the lightly doped source / drain regions 211, 221 without increasing the number of steps as compared with the third and fourth embodiments. Regions 111 and 121 can be formed. Therefore, the low-concentration source / drain regions 111 and 121 of the pixel TFT 10 are left without changing the impurity concentrations of the low-concentration source / drain regions 211 and 221 of the first conductivity type driving circuit TFT 20 and the lower-layer side electrode portion 40c. It is possible to optimize the electrical characteristics of each TFT for each region with a small number of processes such as reducing the concentration and further reducing the off-leak current of the pixel TFT 10 without sacrificing the operation speed in the drive circuit. I can do it.
[0235]
The low concentration second conductivity type impurity introduction step shown in FIG. 11C, the high concentration second conductivity type impurity introduction step shown in FIG. 11D, and the high concentration first conductivity type impurity shown in FIG. Of course, the order may be interchanged between the introduction steps.
[0236]
[Example 6]
FIG. 12 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example.
[0237]
Referring to FIG. 12, in the active matrix substrate 1 with a built-in driving circuit of the liquid crystal display device of this example, a first conductive type pixel TFT 10, a first conductive type drive circuit TFT 20, and a second conductive type drive. Since the channel regions 13, 23 and 33 of the circuit TFT 30 'are channel-doped with low-concentration boron ions, the impurity concentration is about 1 × 10¹⁷cm^-3It is a low-concentration second conductivity type region. Accordingly, the threshold voltages of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20 and the second conductivity type drive circuit TFT 30 'are set to predetermined values.
[0238]
In the active matrix substrate 1 configured as described above, the source / drain regions 11, 12, 21, 22 are opposed to the end portions of the gate electrodes 15, 25 via the gate insulating films 14, 24. The low-concentration source / drain regions 111, 121, 211, and 221 are provided, and the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 have an LDD structure.
[0239]
On the other hand, the second conductivity type driving circuit TFT 30 ′ has an offset gate structure, and in the source / drain regions 31, 32, the gate insulating film 34 with respect to the end of the gate electrode 35. The portions facing each other are offset regions 311 ′ and 321 ′. The offset regions 311 ′ and 321 ′ have an impurity concentration of about 1 × 10 6 like the channel region 33.¹⁷It is a low concentration second conductivity type region of cm-3.
[0240]
In the storage capacitor 40, the lower electrode portion 40 c is a low concentration first conductivity type region formed simultaneously with the low concentration source / drain regions 111, 121, 211, and 221.
[0241]
Of the source regions 11 and 21 and the drain regions 12 and 22 of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20, the low concentration source regions 111 and 211 and the low concentration drain region 121. The regions excluding 221 are high-concentration source / drain regions 112, 122, 212, and 222 having an impurity concentration of about 1 × 10 20 cm −3. Source / drain electrodes 16, 17, 26, 27 such as signal lines and pixel electrodes for each TFT are electrically connected to these high concentration regions through contact holes in the interlayer insulating film 4. Further, in the source / drain regions 31, 32 of the second conductivity type driving circuit TFT 30 ', the impurity concentration adjacent to the offset regions 311', 321 'is about 1 × 10.²⁰cm^-3The source / drain electrodes 36 and 37 such as signal lines are electrically connected to the high concentration source / drain regions 312 and 322 through the contact holes of the interlayer insulating film 4.
[0242]
(TFT on / off leakage current characteristics)
In the active matrix substrate 1 configured as described above, the TFT with the offset gate structure has the same on / off leakage current characteristics as the TFT with the LDD structure, and therefore, any TFT has an extremely small off leakage current. In addition, the TFT with the offset gate structure exhibits the same characteristics as the TFT with the LDD structure in the withstand voltage characteristics. Accordingly, since any TFT has a higher withstand voltage than a TFT having a self-aligned structure, the channel length can be shortened.
[0243]
(TFT manufacturing method)
The active matrix substrate 1 having such a structure can be manufactured by the following method.
[0244]
First, as shown in FIG. 13A, after forming island-like silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step) as in the third embodiment, a gate insulating film is formed. 14, 24, 34 and the dielectric film 44 are formed (gate insulating film forming step).
[0245]
Next, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions at a dose of (channel doping step / first impurity introduction step).
[0246]
Next, as shown in FIG. 13B, the formation area of the second conductivity type driving circuit TFT 30 'is covered, and the gates of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are covered. A resist mask 401 is formed to cover the formation region of the electrodes 15 and 25 slightly wider (first mask formation step).
[0247]
Subsequently, phosphorus ion is about 1 × 10¹⁴cm^-2Ion implantation (second impurity introduction step / low-concentration first conductivity type impurity introduction step) with an impurity concentration of about 1 × 10¹⁹cm^-3The low-concentration first conductivity type source / drain regions 11, 12, 21, 22, and the lower layer side electrode portion 40 c are formed.
[0248]
Next, as shown in FIG. 13C, the gate electrodes 15, 25, and 35, and the upper layer side electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.
[0249]
Next, a resist mask 402 is formed to cover the formation region of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the storage capacitor 40 and to cover the gate electrode 35 wider (second time). Mask forming step).
[0250]
In this state, boron ion is 1 × 10¹⁵cm^-2Are implanted at a dose of (high concentration second conductivity type impurity introduction step / third impurity introduction step).
[0251]
As a result, the low concentration second conductivity type silicon film 30a has an impurity concentration of 1 × 10 5.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. On the other hand, the portion of the low-concentration second conductivity type silicon film 30a covered with the resist mask 402 has an impurity concentration of about 1 × 10 5 as it is.¹⁷cm^-3Offset regions 311 'and 321'. Of course, the channel region 33 has an impurity concentration of about 1 × 10 5.¹⁷cm^-3The low-concentration second conductivity type region remains.
[0252]
In this manner, the second conductivity type driving circuit TFT 30 'is formed. Thereafter, the resist mask 402 is removed.
[0253]
Next, as shown in FIG. 13 (d), in addition to the formation region of the second conductivity type driving circuit TFT 30 ', a resist mask 403 that covers the gate electrodes 15 and 25 is formed (third time). Mask formation step).
[0254]
Subsequently, phosphorus ions (first conductivity type impurities) are 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0255]
As a result, the low concentration first conductivity type source / drain regions 11, 12, 21, 22 have an impurity concentration of 1 × 10 5.²⁰cm^-3High-concentration source / drain regions 112, 122, 212, 222 and an impurity concentration of about 1 × 10¹⁹cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 403 is removed.
[0256]
Therefore, a semiconductor device such as the active matrix substrate 1 can be manufactured through three mask formation steps for forming the resist masks 401 to 403 and four impurity introduction steps.
[0257]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 13B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the low concentration source / drain is formed. A low-concentration first conductivity type impurity introduction step for forming the regions 111, 121, 211, and 221 is performed, and the lower layer side electrode portion 40c is formed by using this step. Therefore, it is possible to reduce the number of mask forming steps and the number of impurity introducing steps as compared with the conventional manufacturing method.
[0258]
Further, in this example, as shown in FIG. 13C, in the second conductivity type driving circuit TFT 30 ′, when the portion facing the gate electrode 35 is set to the low concentration region, not the LDD structure but the offset. It is a gate structure. For this reason, both the mask formation step and the impurity introduction step are less than once in comparison with the third embodiment. That is, compared with the conventional manufacturing method, both the mask formation step and the impurity introduction step are less twice. Therefore, the electrical characteristics of the TFT in the pixel region and the drive circuit portion can be improved with the smallest number of manufacturing steps.
[0259]
In Tables 5 and 6, the channel doping process is “C / D” and the low concentration first conductivity type impurity introduction process is “N”.^- "High concentration first conductivity type impurity introduction process" N⁺ "High concentration second conductivity type impurity introduction process" P⁺ As shown in the order of steps while omitting the gate electrode forming step by “G”, the low concentration source / drain regions 111, 121, 211 are formed before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45. As long as the low-concentration first conductivity type impurity introduction step for forming 221 is performed and this step is used to form the lower layer side electrode portion 40c, any order of steps may be employed.
[0260]
[Table 5]

[0261]
[Table 6]

[0262]
[Example 7]
FIG. 14 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example.
[0263]
Referring to FIG. 14, in the active matrix substrate 1 with a built-in driving circuit of the liquid crystal display device of this example, a first conductive type pixel TFT 10, a first conductive type drive circuit TFT 20, and a second conductive type drive. All of the circuit TFTs 30 have an LDD structure, and in each TFT, the channel regions 13, 23, and 33 are channel-doped with low-concentration boron ions, so that the impurity concentration is about 1 × 10.¹⁷cm^-3It is a low-concentration second conductivity type region.
[0264]
In this example, the lower layer side electrode part 40d (first electrode part) of the storage capacitor 40 includes the high-concentration source / drain regions 112 of the first conductive type pixel TFT 10 and the first conductive type drive circuit TFT 20, The impurity concentration formed simultaneously with 122, 212, 222 is 1 × 10²⁰cm^-3This is a high concentration first conductivity type region.
[0265]
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method.
[0266]
First, as shown in FIG. 15A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0267]
Next, about 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / first impurity introduction step).
[0268]
Next, as shown in FIG. 15B, a resist mask 501 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 and to cover the formation regions of the gate electrodes 15 and 25 to be formed later. (First mask formation step).
[0269]
Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction process / high concentration first conductivity type impurity introduction process).
[0270]
As a result, in the low-concentration second conductivity type silicon films 10a and 20a, the region where the phosphorus ions are implanted has the conductivity type inverted and the impurity concentration is about 1 × 10.²⁰cm^-3High concentration source / drain regions 112, 122, 212, 222. The low-concentration second conductivity type silicon film 40a is also inverted in conductivity type so that the impurity concentration is about 1 × 10.²⁰cm^-3The lower concentration side first conductivity type lower electrode portion 40d is formed. Thereafter, the resist mask 501 is removed.
[0271]
Next, as shown in FIG. 15C, the gate electrodes 15, 25 and 35 and the upper layer side electrode portion 45 (second electrode portion) are formed (gate electrode forming step). In this manner, the storage capacitor 40 is formed in which the lower layer side electrode portion 40d and the upper layer side electrode portion 45 are opposed to each other with the dielectric film 44 interposed therebetween.
[0272]
Next, a resist mask 502 is formed to cover the formation regions of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the storage capacitor 40 (second mask formation step).
[0273]
Subsequently, boron ions are about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0274]
As a result, the low-concentration second conductivity type silicon film 30 a has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. A portion where no impurity is introduced becomes a channel region 33. Thereafter, the resist mask 502 is removed.
[0275]
Next, as shown in FIG. 15D, a resist mask 503 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 (third mask forming step).
[0276]
Subsequently, phosphorus ion is about 1 × 10¹³cm^-2(4th impurity introduction step / low concentration first conductivity type impurity introduction step).
[0277]
As a result, the low-concentration second conductivity type silicon films 10a and 20a sandwiched between the high-concentration source / drain regions 112, 122, 212, and 222 have an impurity concentration in a self-aligned manner with respect to the gate electrodes 15 and 25. 0.9 × 10¹⁸cm^-3Low concentration source / drain regions 211 and 221 are formed. The portions where impurities are not introduced become channel regions 23 and 33. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 503 is removed.
[0278]
Next, as shown in FIG. 15E, the first conductive type pixel TFT 10, the first conductive type drive circuit TFT 20, and the storage capacitor 40 are formed, and the gate electrode 35 is covered wider. A resist mask 504 is formed (fourth mask formation step). Here, the distance between the end portion of the resist mask 504 and the end portion of the gate electrode 35 is suitably about 0.5 μm to 2 μm.
[0279]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0280]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Further, in the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 504 has an impurity concentration of about 1.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0281]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 504 is removed.
[0282]
Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 501 to 504 and five impurity introduction steps.
[0283]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 15B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration first conductivity type impurity introduction step for forming the drain regions 112, 122, 212, and 222 is performed, and the lower layer side electrode portion 40d is formed by using this step. Therefore, it is possible to reduce the number of mask formation steps and the number of impurity introduction steps one by one as compared with the conventional manufacturing method. Therefore, the electrical characteristics of each TFT can be improved while forming the TFT and the capacitor (retention capacitor 40) with a small number of manufacturing steps.
[0284]
In Table 7, the channel doping process is “C / D” and the low concentration first conductivity type impurity introduction process is “N”.^- "High concentration first conductivity type impurity introduction process" N⁺ "Low concentration second conductivity type impurity introduction process" P^- "High concentration second conductivity type impurity introduction process" P⁺ As shown in the order of steps by abbreviating the gate electrode forming process as “G”, the high concentration source / drain regions 112, 122, 212 are formed before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45. , 222 may be performed in any order as long as the high-concentration first conductivity type impurity introduction step is performed and the lower electrode portion 40d is formed by using this step.
[0285]
[Table 7]

[0286]
[Example 8]
The structure of the active matrix substrate of this example will be described with reference to FIG.
[0287]
In FIG. 14, the feature of the active matrix substrate 1 of this example is that the number of mask forming steps is one less than that of the manufacturing method according to the seventh embodiment, and the manufacturing method is as described below. Yes.
[0288]
First, as shown in FIG. 16A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0289]
Next, about 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions (second conductivity type impurities / second conductivity type impurities) at a dose of (channel doping step / first impurity introduction step).
[0290]
Next, as shown in FIG. 16B, a resist mask 601 is formed which covers the formation region of the second conductivity type driving circuit TFT 30 and covers the formation regions of the gate electrodes 15 and 25 to be formed later. (First mask formation step).
[0291]
Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction process / high concentration first conductivity type impurity introduction process).
[0292]
As a result, in the low-concentration second conductivity type silicon films 10a and 20a, the region where the phosphorus ions are implanted has the conductivity type inverted and the impurity concentration is about 1 × 10.²⁰cm^-3High concentration source / drain regions 112, 122, 212, 222. The low-concentration second-conductivity type silicon film 40a also has an impurity concentration of about 1 × 10 by inverting the conductivity type.²⁰cm^-3The lower concentration side first conductivity type lower electrode portion 40d is formed. Thereafter, the resist mask 601 is removed.
[0293]
Next, as shown in FIG. 16C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0294]
Next, a resist mask 602 is formed to cover the formation regions of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the storage capacitor 40 (second mask formation step).
[0295]
Next, about 3 × 10 boron ions¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0296]
As a result, the low-concentration second conductivity type silicon film 30a has an impurity concentration of about 3.1 × 10 10 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. A portion where no impurity is introduced becomes a channel region 33. Thereafter, the resist mask 602 is removed.
[0297]
Next, as shown in FIG. 16 (d), phosphorus ions are added by about 1 × 10 without forming a resist mask.¹³cm^-2(4th impurity introduction step / low concentration first conductivity type impurity introduction step).
[0298]
As a result, the low-concentration second conductivity type silicon films 10a and 20a sandwiched between the high-concentration source / drain regions 112, 122, 212, and 222 have an impurity concentration in a self-aligned manner with respect to the gate electrodes 15 and 25. 0.9 × 10¹⁸cm^-3Low concentration source / drain regions 111, 121, 211 and 221 are formed. The portions where impurities are not introduced become channel regions 23 and 33. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed.
[0299]
Here, phosphorus ions are also present in the low-concentration second conductivity type source / drain regions 31 and 32 by 1 × 10 6.¹³cm^-2The impurity concentration of the low-concentration second conductivity type source / drain regions 31 and 32 is about 3.1 × 10 10.¹⁸cm^-3It is. Therefore, the low-concentration second conductivity type source / drain regions 31 and 32 substantially have an acceptor-type impurity concentration of about 2.1 × 10 6.¹⁸cm^-3However, the conductivity type is not reversed.
[0300]
Next, as shown in FIG. 16 (e), the first conductive type pixel TFT 10, the first conductive type drive circuit TFT 20, and the storage capacitor 40 are covered and the gate electrode 35 is covered wider. A resist mask 603 is formed (third mask formation step).
[0301]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0302]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31 and 32 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Of the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 603 has an impurity concentration of about 2.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0303]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 603 is removed.
[0304]
Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured through three mask formation steps for forming the resist masks 601 to 603 and five impurity introduction steps.
[0305]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 16B, before forming the gate electrodes 15, 25 and 35 and the upper layer side electrode 45, the high concentration source A high-concentration first conductivity type impurity introduction step for forming the drain regions 112, 122, 212, and 222 is performed, and the lower layer side electrode portion 40d is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0306]
In addition, in the process for forming the low concentration source / drain regions 111, 121, 211, and 221, phosphorus ions are implanted without forming a mask. Therefore, each TFT and the storage capacitor 40 can be manufactured by three mask formation steps and five impurity introduction steps.
[0307]
As in the seventh embodiment, the high-concentration first conductivity type for forming the high-concentration source / drain regions 112, 122, 212, and 222 before forming the gate electrodes 15, 25, and 35 and the upper layer side electrode 45. Any order of steps shown in Table 7 may be employed as long as an impurity introduction step is performed and this step is used to form the lower layer side electrode portion 40d.
[0308]
[Example 9]
The structure of the active matrix substrate of this example will be described with reference to FIG. Similar to the eighth embodiment, the feature of this embodiment is that the number of mask forming steps is one less than that of the manufacturing method according to the seventh embodiment, and the manufacturing method is as described below.
[0309]
First, as shown in FIG. 17A, after forming island-like silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, And the dielectric film 44 are formed (step of forming a gate insulating film).
Next, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of about 1 × 10 12 cm −2 to perform channel doping (channel doping step / first impurity introduction step).
[0310]
Next, as shown in FIG. 17B, a resist mask 701 is formed which covers the formation region of the second conductivity type driving circuit TFT 30 and covers the formation regions of the gate electrodes 15 and 25 to be formed later. (First mask formation step).
[0311]
Subsequently, for example, phosphorus ions (first conductivity type impurities / first conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction process / high concentration first conductivity type impurity introduction process).
[0312]
As a result, in the low-concentration second conductivity type silicon films 10a and 20a, the region where the phosphorus ions are implanted has the conductivity type inverted and the impurity concentration is about 1 × 10.²⁰cm^-3High concentration source / drain regions 112, 122, 212, 222. The low-concentration second-conductivity type silicon film 40a also has an impurity concentration of about 1 × 10 by inverting the conductivity type.²⁰cm^-3The lower concentration side first conductivity type lower electrode portion 40d is formed. Thereafter, the resist mask 701 is removed.
[0313]
Next, as shown in FIG. 17C, the gate electrodes 15, 25, and 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0314]
Next, a resist mask 702 is formed to cover the formation region of the p-type driver circuit TFT 30 (second mask formation step).
[0315]
Subsequently, about 3 × 10 phosphorus ions¹³cm^-2(3rd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0316]
As a result, the low-concentration second conductivity type silicon films 10a and 20a sandwiched between the high-concentration source / drain regions 112, 122, 212, and 222 have an impurity concentration in a self-aligned manner with respect to the gate electrodes 15 and 25. 2.9 × 10¹⁸cm^-3Low concentration source / drain regions 111, 121, 211 and 221 are formed. The portions where impurities are not introduced become channel regions 23 and 33. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed.
[0317]
Next, as shown in FIG. 17D, the resist mask 702 is removed, and boron ions are about 1 × 10 6 without forming the resist mask as it is.¹³cm^-2(4th impurity introduction step / low concentration second conductivity type impurity introduction step).
[0318]
As a result, the low-concentration second conductivity type silicon film 30 a has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration p-type regions 31 and 32 are formed. A portion where no impurity is introduced becomes a channel region 33.
[0319]
Here, boron ions are also present on the side of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 by 1 × 10 5.¹³cm^-2The impurity concentration of the low concentration source / drain regions 111, 121, 211, and 221 is about 2.9 × 10.¹⁸cm^-3It is. Therefore, the low-concentration source / drain regions 111, 121, 211, and 221 substantially have a donor-type impurity concentration of about 1.9 × 10.¹⁸cm^-3However, the conductivity type is not reversed. The high-concentration dose / drain regions 112, 122, 212, and 222 are also only slightly reduced in concentration, the conductivity type is not reversed, and the concentration is still high.
[0320]
Next, as shown in FIG. 17E, the first conductive type pixel TFT 10 forming region, the first conductive type driving circuit TFT 20 forming region, and the storage capacitor 40 are covered, and the gate electrode 35 is covered. A resist mask 703 that covers a wider area is formed (third mask formation step).
[0321]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0322]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31, 32 is 1 × 10.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Further, in the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 703 has an impurity concentration of about 2.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0323]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 703 is removed.
[0324]
Thereafter, as shown in FIG. 14, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask formation steps for forming the resist masks 701 to 703 and five impurity introduction steps.
[0325]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 17B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration first conductivity type impurity introduction step for forming the drain regions 112, 122, 212, and 222 is performed, and the lower layer side electrode portion 40d is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0326]
In addition, in the step for forming the low concentration source / drain regions 311 and 321, boron ions are implanted without forming a mask. Therefore, each TFT and the storage capacitor 40 can be manufactured by three mask formation steps and five impurity introduction steps.
[0327]
As in the seventh embodiment, the high-concentration first conductivity type for forming the high-concentration source / drain regions 112, 122, 212, and 222 before forming the gate electrodes 15, 25, and 35 and the upper layer side electrode 45. Any order of steps shown in Table 7 may be employed as long as an impurity introduction step is performed and this step is used to form the lower layer side electrode portion 40d.
[0328]
[Example 10]
FIG. 18 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example.
[0329]
In FIG. 18, in the active matrix substrate 1 with a built-in drive circuit of the liquid crystal display device of this example, the first conductive type pixel TFT 10 and the first conductive type drive circuit TFT 20 have an LDD structure. There is. In contrast, the second conductivity type driving circuit TFT 30 'has an offset gate structure.
[0330]
In this example, the lower electrode portion 40d of the storage capacitor 402 is simultaneously with the high-concentration source / drain regions 112, 122, 212, and 222 of the first conductivity type driving circuit TFT 20 and the first conductivity type pixel TFT 10. The impurity concentration formed is 1 × 10²⁰cm^-3The first conductivity type region of high concentration.
[0331]
The active matrix substrate 1 having such a structure can be manufactured by the following method.
[0332]
First, as shown in FIG. 19A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0333]
After that, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions at a dose of (channel doping step / first impurity introduction step).
[0334]
Next, as shown in FIG. 19B, the formation area of the second conductivity type driving circuit TFT 30 'is covered, and the gates of the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are covered. A resist mask 801 that covers a region where the electrodes 15 and 25 are to be formed is formed to be wide (first mask formation step).
[0335]
Subsequently, a first conductivity type impurity such as phosphorous ion is about 1 × 10¹⁵cm^-2(2nd impurity introduction process / high concentration first conductivity type impurity introduction process).
[0336]
As a result, in the silicon films 10a and 20a, the regions where phosphorus ions are implanted are inverted in conductivity type and have an impurity concentration of about 1 × 10.²⁰cm^-3High concentration source / drain regions 112, 122, 211, and 221. The silicon film 40a is inverted in conductivity type and has an impurity concentration of about 1 × 10.²⁰cm^-3The lower concentration side first conductivity type lower electrode portion 40d is formed. Thereafter, the resist mask 801 is removed.
[0337]
Next, as shown in FIG. 19C, gate electrodes 15, 25, and 35 made of doped silicon, silicide film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34 (gate electrode forming step). At the same time, the upper electrode portion 45 is formed on the surface of the dielectric film 44. The upper layer side electrode unit 45 may be a part of the previous signal line. In this way, the storage capacitor 40 is formed in which the lower layer side electrode part 40 c and the upper layer side electrode part 45 are opposed to each other with the dielectric film 44 interposed therebetween.
[0338]
Next, a resist mask 802 covering the second conductivity type driving circuit TFT 30 is formed (second mask formation step).
[0339]
In this state, phosphorus ion is 1 × 10¹³cm^-2Are implanted at a low dose (low-concentration first conductivity type impurity introduction step / third impurity introduction step).
[0340]
As a result, the low-concentration second conductivity type silicon films 20a and 30a sandwiched between the high-concentration source / drain regions 112, 122, 212, and 222 have an impurity concentration in a self-aligned manner with respect to the gate electrodes 15 and 25. 0.9 × 10¹⁸Low concentration source / drain regions 111, 121, 211, and 221 of cm-3 are formed. The portions where impurities are not introduced become channel regions 23 and 33. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed.
[0341]
Next, as shown in FIG. 19D, the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the storage capacitor 40 are covered, and the gate electrode 35 is covered wider. A resist mask 803 is formed (third mask formation step).
[0342]
In this state, boron ion is 1 × 10¹⁵cm^-2Are implanted at a dose of (high concentration second conductivity type impurity introduction step / fourth impurity introduction step).
[0343]
As a result, high concentration source / drain regions 312 and 322 having an impurity concentration of 1 × 10 20 cm −3 are formed in the low concentration second conductivity type silicon film 30a. On the other hand, the portion of the low-concentration second conductivity type silicon film 30a covered with the resist mask 803 has an impurity concentration of about 1 × 10 5 as it is.¹⁷cm^-3Offset regions 311 'and 321'. The channel region 33 has an impurity concentration of about 1 × 10¹⁷cm^-3The low-concentration second conductivity type region remains.
[0344]
In this manner, the second conductivity type driving circuit TFT 30 'is formed. Thereafter, the resist mask 803 is removed.
[0345]
Therefore, the active matrix substrate 1 can be manufactured through three mask formation steps for forming the resist masks 801 to 803 and four impurity introduction steps.
[0346]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 19B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the high concentration source / drain is formed. A high-concentration first conductivity type impurity introduction step for forming the regions 112, 122, 212, and 222 is performed, and the lower layer side electrode portion 40d is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0347]
Further, in this example, as shown in FIG. 19C, in the second conductivity type driving circuit TFT 30 ′, when the portion facing the end of the gate electrode 35 is made a low concentration region, the LDD structure There is no offset gate structure. For this reason, as compared with the third embodiment, both the mask formation step and the impurity introduction step are less each time. That is, as compared with the conventional manufacturing method, both the mask formation step and the impurity introduction step are less twice. Therefore, the electrical characteristics of the TFT in the pixel region and the drive circuit portion can be improved with the smallest number of manufacturing steps.
[0348]
In Table 8, the channel doping step is “C / D”, the low concentration first conductivity type impurity introduction step is “N−”, and the high concentration first conductivity type impurity introduction step is “N”.⁺ "High concentration second conductivity type impurity introduction process" P⁺ As shown in the order of steps while omitting the gate electrode forming step by “G”, the high concentration source / drain regions 112, 122, 212 are formed before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45. As long as the low-concentration first conductivity type impurity introduction step for forming 222 is performed and the lower layer side electrode portion 40d is formed by using this step, any order may be used.
[0349]
[Table 8]

[0350]
[Example 11]
As shown in FIG. 20, in the active matrix substrate 1 of this example, the second conductivity type driving circuit TFT 30, the first conductivity type driving circuit TFT 20, and the first conductivity type pixel TFT 10 are all LDD. It has a structure.
[0351]
In the active matrix substrate 1 of this example, the lower electrode portion 40e (first electrode portion) of the storage capacitor 40 is formed simultaneously with the low concentration source / drain regions 311 and 312 of the second conductivity type driving circuit TFT 30. Impurity concentration is 1 × 10¹⁹cm^-3It is a low-concentration second conductivity type region.
[0352]
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method.
[0353]
First, as shown in FIG. 21A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0354]
Next, about 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / first impurity introduction step).
[0355]
Next, as shown in FIG. 21B, the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 is covered, and the formation region of the gate electrode 35 to be formed later is slightly widened. A resist mask 901 is formed to cover (a first mask formation step).
[0356]
Subsequently, for example, boron phosphorus ions (second conductivity type impurities / second conductivity type impurities) are about 1 × 10 5.¹⁴cm^-2(2nd impurity introduction process / low-concentration second conductivity type impurity introduction process).
[0357]
As a result, the low concentration second conductivity type silicon film 30a has an impurity concentration of about 1 × 10 10.¹⁹cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. The low-concentration second conductivity type silicon film 40a has an impurity concentration of about 1 × 10 6.¹⁹cm^-3The low-concentration second conductivity type lower electrode portion 40e. Thereafter, the resist mask 901 is removed.
[0358]
Next, as shown in FIG. 21C, gate electrodes 15, 25, and 35 made of doped silicon, a silicide film, and the like are formed on the surfaces of the gate insulating films 14, 24, and 34. At the same time, an upper electrode portion 45 (second electrode portion) is formed on the surface of the dielectric film 44 (gate electrode forming step). The upper layer side electrode unit 45 may be a part of the previous signal line. In this way, the storage capacitor 40 is formed in which the lower layer side electrode part 40e and the upper layer side electrode part 45 are opposed to each other with the dielectric film 44 interposed therebetween.
[0359]
Next, a resist mask 902 that covers the formation region of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 is formed (second mask formation step).
[0360]
Subsequently, phosphorus ion is about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0361]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have an impurity concentration of about 0.9 × 10 5 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23. Thereafter, the resist mask 902 is removed.
[0362]
Next, as shown in FIG. 21 (d), the first conductive type pixel TFT 10, the first conductive type drive circuit TFT 20, and the storage capacitor 40 are formed, and the gate electrode 35 is covered wider. A resist mask 903 is formed (third mask formation step).
[0363]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0364]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31, 32 is 1 × 10.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Further, in the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 103 has an impurity concentration of about 1.1 × 10 5 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0365]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 903 is removed.
[0366]
Next, as shown in FIG. 21E, a resist mask 904 that covers the second conductivity type driving circuit TFT 30 and covers the gate electrodes 15 and 25 is formed (fourth mask forming step).
[0367]
Subsequently, phosphorus ion is 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0368]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed. Further, in the low-concentration first conductivity type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 904 has an impurity concentration of about 0.9 × 10 as it is.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221.
[0369]
In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 904 is removed.
[0370]
Thereafter, as shown in FIG. 20, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured through four mask formation steps for forming the resist masks 901 to 904 and five impurity introduction steps.
[0371]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 21B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the low-concentration source A low-concentration second conductivity type impurity introduction step for forming the drain regions 311 and 321 is performed, and the lower layer side electrode portion 40e is formed by using this step. Therefore, it is possible to reduce the number of mask formation steps and the number of impurity introduction steps one by one as compared with the conventional manufacturing method. Therefore, the electrical characteristics of each TFT in the pixel region and the drive circuit portion can be improved while forming the TFT and the capacitor (retention capacitor 40) with a small number of manufacturing steps.
[0372]
The manufacturing method of this example is the same as that in the manufacturing method according to Example 3 shown in Tables 2 to 4.^- A low concentration first conductivity type impurity introduction step indicated by^- Therefore, the low concentration source / drain regions 311 and 321 are formed before forming the gate electrodes 15, 25 and 35 and the upper layer side electrode 45. If the low-concentration second-conductivity type impurity introduction step is performed to form the lower electrode portion 40e with the aid of this step, any of the 60 process sequences can be performed. May be.
[0373]
Example 12
The feature of the active matrix substrate 1 of this example is that the low-concentration source / drain regions 311 and 321 of the driving circuit TFT 30 of the second conductivity type are formed in the storage capacitor while being manufactured with the same number of steps as the manufacturing method according to Example 11. The lower concentration of the lower electrode portion 40e is 40.
[0374]
That is, in FIG. 20, the lower layer side electrode portion 40e of the storage capacitor 40 is formed simultaneously with the low-concentration source / drain regions 311 and 321 of the second conductivity type driving circuit TFT 30 as in the eleventh embodiment. However, the impurity concentration of the lower layer side electrode part 40e is about 1 × 10¹⁹cm^-3The low-concentration source / drain regions 311 and 321 of the second-conductivity-type driving circuit TFT 30 have an impurity concentration of about 9 × 10.¹⁸cm^-3It is.
[0375]
In the active matrix substrate 1 of this example, all of the second conductivity type driving circuit TFT 30, the first conductivity type driving circuit TFT 20, and the first conductivity type pixel TFT 10 are gate electrodes 15, 25, 35. The LDD structure is provided with low-concentration source / drain regions 111, 121, 211, 221, 311, and 321 at portions facing each other through the gate insulating films 14, 24, and 34.
[0376]
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method. In the following description, all impurity concentrations are expressed as impurity concentrations after activation annealing.
[0377]
First, as shown in FIG. 22A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0378]
Next, about 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions (second conductivity type impurities / second conductivity type impurities) at a dose of (channel doping step / first impurity introduction step).
[0379]
Next, as shown in FIG. 22B, the second conductive type driving circuit TFT 30 to be formed later is covered while the formation regions of the first conductive type pixel TFT 10 and the first conductive type driving circuit TFT 20 are covered. A resist mask 1101 is formed to cover a region where the gate electrode 35 is to be formed slightly wider (first mask formation step).
[0380]
Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are about 1 × 10 5.¹⁴cm^-2(2nd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0381]
As a result, the low concentration second conductivity type silicon film 30a has an impurity concentration of about 1 × 10 10.¹⁹cm^-3Low concentration second conductivity type source / drain regions 31, 32 are formed. The low-concentration second conductivity type silicon film 40a has an impurity concentration of about 1 × 10 6.¹⁹cm^-3The low-concentration second conductivity type lower electrode portion 40e. Thereafter, the resist mask 1101 is removed.
[0382]
Next, as shown in FIG. 22C, the gate electrodes 15, 25, 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0383]
Next, a resist mask 1102 that covers the formation region of the storage capacitor 40 is formed (second mask formation step).
[0384]
Subsequently, phosphorus ion is about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0385]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have an impurity concentration of about 0.9 × 10 5 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23.
[0386]
Here, phosphorus ions are also present in the low-concentration second conductivity type silicon films 31 and 32 by about 1 × 10 6.¹³cm^-2The impurity concentration of the low-concentration second conductivity type silicon films 31 and 32 is about 1 × 10 10.¹⁹cm^-3It is. Accordingly, the low-concentration second conductivity type silicon films 31 and 32 substantially have an acceptor-type impurity concentration of about 9 × 10.¹⁸cm^-3However, the conductivity type is not reversed.
[0387]
Thereafter, the resist mask 1102 is removed.
[0388]
Next, as shown in FIG. 22D, the first conductive type pixel TFT 10, the first conductive type drive circuit TFT 20, and the storage capacitor 40 are covered, and the gate electrode 35 is covered wider. A resist mask 1103 is formed (third mask formation step).
[0389]
Subsequently, boron ions are about 1 × 10¹⁵cm^-2(4th impurity introduction step / high concentration second conductivity type impurity introduction step).
[0390]
As a result, the impurity concentration of the low concentration second conductivity type source / drain regions 31, 32 is 1 × 10.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. Further, in the low-concentration second conductivity type source / drain regions 31, 32, the portion covered with the resist mask 1103 has an impurity concentration of about 9 × 10 as it is.¹⁸cm^-3Low concentration source / drain regions 311 and 321.
[0390]
In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 1103 is removed.
[0392]
Next, as shown in FIG. 22E, a resist mask 1104 is formed which covers the formation regions of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 and covers the gate electrodes 15 and 25 wider (4). Second mask formation step).
[0393]
Subsequently, phosphorus ion is 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0394]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 222, and 222 are formed. Further, the portion of the low concentration first conductivity type source / drain region 11, 12, 21, 22 covered with the resist mask 1104 has an impurity concentration of about 0.9 × 10.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221.
[0395]
In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1104 is removed.
[0396]
Thereafter, as shown in FIG. 20, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 1101 to 1104 and five impurity introduction steps.
[0397]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 22B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A low-concentration first conductivity type impurity introduction step for forming the drain regions 311 and 321 is performed, and the lower layer side electrode portion 40e is formed by using this step. Therefore, as compared with the conventional manufacturing method, the same effects as those of the twelfth embodiment can be achieved, for example, the number of mask forming steps and the number of impurity introducing steps can be reduced by one.
[0398]
Further, as shown in FIG. 22C, in the low concentration first conductivity type impurity introduction step for forming the low concentration source / drain regions 111, 121, 211, and 221, the phosphorus ions implanted at this time are converted into the second conductivity type. The drive circuit TFT 30 is also formed. That is, the impurity concentration of the low-concentration second conductivity type source / drain regions 31 and 32 for forming the low-concentration source / drain regions 311 and 321 is changed by using the low-concentration first conductivity type impurity introduction step. . Therefore, it is possible to form the lightly doped source / drain regions 311 and 321 having a concentration lower than that of the lower layer side electrode portion 40e of the storage capacitor 40 without increasing the number of steps as compared with the embodiment 11.
[0399]
The manufacturing method of this example corresponds to a method in which the low concentration first conductivity type impurity introduction step and the low concentration second conductivity type impurity introduction step are interchanged in the manufacturing method according to the fourth embodiment. Before forming the electrodes 15, 25, 35 and the upper layer side electrode 45, a low-concentration second conductivity type impurity introduction step for forming the low-concentration source / drain regions 311, 321 is performed. If the lower layer side electrode part 40e is to be formed, “N” of the 60 process orders shown in Tables 2 to 4 is used.^- A low concentration first conductivity type impurity introduction step indicated by^- Any order of the steps may be used in which the low-concentration second conductivity type impurity introduction step shown in FIG.
[0400]
[Example 13]
FIG. 23 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example. In the active matrix substrate of this example, the basic structure of each TFT is substantially the same as that of the active matrix substrate shown in FIG.
[0401]
In FIG. 23, in the active matrix substrate 1 with a built-in driving circuit of the liquid crystal display device of this example, the first conductive type TFT for pixel 10, the first conductive type driving circuit TFT 20, and the second conductive type drive. All of the circuit TFTs 30 have an LDD structure, and in each TFT, the channel regions 13, 23, and 33 are channel-doped with low-concentration boron ions, so that the impurity concentration is about 1 × 10.¹⁷cm^-3It is a low-concentration second conductivity type region.
[0402]
In this example, the lower electrode portion 40f (first electrode portion) of the storage capacitor 402 has an impurity concentration of 1 formed simultaneously with the high concentration source / drain regions 311 and 312 of the second conductivity type driving circuit TFT 30. × 10²⁰cm^-3It is a high concentration second conductivity type region.
[0403]
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method.
[0404]
First, as shown in FIG. 24A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, The dielectric film 44 is formed at the same time (gate insulating film forming step).
[0405]
Next, about 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / first impurity introduction step).
[0406]
Next, as shown in FIG. 24B, the first conductive type TFT 10 for pixel and the first conductive type TFT 20 for driving circuit are covered and the second conductive type TFT 30 for driving circuit to be formed later. A resist mask 1201 is formed to cover a region where the gate electrode 35 is to be formed slightly wider (first mask formation step).
[0407]
Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction step / high concentration second conductivity type impurity introduction step).
[0408]
As a result, in the low-concentration second conductivity type silicon film 30a, the region in which high-concentration boron ions are implanted has an impurity concentration of about 1 × 10.²⁰cm^-3High concentration source / drain regions 312, 322. The low-concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10.²⁰cm^-3The high-concentration second conductivity type lower electrode portion 40f. Thereafter, the resist mask 1201 is removed.
[0409]
Next, as shown in FIG. 24C, the gate electrodes 15, 25 and 35 and the upper layer side electrode portion 45 (second electrode portion) are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0410]
Next, a resist mask 1202 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 (second mask formation step).
[0411]
Subsequently, phosphorus ion is about 1 × 10¹³cm^-2(3rd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0412]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have an impurity concentration of about 0.9 × 10 5 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23. Thereafter, the resist mask 1202 is removed.
[0413]
Next, as shown in FIG. 24D, a resist mask 1203 is formed to cover the formation regions of the first conductivity type pixel TFT 10, the first conductivity type drive circuit TFT 20, and the storage capacitor 40 (third time). Mask forming step).
[0414]
Subsequently, boron ions are about 1 × 10¹³cm^-2(4th impurity introduction step / low concentration second conductivity type impurity introduction step).
[0415]
As a result, the low-concentration second conductivity type silicon film 30a sandwiched between the high-concentration source / drain regions 312 and 322 has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration source / drain regions 311 and 321 are formed. A portion where no impurity is introduced becomes a channel region 33. In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 1203 is removed.
[0416]
Next, as shown in FIG. 24E, a resist mask 1204 that covers the formation regions of the second-conductivity-type driving circuit TFT 30 and the storage capacitor 40 and covers the gate electrodes 15 and 25 wider is formed. Fourth mask formation step).
[0417]
Subsequently, phosphorus ion is about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0418]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed. Further, in the low-concentration second conductivity type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 1204 has an impurity concentration of about 0.9 × 10.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1204 is removed.
[0419]
Thereafter, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by four mask formation steps for forming the resist masks 1201 to 1204 and five impurity introduction steps.
[0420]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 24B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration second conductivity type impurity introduction step for forming the drain regions 312 and 322 is performed, and the lower layer side electrode portion 40f is formed by using this step. Therefore, it is possible to reduce the number of mask formation steps and the number of impurity introduction steps one by one as compared with the conventional manufacturing method. Therefore, it is possible to improve the electrical characteristics of each TFT while forming the TFT and the capacitor (retention capacitor 40) with a small number of manufacturing steps.
[0421]
The manufacturing method of this example corresponds to a method in which the high concentration first conductivity type impurity introduction step and the high concentration second conductivity type impurity introduction step are interchanged in the manufacturing method according to the seventh embodiment. Prior to forming the electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. If the lower electrode portion 40f is to be formed, “N” of the 24 process orders shown in Table 7⁺ A high concentration first conductivity type impurity introduction step indicated by⁺ Any sequence of steps may be used in which the high-concentration second conductivity type impurity introduction step shown in FIG.
[0422]
[Example 14]
The feature of the active matrix substrate 1 of this example is that the number of mask forming steps is less than that of the manufacturing method according to the thirteenth embodiment, and the manufacturing method is as described below.
[0423]
First, as shown in FIG. 25A, after forming island-like silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0424]
Next, about 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / first impurity introduction step).
[0425]
Next, as shown in FIG. 25 (b), the first conductive type pixel TFT 10 and the first conductive type drive circuit TFT 20 are covered, and the second conductive type drive circuit TFT 30 to be formed later is covered. A resist mask 1301 is formed to cover a region where the gate electrode 35 is to be formed slightly wider (first mask formation step).
[0426]
Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction step / high concentration second conductivity type impurity introduction step).
[0427]
As a result, in the low-concentration second conductivity type silicon film 30a, the region in which high-concentration boron ions are implanted has an impurity concentration of about 1 × 10.²⁰cm^-3High concentration source / drain regions 312, 322. The low-concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10.²⁰cm^-3The high-concentration second conductivity type lower electrode portion 40f. Thereafter, the resist mask 1301 is removed.
[0428]
Next, as shown in FIG. 25C, the gate electrodes 15, 25, and 35 and the upper layer side electrode portion 45 are formed (gate electrode forming step). In this way, the storage capacitor 40 is formed.
[0429]
Next, a resist mask 1302 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 (second mask formation step).
[0430]
Subsequently, about 3 × 10 phosphorus ions¹³cm^-2(3rd impurity introduction step / low concentration first conductivity type impurity introduction step).
[0431]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have an impurity concentration of about 2.9 × 10 6 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23. Thereafter, the resist mask 1302 is removed.
[0432]
Next, as shown in FIG. 25D, without forming a mask, boron ions are about 1 × 10 × 10.¹³cm^-2(4th impurity introduction step / low concentration second conductivity type impurity introduction step).
[0433]
As a result, the low-concentration second conductivity type silicon film 30a sandwiched between the high-concentration source / drain regions 312 and 322 has an impurity concentration of about 1.1 × 10 5 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration source / drain regions 311 and 321 are formed. A portion where no impurity is introduced becomes a channel region 33. In this way, the second conductivity type driving circuit TFT 30 is formed.
[0434]
On the other hand, boron ions are also present in the low-concentration first conductivity type silicon films 11, 12, 21 and 22 by about 1 × 10 6.¹³cm^-2However, the impurity concentration of the low-concentration first conductivity type silicon films 11, 12, 21, and 22 is about 2.9 × 10.¹⁸cm^-3It is. Therefore, the low-concentration first conductivity type silicon films 11, 12, 21, and 22 substantially have a donor-type impurity concentration of about 1.9 × 10.¹⁸cm^-3However, the conductivity type is not reversed.
[0435]
Next, as shown in FIG. 25E, a resist mask 1303 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 and to cover the gate electrodes 15 and 25 broadly (see FIG. 25E). Third mask formation step).
[0436]
Subsequently, phosphorus ion is about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0437]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed. Further, in the low-concentration second conductivity type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 1204 has an impurity concentration of about 1.9 × 10.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1303 is removed.
[0438]
Thereafter, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured by three mask formation steps for forming the resist masks 1301 to 1303 and five impurity introduction steps.
[0439]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 25B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, A high-concentration second conductivity type impurity introduction step for forming the drain regions 312 and 322 is performed, and the lower layer side electrode portion 40f is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0440]
In addition, as shown in FIG. 25D, boron ions are implanted without forming a mask in the process for forming the low concentration source / drain regions 311 and 321. Therefore, each TFT and the storage capacitor 40 can be manufactured by three mask formation steps and five impurity introduction steps.
[0441]
The manufacturing method of this example corresponds to a method in which the high concentration first conductivity type impurity introduction step and the high concentration second conductivity type impurity introduction step are interchanged in the manufacturing method according to the eighth embodiment. Prior to forming the electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. If the lower electrode portion 40f is to be formed, “N” of the 24 process orders shown in Table 7⁺ A high concentration first conductivity type impurity introduction step indicated by⁺ Any sequence of steps may be used in which the high-concentration second conductivity type impurity introduction step shown in FIG.
[0442]
[Example 15]
The basic part of the active matrix substrate and the manufacturing method thereof in this example is the same as that in the fourteenth embodiment. The feature of this example is that the mask forming step is less than once compared with the manufacturing method according to the embodiment 13, as in the case of the embodiment 14. The manufacturing method is as described below.
[0443]
First, as shown in FIG. 26A, after forming island-shaped silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0444]
Next, about 1 × 10¹²cm^-2Then, boron ions (second conductivity type impurities / second conductivity type impurities) are implanted at a dose of 1 to perform channel doping (channel doping step / first impurity introduction step).
[0445]
As a result, the silicon films 10a, 20a, 30a, and 40a become low-concentration second conductivity type silicon films 10a, 20a, 30a, and 40a having an impurity concentration of about 1 × 10 17 cm −3.
[0446]
Next, as shown in FIG. 26B, the second conductive type driving circuit TFT 30 to be formed later is covered while the formation regions of the first conductive type pixel TFT 10 and the first conductive type driving circuit TFT 20 are covered. A resist mask 1401 is formed so as to cover a region where the gate electrode 35 is to be formed widely (first mask formation step).
[0447]
Subsequently, for example, boron ions (second conductivity type impurities / second conductivity type impurities) are about 1 × 10 5.¹⁵cm^-2(2nd impurity introduction step / high concentration second conductivity type impurity introduction step).
[0448]
As a result, in the low-concentration second conductivity type silicon film 30a, the region in which high-concentration boron ions are implanted has an impurity concentration of about 1 × 10.²⁰cm^-3High concentration source / drain regions 312, 322. The low-concentration second conductivity type silicon film 40a also has an impurity concentration of about 1 × 10.²⁰cm^-3The high-concentration second conductivity type lower electrode portion 40f. Thereafter, the resist mask 1401 is removed.
[0449]
Next, as shown in FIG. 26C, gate electrodes 15, 25, and 35 made of doped silicon, a silicide film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34. At the same time, an upper electrode portion 45 is formed on the surface of the dielectric film 44 (gate electrode forming step). The upper layer side electrode unit 45 may be a part of the previous signal line. In this way, the storage capacitor 40 is formed in which the lower electrode portion 40f and the upper electrode portion 45 are opposed to each other with the dielectric film 44 interposed therebetween.
[0450]
Next, a resist mask 1402 is formed to cover the formation regions of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 (second mask formation step).
[0451]
Next, about 3 × 10 boron ions¹³cm^-2(3rd impurity introduction step / low concentration second conductivity type impurity introduction step).
[0452]
As a result, the low-concentration second conductivity type silicon film 30a sandwiched between the high-concentration source / drain regions 312 and 322 has an impurity concentration of about 3.1 × 10 10 in a self-aligned manner with respect to the gate electrode 35.¹⁸cm^-3Low concentration source / drain regions 311 and 321 are formed. A portion where no impurity is introduced becomes a channel region 33. In this way, the second conductivity type driving circuit TFT 30 is formed. Thereafter, the resist mask 1402 is removed.
[0453]
Next, as shown in FIG. 26 (d), phosphorus ions are added by about 1 × 10 without forming a mask.¹³cm^-2(4th impurity introduction step / low concentration first conductivity type impurity introduction step).
[0454]
As a result, the low-concentration second conductivity type silicon films 10a and 20a have an impurity concentration of about 0.9 × 10 5 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23.
[0455]
Here, phosphorus ions are also implanted into the low-concentration source / drain regions 311 and 321 at a dose of about 1 × 10 13 cm −2, but the impurity concentration of the low-concentration source / drain regions 311 and 321 is about 3. 1 × 10¹⁸cm^-3It is. Therefore, the low concentration source / drain regions 311 and 321 substantially have an acceptor type impurity concentration of about 2.1 × 10 6.¹⁸cm^-3However, the conductivity type is not reversed.
[0456]
Next, as shown in FIG. 26E, a resist mask 1403 that covers the formation regions of the second-conductivity-type driving circuit TFT 30 and the storage capacitor 40 and covers the gate electrodes 15 and 25 wide is formed. Third mask formation step).
[0457]
Subsequently, phosphorus ion is about 1 × 10¹⁵cm^-2(5th impurity introduction step / high concentration first conductivity type impurity introduction step).
[0458]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed. Further, in the low-concentration first conductivity type source / drain regions 11, 12, 21, and 22, the portion covered with the resist mask 1403 has an impurity concentration of about 0.9 × 10 as it is.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1403 is removed.
[0459]
Thereafter, as shown in FIG. 23, after forming the interlayer insulating film 4, annealing for activation is performed, and then contact holes are formed to form the source / drain electrodes 16, 17, 26, 27, 36, If 37 is formed, a semiconductor device such as the active matrix substrate 1 can be manufactured through three mask formation steps for forming the resist masks 1401 to 1403 and five impurity introduction steps.
[0460]
Thus, in the method of manufacturing the active matrix substrate 1 of this example, as shown in FIG. 26B, before forming the gate electrodes 15, 25, and 35 and the upper layer side electrode 45, A high-concentration second conductivity type impurity introduction step for forming the drain regions 312 and 322 is performed, and the lower layer side electrode portion 40f is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0461]
In addition, as shown in FIG. 26D, in the step for forming the low concentration source / drain regions 111, 121, 211, and 221, phosphorus ions are implanted without forming a mask. Therefore, each TFT and the storage capacitor 40 can be manufactured by three mask formation steps and five impurity introduction steps.
[0462]
Note that the manufacturing method of this example corresponds to a method in which the high concentration first conductivity type impurity introduction step and the high concentration second conductivity type impurity introduction step are interchanged in the manufacturing method according to the ninth embodiment. Prior to forming the electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. If the lower electrode portion 40f is to be formed, “N” of the 24 process orders shown in Table 7⁺ A high concentration first conductivity type impurity introduction step indicated by⁺ Any sequence of steps may be used in which the high-concentration second conductivity type impurity introduction step shown in FIG.
[0463]
[Example 16]
FIG. 27 is a cross-sectional view schematically showing the structure of an active matrix substrate with a built-in drive circuit in the liquid crystal display device of this example. In the active matrix substrate of this example, the basic structure of each TFT is substantially the same as that of the active matrix substrate shown in FIG.
[0464]
In FIG. 27, the first conductive type driving circuit TFT 20 and the first conductive type pixel TFT 10 also have an LDD structure in the active matrix substrate 1 with a built-in driving circuit of the liquid crystal display device of this example. It has become.
[0465]
On the other hand, the second conductivity type driving circuit TFT 30 ′ has an offset gate structure, and the offset regions 311 ′ and 321 ′ have an impurity concentration of about 1 × 10 6 like the channel region 33.¹⁷cm^-3It is a low-concentration second conductivity type region.
[0466]
In this example, the lower electrode portion 40d of the storage capacitor 402 has an impurity concentration of 1 × 10 5 simultaneously formed with the high concentration source / drain regions 312 and 322 of the second conductivity type driving circuit TFT 30 ′.²⁰cm^-3It is a high concentration second conductivity type region.
[0467]
The active matrix substrate 1 having such a structure can be manufactured by the following method.
[0468]
First, as shown in FIG. 28A, after forming island-like silicon films 10a, 20a, 30a, and 40a on the surface of the insulating substrate 2 (silicon film forming step), the gate insulating films 14, 24, 34, Then, the dielectric film 44 is formed (gate insulating film forming step).
[0469]
Next, 1 × 10¹²cm^-2Channel doping is performed by implanting boron ions at a dose of (channel doping step / first impurity introduction step).
[0470]
Next, as shown in FIG. 28 (b), the formation region of the first conductivity type pixel TFT 10 and the first conductivity type drive circuit TFT 20 is covered and the second conductivity type drive circuit TFT 30 'is formed. Of the region, a resist mask 1501 is formed to cover a region where a gate electrode 35 to be formed later is to be formed (first mask formation step).
[0471]
Subsequently, a second conductivity type impurity such as boron ion is about 1 × 10¹⁵cm^-2(2nd impurity introduction step / high concentration second conductivity type impurity introduction step).
[0472]
As a result, the low concentration second conductivity type silicon film 30a has an impurity concentration of 1 × 10 5.²⁰cm^-3High concentration source / drain regions 312 and 322 are formed. On the other hand, the portion of the low concentration second conductivity type silicon film 30a covered with the resist mask 1501 has an impurity concentration of about 1 × 10 5 as it is.¹⁷cm^-3Offset regions 311 'and 321'. Of course, the channel region 33 has an impurity concentration of about 1 × 10 5.¹⁷cm^-3The low-concentration second conductivity type region remains. The silicon film 40a has an impurity concentration of about 1 × 10.²⁰cm^-3The high-concentration second conductivity type lower electrode portion 40f. Thereafter, the resist mask 1501 is removed.
[0473]
Next, as shown in FIG. 28C, the gate electrodes 15, 25, and 35 and the upper layer side electrode portion 45 are formed. In this way, the storage capacitor 40 is formed.
[0474]
Next, a resist mask 1502 is formed to cover the formation region of the second conductivity type driving circuit TFT 30 and the storage capacitor 40 (second mask formation step).
[0475]
In this state, phosphorus ion is 1 × 10¹³cm^-2Are implanted at a low dose (low-concentration first conductivity type impurity introduction step / third impurity introduction step).
[0476]
As a result, the low-concentration first conductivity type silicon films 10a and 20a have an impurity concentration of about 0.9 × 10 10 in a self-aligned manner with respect to the gate electrodes 15 and 25.¹⁸cm^-3Low concentration first conductivity type source / drain regions 11, 12, 21, and 22 are formed. The portions where impurities are not introduced become channel regions 13 and 23. In this manner, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1502 is removed.
[0477]
Next, as shown in FIG. 28D, a resist mask 1503 is formed which covers the formation regions of the second-conductivity-type driving circuit TFT 30 and the storage capacitor 40 and covers the gate electrodes 15 and 25 wider. (Third mask formation step).
[0478]
In this state, phosphorus ion is 1 × 10¹⁵cm^-2Are implanted at a high dose (high-concentration first conductivity type impurity introduction step / fourth impurity introduction step).
[0479]
As a result, the impurity concentration in the low concentration first conductivity type source / drain regions 11, 12, 21, 22 is 1 × 10 5.²⁰cm^-3High concentration source / drain regions 112, 122, 212, and 222 are formed. On the other hand, the portion of the low concentration first conductivity type source / drain region 11, 12, 21, 22 covered with the resist mask 1503 has an impurity concentration of about 0.9 × 10.¹⁸cm^-3Low concentration source / drain regions 111, 121, 211, and 221. In this way, the first conductivity type pixel TFT 10 and the first conductivity type driving circuit TFT 20 are formed. Thereafter, the resist mask 1503 is removed.
[0480]
Therefore, the active matrix substrate 1 can be manufactured through three mask formation steps for forming the resist masks 1503 to 1503 and four impurity introduction steps.
[0481]
Thus, in the manufacturing method of the active matrix substrate 1 of this example, as shown in FIG. 28B, before forming the gate electrodes 15, 25, 35 and the upper layer side electrode 45, the high concentration source / drain is formed. A high-concentration second conductivity type impurity introduction step for forming the regions 311 and 321 is performed, and the lower layer side electrode portion 40f is formed by using this step. Therefore, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0482]
Further, in this example, as shown in FIG. 28C, in the second conductivity type driving circuit TFT 30 ′, when the portion facing the gate electrode 35 is set to the low concentration region, not the LDD structure but the offset. It is a gate structure. For this reason, as compared with the third embodiment, both the mask formation step and the impurity introduction step are less each time. That is, as compared with the conventional manufacturing method, both the mask formation step and the impurity introduction step are less twice. Therefore, the electrical characteristics of the TFT in the pixel region and the drive circuit portion can be improved with the smallest number of manufacturing steps.
[0483]
The manufacturing method of this example corresponds to a method in which the high concentration first conductivity type impurity introduction step and the high concentration second conductivity type impurity introduction step are interchanged in the manufacturing method according to the tenth embodiment. Prior to forming the electrodes 15, 25, 35 and the upper layer side electrode 45, a high-concentration second conductivity type impurity introduction step for forming the high-concentration source / drain regions 312, 322 is performed. If the lower electrode portion 40f is to be formed, “N” of the 10 process sequences shown in Table 8 will be used.⁺ High concentration first conductivity type impurity introduction step indicated by⁺ Any sequence of steps may be used in which the high-concentration second conductivity type impurity introduction step shown in FIG.
[0484]
[Modifications of Embodiment 3 to Embodiment 16]
As the impurity introduction method, for example, a method of implanting all ions generated from the dopant gas without mass separation, a so-called ion doping method may be used. In this method, for example, when implanting the first conductivity type impurity at a high concentration, a mixed gas containing about 5% of PH3 and the balance of hydrogen gas is used, and all ions generated from the mixed gas are massed. Type in without separation. On the other hand, when the impurity of the first conductivity type is implanted at a low concentration, PH_Three Is implanted without mass separation of all the ions generated from the mixed gas consisting of hydrogen gas, and the remainder is implanted without mass separation. It is preferable to terminate the asymmetric bond. In addition to the ion implantation method or the ion doping method, a plasma doping method, a laser doping method, or the like may be used as the impurity introduction method. Further, the mask material is not limited to a resist mask. In any form, the first conductivity type is N-type and the second conductivity type is P-type. That is, the pixel TFT may be a P-type.
[0485]
【The invention's effect】
As described above, in the semiconductor device according to the present invention, each TFT has a low concentration region in the portion facing the end portion of the gate electrode in the low concentration region. Further, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened, so that high speed operation is possible. Further, in the second conductivity type driving circuit TFT, the low concentration region facing the end portion of the gate electrode is formed as an offset region having the same impurity concentration as the channel region. Accordingly, the mask formation process and the impurity introduction process can be reduced by one time each, compared with the case where all TFTs are manufactured with the LDD structure. Therefore, a semiconductor device capable of improving the electrical characteristics of each TFT can be realized with a minimum number of manufacturing steps.
[0486]
In particular, when the semiconductor device according to the present invention is applied to an active matrix substrate with a built-in drive circuit, TFTs that are less likely to cause display unevenness can be formed in the pixel region, while malfunctions occur in the drive circuit portion. It is difficult to form a TFT with a small current passing between the power supply terminals of the CMOS circuit. For example, the electrical characteristics of the TFT can be improved for each pixel region and the drive circuit portion.
[0487]
In the present invention, the second conductivity type thin film transistor is configured such that the second conductivity type TFT having an offset structure is configured as a weak depletion mode and the first conductivity type TFT having an LDD structure is configured as a weak enhancement mode. In general, when the impurity concentration of the second conductivity type is set in the channel region and the offset region of the TFT, the TFT with the offset structure tends to be smaller in the ON state than the TFT with the LDD structure. According to the invention, even when a gate voltage having the same absolute value is applied, a large gate bias voltage is applied to the second conductivity type TFT as compared with the first conductivity type TFT. The on-current balance can be secured. In addition, since it is realized by the impurity concentration of the second conductivity type in the channel region and the offset region of the second conductivity type thin film transistor, the balance of the transistor capacitance can be ensured. Therefore, a CMOS circuit capable of high-speed operation can be configured.
[0488]
In the present invention, the second conductivity type impurity concentration included in the channel region of the first conductivity type TFT, the second conductivity type impurity concentration included in the channel region of the second conductivity type TFT, and the offset of the second conductivity type TFT. When the second conductivity type impurity concentration contained in the region is all made equal, that is, when the second conductivity type impurity is introduced into the channel region of the second conductivity type TFT, the second conductivity type impurity is also introduced into the channel region of the first conductivity type TFT. When the type impurity is introduced, the second conductivity type impurity can be introduced into the channel region without using a mask, so that the number of steps can be reduced.
[0489]
In the present invention, before forming one electrode of the capacitor element on the upper layer of the semiconductor film, an impurity introduction step for forming a low concentration source / drain region or a high concentration source / drain region of the TFT is performed. The process is characterized in that impurities are introduced into a semiconductor film for forming a capacitor element to form the other electrode of the capacitor element. Therefore, according to the present invention, the number of mask forming steps and the number of impurity introducing steps can be reduced as compared with the conventional manufacturing method.
[0490]
In forming the low concentration source / drain regions of the TFT, when the offset gate structure is used, the mask formation process and the impurity introduction process can be reduced once each as compared with the LDD structure.
[0491]
A low-concentration first conductivity type in which a low-concentration source / drain region of the first conductivity type thin film transistor is introduced together with a first conductivity-type impurity and a second conductivity-type impurity equivalent to the low-concentration source / drain region of the second conductivity type thin film transistor. When configured as a region, the substantial impurity concentration can be changed between the low concentration source / drain region and the first electrode portion.
[0492]
A step of introducing a low-concentration first-conductivity-type impurity to form a low-concentration source / drain region of the first-conductivity-type thin film transistor; and a low-concentration to form a low-concentration source-drain region of the second-conduction-type thin-film transistor One of the steps of introducing the second conductivity type impurity is performed without forming a mask, and the conductivity type and impurity concentration of the region into which both of the first and second conductivity type impurities are introduced are In the case where it is defined by the difference between the introduction amounts of the first and second conductivity type impurities, the mask forming process can be further reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 1 of the present invention.
2A is an explanatory diagram of a semiconductor device such as an active matrix substrate of the liquid crystal display device using the TFT shown in FIG. 1, and FIG. 2B is an explanatory diagram of a CMOS circuit used for its drive circuit. .
3 is a graph showing comparison of on / off current characteristics of TFTs on a semiconductor device such as an active matrix substrate shown in FIG. 1. FIG.
4A to 4D are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as the active matrix substrate shown in FIG.
FIGS. 5A to 5D are process cross-sectional views showing another method for manufacturing the semiconductor device such as the active matrix substrate shown in FIG.
FIG. 6 is a graph showing comparison of on / off current characteristics of TFTs formed on a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 2 of the present invention.
FIG. 7 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiments 3 to 5 of the present invention.
FIG. 8 is an explanatory diagram illustrating a structure of a storage capacitor configured in a semiconductor device such as an active matrix substrate of a liquid crystal display device.
FIGS. 9A to 9E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 3 of the present invention. FIGS.
FIGS. 10A to 10E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 4 of the present invention. FIGS.
11A to 11E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 5 of the present invention.
FIG. 12 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 6 of the present invention.
FIGS. 13A to 13D are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 6 of the present invention. FIGS.
FIG. 14 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 7 of the invention.
15A to 15E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 7 of the present invention.
16A to 16E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 8 of the present invention.
FIGS. 17A to 17E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 9 of the present invention. FIGS.
FIG. 18 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 10 of the present invention.
FIGS. 19A to 19D are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 10 of the present invention. FIGS.
20 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Example 11 of the present invention. FIG.
21A to 21E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 11 of the present invention.
FIGS. 22A to 22E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 12 of the present invention. FIGS.
FIG. 23 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 13 of the present invention.
24A to 24E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 13 of the present invention.
25A to 25E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 14 of the present invention.
26A to 26E are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 15 of the present invention.
FIG. 27 is a cross-sectional view schematically showing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 16 of the present invention.
FIGS. 28A to 28D are process cross-sectional views illustrating a method for manufacturing a semiconductor device such as an active matrix substrate of a liquid crystal display device according to Embodiment 16 of the present invention. FIGS.
FIG. 29 is a cross-sectional view schematically showing a conventional semiconductor device such as an active matrix substrate.
FIG. 30 is a graph showing the on / off leakage current characteristics of a self-aligned TFT.
31A is a graph showing the relationship between the channel length and the withstand voltage between the source and drain in an N-type TFT, and FIG. 31B is the channel length and source in a P-type TFT. -It is a graph which shows the relationship with the withstand voltage between drains.
FIG. 32 is a graph showing on / off leakage current characteristics of a TFT having an LDD structure.
FIGS. 33A to 33F are process cross-sectional views illustrating a method of manufacturing a semiconductor device such as an active matrix substrate shown in FIG.
[Explanation of symbols]
1, 1 ″ ・ ・ ・ Active matrix substrate (semiconductor device)
2 ... Insulating substrate
10, 10 ″ ・ ・ ・ N type TFT for pixel
20, 20 ″ ・ ・ ・ N type TFT for driving circuit
30, 30 ', 30 "... P-type drive circuit TFT
n1, n2 ... N-type TFT
p1, p2 ... P-type TFT
11, 12, 21, 22, 31, 32... Source / drain regions
13, 23, 33 ... channel region
14, 24, 34 ... gate insulating film
15, 25, 35 ... gate electrodes
82 ... Data driver section (drive circuit)
83 ... Scanning driver section (drive circuit)
84, 88... Shift register
85, 89 ... Level shifter
90 ... Signal line
91 ... Scanning line
92 ... TFT for pixel
111, 121, 211, 221, 311, 321... Low concentration source / drain regions
311 ', 321' ... Offset area

Claims (5)

A first-conductivity-type thin film transistor comprising a first channel region and a first-conductivity-type high-concentration source / drain region facing the first gate electrode with a first-gate insulating film positioned below the first-gate electrode; A semiconductor device having a second channel region facing a gate electrode through a second gate insulating film and positioned below the second gate electrode and a second conductivity type thin film transistor having a second conductivity type high concentration source / drain region In
The first conductivity type thin film transistor has an LDD structure including a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region. The region contains a very low concentration of second conductivity type impurities,
The second conductivity type thin film transistor has an offset structure including an offset region having the same impurity concentration as the second channel region between the second conductivity type high concentration source / drain region and the second channel region, The second channel region contains the same very low concentration second conductivity type impurity as the first channel region of the first conductivity type transistor,
The source / drain voltage of the first conductive thin film transistor is V _DS1 , the gate voltage is V _GS1 , the source / drain current is I _DS1 , the source / drain voltage of the second conductive thin film transistor is V _DS2 , and the gate voltage is V _GS2. When the source / drain current is I _DS2 , so that I _DS2 > I _DS1 under the condition of | V _DS1 | = | V _DS2 | and V _GS1 = V _GS2 = 0, or | V _DS1 | = The gate voltage when I _DS2 = I _DS1 under the condition of | V _DS2 | and V _GS1 = V _GS2 is shifted from 0 V to the direction in which the first conductive thin film transistor is turned on. A semiconductor device characterized in that second conductivity type impurity concentrations of the second channel region and the offset region are determined. A first-conductivity-type thin film transistor comprising a first channel region and a first-conductivity-type high-concentration source / drain region facing the first gate electrode with a first-gate insulating film positioned below the first-gate electrode; A semiconductor device having a second channel region facing a gate electrode through a second gate insulating film and positioned below the second gate electrode and a second conductivity type thin film transistor having a second conductivity type high concentration source / drain region In
The first conductivity type thin film transistor has an LDD structure including a first conductivity type low concentration source / drain region between the first conductivity type high concentration source / drain region and the first channel region. The region contains a very low concentration of first conductivity type impurities,
The second conductivity type thin film transistor has an offset structure including an offset region having the same impurity concentration as the second channel region between the second conductivity type high concentration source / drain region and the second channel region, The second channel region contains the same extremely low concentration first conductivity type impurity as the first channel region of the first conductivity type transistor,
The source / drain voltage of the first conductive thin film transistor is V _DS1 , the gate voltage is V _GS1 , the source / drain current is I _DS1 , the source / drain voltage of the second conductive thin film transistor is V _DS2 , and the gate voltage is V _GS2. When the source / drain current is I _DS2 , so that I _DS2 > I _DS1 under the condition of | V _DS1 | = | V _DS2 | and V _GS1 = V _GS2 = 0, or | V _DS1 | = The gate voltage when I _DS2 = I _DS1 under the condition of | V _DS2 | and V _GS1 = V _GS2 is shifted from 0 V to the direction in which the first conductive thin film transistor is turned on. A semiconductor device characterized in that a first conductivity type impurity concentration of the second channel region and the offset region is determined. An active matrix substrate using the semiconductor device defined in claim 1 or 2,
The first conductivity type thin film transistor and the second conductivity type thin film transistor constitute a CMOS circuit in a drive circuit region,
An active matrix substrate, wherein one of the first conductivity type thin film transistor and the second conductivity type thin film transistor forms a pixel thin film transistor in a pixel region. In the manufacturing method of the semiconductor device according to claim 1,
A very low concentration second conductivity type impurity introducing step of introducing a second conductivity type impurity into the semiconductor film at a very low concentration to form the first channel region, the second channel region, and the offset region;
A gate electrode forming step of forming the first gate electrode and the second gate electrode;
A low concentration first conductivity type impurity introduction step for introducing a first conductivity type impurity into the semiconductor film at a low concentration to form the first conductivity type low concentration source / drain region;
A high concentration first conductivity type impurity introduction step for introducing a first conductivity type impurity into the semiconductor film at a high concentration to form the first conductivity type high concentration source / drain region;
A high concentration second conductivity type impurity introduction step for introducing a second conductivity type impurity into the semiconductor film at a high concentration to form the second conductivity type high concentration source / drain region;
The very low concentration second conductivity type impurity introduction step is performed before the gate electrode formation step, and the low concentration first conductivity type impurity introduction step is performed after the gate electrode formation,
In the step of introducing the very low concentration second conductivity type impurity, the source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain current is I _DS1 . the source-drain voltage V _DS2, the gate voltage V _GS2, the source-drain current when the _{I DS2 | V DS1 | = |} V DS2 |, and V _GS1 = V _GS2 = at 0 under the conditions of I _DS2> as becomes a I _DS1, or _{| V DS1 | = | V DS2} |, said first conductivity type thin film transistor gate voltage from 0V when serving as the I _DS2 = I _DS1 and under conditions of V _GS1 = V _GS2 A method of manufacturing a semiconductor device, wherein impurities are introduced by determining a second conductivity type impurity concentration of the second channel region and the offset region so as to shift in an on state. In the manufacturing method of the semiconductor device according to claim 2,
A very low concentration first conductivity type impurity introduction step for introducing a first conductivity type impurity into the semiconductor film at a very low concentration to form the first channel region, the second channel region, and the offset region;
A gate electrode forming step of forming the first gate electrode and the second gate electrode;
A low concentration first conductivity type impurity introduction step for introducing a first conductivity type impurity into the semiconductor film at a low concentration to form the first conductivity type low concentration source / drain region;
A high concentration first conductivity type impurity introduction step for introducing a first conductivity type impurity into the semiconductor film at a high concentration to form the first conductivity type high concentration source / drain region;
A high concentration second conductivity type impurity introduction step for introducing a second conductivity type impurity into the semiconductor film at a high concentration to form the second conductivity type high concentration source / drain region;
The very low concentration first conductivity type impurity introduction step is performed before the gate electrode formation step, and the low concentration first conductivity type impurity introduction step is performed after the gate electrode formation,
In the step of introducing the very low concentration first conductivity type impurity, the source / drain voltage of the first conductivity type thin film transistor is V _DS1 , the gate voltage is V _GS1 , and the source / drain current is I _DS1 . the source-drain voltage V _DS2, the gate voltage V _GS2, the source-drain current when the _{I DS2 | V DS1 | = |} V DS2 |, and V _GS1 = V _GS2 = at 0 under the conditions of I _DS2> as becomes a I _DS1, or _{| V DS1 | = | V DS2} |, said first conductivity type thin film transistor gate voltage from 0V when serving as the I _DS2 = I _DS1 and under conditions of V _GS1 = V _GS2 A method of manufacturing a semiconductor device, wherein impurities are introduced by determining a first conductivity type impurity concentration of the second channel region and the offset region so as to shift in an ON state.

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