JP2682528B2 - Active matrix panel - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel having a complementary thin film transistor in which a P channel thin film transistor and an N channel thin film transistor are integrated. [0002] In recent years, active research has been conducted on a technique for forming a thin film transistor on an insulating substrate. This technology is based on an active matrix panel that realizes a high-quality thin display using an inexpensive transparent insulating substrate, a three-dimensional integrated circuit that forms active elements such as transistors on a normal semiconductor integrated circuit, or an inexpensive high-performance integrated circuit. Many applications are expected, such as high-performance image sensors or high-density memories. Some of these applications basically use a thin film transistor only as a switching element. However, it is desirable that a driving circuit necessary for the switching is simultaneously formed by the thin film transistor. For example, in an active matrix panel, a thin film transistor is arranged in each of the pixels arranged in a matrix to perform switching of display data. At the same time, if the peripheral driving circuit can be integrated with the thin film transistor, the burden of mounting can be reduced and The cost and size of the entire system can be reduced. That is, it is necessary to form a logic circuit with thin film transistors. In this case, a complementary structure (CMOS) is required more than in a normal semiconductor integrated circuit. this is,
This is because, when a logic circuit is formed using thin film transistors, the number of elements is generally increased, and power consumption becomes extremely large unless a complementary structure is adopted. For example, when a peripheral drive circuit of an active matrix panel is built with thin film transistors, a number of shift registers and buffers corresponding to the number of pixels, analog switches, or the like are required. In general, a shift register having 500 or more stages must be built in. It can be easily analogized that a large number of elements are required in the case of a three-dimensional integrated circuit, an image sensor, a high-density memory, and the like. When the number of elements is large, it is extremely effective to make the thin film transistors complementary in order to reduce the power consumption. The complementary thin film transistor includes a P-channel thin film transistor and an N-channel thin film transistor. Of these thin film transistors,
Since one of them is always in the off state, the through current does not flow between the power supplies, and the power consumption can be significantly reduced. However, the complementary type thin film transistor has the following disadvantages, and has not been sufficiently studied conventionally. (1) The manufacturing method is complicated because both the P-channel type and the N-channel type are integrated. (2) The manufacturing cost is accordingly high. (3) The characteristics of the thin film transistor are not well balanced. (4) It is difficult to match the characteristics of the P-channel type thin film transistor and the characteristics of the N-channel type thin film transistor. (5) In order to have these characteristics, it is necessary to add extra steps such as adding appropriate impurities to the channel portion. Due to these drawbacks, complementary thin film transistors have not reached the level of practical use. The present invention is intended to eliminate such drawbacks all at once, and an object of the present invention is to provide P with excellent characteristics and small difference in characteristics. It is an object to provide a complementary thin film transistor including a channel type and an N channel type thin film transistor at low cost by a simple manufacturing method. According to the present invention, in an active matrix panel having a complementary thin film transistor including a first conductive type thin film transistor and a second conductive type thin film transistor, channels of the first and second conductive type thin film transistors are provided. The regions are formed of non-single-crystal silicon deposition films of the same layer, and the silicon film thickness of each channel region of the first and second conductivity type thin film transistors is thinner than any of the maximum widths of the depletion layer that can spread in each thin film transistor. It is characterized by being formed. Embodiment 1 Hereinafter, the present invention is characterized in that a channel region is composed of a non-doped silicon thin film and a P-channel or N-channel thin film transistor is realized depending on the conductivity type of source / drain. The complementary thin film transistor will be described in detail based on examples. FIG. 1 is a sectional view showing the structure of a complementary thin film transistor according to the present invention. 101 is glass, quartz,
An insulating substrate such as a semiconductor integrated circuit substrate including a passivation film, on which a P-channel thin film transistor 1 is provided.
02 and the N-channel type thin film transistor 103 are formed to form a complementary type thin film transistor. 10
Reference numeral 4 denotes a channel region of a P-channel thin film transistor formed of a non-doped silicon thin film. Reference numeral 105 denotes a source region formed of a P-type silicon thin film doped with an acceptor such as boron, and reference numeral 106 denotes a drain region having the same configuration. 107 is a gate insulating film such as Sio _2.
08 is a gate electrode made of polycrystalline silicon, metal, or the like, 109
Is an interlayer insulating film such as Sio ₂ . Reference numerals 110 and 111 are made of a conductor such as a metal, and are a source electrode and a drain electrode, respectively. Reference numeral 112 denotes a channel region of an N-channel type thin film transistor made of a non-doped silicon thin film. Reference numeral 113 denotes a source region made of an N-type silicon thin film doped with a donor such as phosphorus or arsenic, and reference numeral 114 denotes a drain region having the same configuration. 115 is a gate insulating film, 116 is a gate electrode, 117 is a source electrode, 118
Is a drain electrode. As is apparent from this figure, the present invention uses both undoped silicon thin films as the channel regions of the P-channel type and N-channel type thin film transistors, and basically, the P-channel type thin transistor and the N-channel type thin film transistor are A major feature is that they are distinguished only by the conductivity type of the source / drain regions. The effects of the present invention realized by these features will be described below. First, the effect of using non-doped silicon thin films as the channel regions of the P-channel type and N-channel type thin film transistors will be described. By using a non-doped silicon thin film, that is, a silicon thin film close to an intrinsic semiconductor, as the channel regions of both types of thin film transistors, a leak current (hereinafter referred to as O
FF current) can be minimized. In a normal transistor using single crystal silicon, an OFF current between a source and a drain is formed by forming an extremely high-quality PN junction using a P-type substrate for an N-channel type and an N-type substrate for a P-channel type. In general, single crystallization cannot be performed with a silicon thin film on an insulating substrate, and a polycrystalline state or an amorphous state is obtained.
A junction cannot be formed, and thus the OFF current cannot be reduced. FIG. 2 is data of an experiment conducted by the present applicant and is a graph showing the relation between the impurity concentration in the silicon thin film in the channel region of the N-channel thin film transistor and the OFF current. The impurity is boron, which is intended to make the channel region P-type. The doping is performed by an ion implantation method, and the horizontal axis of the graph is the doping amount of boron and the vertical axis is the OFF current at the gate voltage of OV. As can be seen from this graph, when the doping amount is 0, that is, when the non-doped silicon thin film close to the intrinsic semiconductor is used, the OFF current is minimized. This is because the leakage current of the PN junction increases as the impurity concentration increases. On the other hand, when the channel region is N-type, the transistor becomes a depletion type, needless to say, and the OFF current increases. Therefore, when a non-doped silicon thin film is used, the OFF current is minimized. That is, in order to reduce the OFF current, it is effective to increase the resistance of the channel region as much as possible, instead of using a PN junction as in a transistor using single crystal silicon. Although the above description has been made for an N-channel thin film transistor, the same holds true for a P-channel thin film transistor. Therefore, both types of thin film transistors can minimize the OFF current by using a non-doped silicon thin film for the channel region. Next, a P-channel type thin film transistor and N
The effect of distinguishing channel type thin film transistors only by the conductivity type of the source / drain regions will be described. Thereby, the manufacturing process of the complementary thin film transistor can be significantly simplified. Therefore, a significant improvement in yield and a reduction in cost can be realized. FIG. 3 is a diagram showing an example of a method for manufacturing the complementary thin film transistor shown in FIG. First, as shown in FIG. 3A, the insulating substrate 30
After depositing the non-doped silicon thin films 302 and 303 on 1, a desired pattern is formed. A P-channel thin film transistor is formed at 302, and an N-channel thin film transistor is formed at 303. Next, as shown in FIG. 3B, a gate insulating film 304 is formed by thermally oxidizing the non-doped silicon thin films 302 and 303. Alternatively, a gate insulating film may be externally deposited by a vapor deposition method or the like. After that, the gate electrode 305 is deposited,
A desired pattern is formed. Of course, different gate electrode materials may be used for the P-channel thin film transistor and the N-channel thin film transistor, such as the P-type silicon thin film and the N-type silicon thin film. Next, as shown in FIG. 3C, a mask material 306 such as a photoresist is formed in a region to be an N-channel type thin film transistor, and an acceptor element 307 such as boron is ion-implanted into a P-channel type thin film transistor. A P-type silicon thin film which becomes the source region 308 and the drain region 309 is formed by doping the inside. Further, as shown in FIG. 3D, similarly, a mask material 310 such as a photoresist is formed in a region to be a P-channel thin film transistor, and a donor element 3 such as phosphorus or arsenic
11 is doped into an N-channel thin film transistor by an ion implantation method to form an N-type silicon thin film to be a source region 312 and a drain region 313. Finally, as shown in FIG. 3E, a contact hole is opened after the interlayer insulating film 314 is deposited, and the source electrode 315 and the drain electrode 316 of the P-channel type thin film transistor are formed.
The source electrode 317 and the drain electrode 318 of the channel type thin film transistor are formed, and the complementary type thin film transistor is completed. As can be seen, the complementary thin film transistor according to the present invention can be manufactured by a very simple method.
This is because both the P-channel type thin film transistor and the N-channel type thin film transistor use a non-doped silicon thin film as a channel region. Therefore, it is not necessary to use an N-type substrate for the P-channel transistor and a P-type substrate for the N-channel transistor, unlike the conventional complementary transistor. That is, it is not necessary to change the conductivity type of the channel region in the two types of transistors. As a result, it is possible to omit the step of adding an impurity to the channel region of each transistor and forming a necessary pattern. In addition, each transistor is separated into islands on the insulating substrate, and no special element separation process is required. Further, along with this, there is no parasitic MOS effect as in a normal semiconductor integrated circuit, and it is not necessary to form a channel stopper.
For these reasons, in the thin film transistor according to the present invention, P-channel type and N-channel type thin film transistors can be realized only by changing the conductivity type of the source / drain regions. Therefore, the manufacturing process thereof is extremely simple as compared with the conventional complementary transistor. For example, the number of pattern forming steps is 10 or more in the conventional complementary transistor, but only 6 in the complementary transistor according to the present invention. The fact that the manufacturing process can be simplified in this way has a great effect that the manufacturing cost can be reduced and the manufacturing yield can be improved, and a significantly low cost can be achieved as a whole. Further, according to the present invention, the silicon thin films in the channel regions of both the P-channel type thin film transistor and the N-channel type thin film transistor are formed of the same layer, and the thickness of the silicon thin film is the same as that of the two types of thin film transistors. The present invention also provides a complementary thin film transistor characterized by being thinner than the maximum width of any depletion layer that can be formed on the surface of the thin film, which will be described in detail below based on examples. FIG. 4 is a sectional view showing the vicinity of the channel region of the complementary thin film transistor according to the present invention. FIG.
4A shows a P-channel thin film transistor, and FIG. 4B shows an N-channel thin film transistor.
On an insulating substrate 401, source regions 402 and 408, drain regions 403 and 409, gate insulating films 404 and 410,
A thin film transistor having gate electrodes 405 and 411 is formed. The non-doped silicon thin films 406 and 412 in the channel region are formed of the same layer, and therefore have the same thickness tsi. Depletion layers 407 and 413 spread on the surface of the silicon thin film with the application of the gate voltage. The width ΔP of the depletion layer in the P-channel type thin film transistor and the width ΔN of the depletion layer in the N-channel type thin film transistor are expressed by the following equations, respectively. Given by [Equation 1] Here, q is the unit charge amount, ε is the dielectric constant of the silicon thin film, φs is the bending amount of the energy band on the surface of the silicon thin film, and ND is equivalent to the density of traps acting as donors, that is, the channel region. Tell Denar the density. NA is equivalent to the density of traps that act as acceptors, that is, the density of acceptors that act in the channel region. As described above, the silicon thin film is in a polycrystalline or amorphous state and has many crystal defects, which act as traps. In the energy band diagram, the trap that creates a level between the Fermi level and the conduction band acts as a donor, and the trap that creates a level between the Fermi level and the valence band acts as an acceptor. The level of each trap is determined by the arrangement of silicon atoms, and ND and NA are generally not equal. FIG. 4 shows a case where ND is larger than NA and therefore χP is smaller than χN. When the gate voltage is further increased, the spread width of each depletion layer reaches a maximum value, and an inversion layer starts to be formed on the surface of the silicon thin film. The gate voltage at this time is the threshold voltage. Even if the gate voltage is further increased, the depletion layer no longer spreads, but only increases the carrier density in the inversion layer. Maximum depletion layer widths χPmax and χNm in P-channel and N-channel thin film transistors
ax and threshold voltages VthP and VthN are given by the following equations. [Equation 2] Here, φfP and φfN are the Fermi energies of P-channel and N-channel thin film transistors, Cox is the capacitance of the gate insulating film per unit area, and VFB is the flat band voltage. In the complementary thin film transistor according to the present invention, the silicon thin film tsi is formed by the above-mentioned χPmax and χNma.
It is configured to be smaller than any of x. The effects of the present invention realized by this will be described below. When the film thickness (tsi) of the silicon thin film is smaller than the maximum width (χPmax and χNmax) in which the depletion layer can spread, the depletion layer cannot spread beyond tsi. Therefore, when the depletion layer width reaches tsi, an inversion layer is immediately formed on the surface of the silicon thin film. That is, the threshold voltage of the transistor is reduced. Normally, since a very high density trap exists in a silicon thin film, the threshold voltage becomes high.
According to the present invention, by reducing the threshold voltage, the operating voltage of the thin film transistor can be lowered, and the current (ON current) flowing when the transistor is in the ON state can be increased. Therefore, the thin film transistor can be easily used, and a higher-speed operation can be performed. The threshold voltage at this time is given by the following equation. [Equation 3] In the case of the example of FIG. 4, ND> NA, χP <χN
It is. Therefore, when the tsi is reduced, the threshold voltage of the N-channel thin film transistor starts to decrease faster than that of the P-channel thin film transistor. However, when tsi is further reduced to fall within the thickness range provided by the present invention, the difference in threshold voltage between the P-channel thin film transistor and the N-channel thin film transistor becomes smaller. This is shown in FIG. The horizontal axis is tsi, and the vertical axis is the absolute value of the threshold voltage. Reference numeral 501 denotes a graph of an N-channel thin film transistor, and 502 denotes a graph of a P-channel thin film transistor. As can be seen from this graph, in a region where tsi is smaller than χPmax, the threshold voltages of the two are rapidly approaching. This is because, in the above equation, ND is larger than NA, and thus the tsi dependence of the threshold voltages of the two transistors is different. Therefore, according to the present invention, it is possible to make the threshold voltages of the P-channel type and N-channel type thin film transistors close to each other and to reduce the characteristic difference. This has a very large effect on complementary transistors. Although the above description has been made on the assumption that ND> NA, the same holds true for NA <ND. (Embodiment 2) FIG. 6 shows another embodiment of the present invention. The P-channel type thin film transistor 616 and the N-channel type thin film transistor 6 are formed on the insulating substrate 601.
17 is formed, which constitutes a complementary thin film transistor. Reference numeral 602 denotes a gate electrode, 603 denotes a gate insulating film, and 604 denotes a channel region of a P-channel thin film transistor made of a non-doped silicon thin film. 60
Reference numeral 5 is a source region made of a P-type silicon thin film doped with an acceptor such as boron, and 606 is a drain region similarly configured. 607 is an interlayer insulating film,
Reference numeral 608 is a source electrode and 609 is a drain electrode. 6
Reference numeral 10 is a gate electrode, and 611 is a channel region of an N-channel thin film transistor made of a non-doped silicon thin film. Reference numeral 612 is a source region made of an N-type silicon thin film doped with a donor such as phosphorus or arsenic.
Reference numeral 3 is a drain region having the same structure. Reference numeral 614 is a source electrode and 6I5 is a drain electrode. As is apparent from the figure, all the effects of the present invention described above are also established in this embodiment. In other words, the present invention is established even if the channel region is located above the gate electrode, or the silicon thin film of the source / drain region is formed of a layer different from the silicon thin film of the channel region, or the accompanying structure changes. The same effect can be obtained. [Summary of Effects of Embodiment] As described above, the embodiment has the following effects. (1) Since the non-doped silicon thin film is used in the channel region, the OFF current of the thin film transistor can be minimized. (2) Since the non-doped silicon thin film is used for the channel region, the P-channel type thin film transistor and the N-channel type thin film transistor can be separately formed only by the conductivity type of the source / drain regions, and the complementary type thin film transistor can be very easily formed. realizable. (3) Since the film thickness of the silicon thin film is smaller than the maximum width in which the depletion layer can spread, the threshold voltage of the thin film transistor is lowered and the ON current is increased to enable a higher speed operation. be able to. (4) The thickness of the silicon thin film is set to the maximum width in which the depletion layer of the P-channel thin film transistor can spread and N
Since it is smaller than any of the maximum widths of the depletion layer of the channel type thin film transistor that can spread, the characteristics of both thin film transistors can be remarkably improved and the difference between both characteristics can be reduced. As described above, according to the present invention, in the active matrix panel having the complementary thin film transistor including the first conductive type thin film transistor and the second conductive type thin film transistor, the first and second conductive type thin film transistors are provided. Of the first and second conductivity type thin film transistors, the silicon film thickness of each of the first and second conductivity type thin film transistors is larger than the maximum width of the depletion layer that can be spread in each thin film transistor. The OFF current can be reduced by forming the thin film as well. [0049]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a first embodiment showing the manufacture of a complementary thin film transistor according to the present invention. FIG. 2 is a graph showing the relationship between the impurity concentration of the channel region and the OFF current. 3A to 3E are views showing a method of manufacturing the complementary thin film transistor according to the present invention shown in FIG. 4A and 4B are diagrams showing the vicinity of a channel region of a thin film transistor according to the present invention. FIG. 5 is a graph showing the relationship between the thickness of the silicon thin film in the channel region and the threshold voltage. FIG. 6 is a diagram showing a second embodiment showing the structure of a complementary thin film transistor according to the present invention.

Continuation of front page    (56) References JP-A-58-98970 (JP, A)                 JP-A-51-5967 (JP, A)                 JP 54-152894 (JP, A)                 JP-A-52-122484 (JP, A)                 JP-A-55-86162 (JP, A)                 Hara, et al. "The movement of MOS transistors               Theory of Work "Second Printing (Sho 56-5-1)               Modern Science Co. P. 111-118                 Electronic materials, VOL. 21, NO. 1               (Sho 57-1) P. 54-65                 SOLID STATE ELECT               RONICS, VOL. 24, NO. 12               (1981) PP. 1093−1098                 R. M. Burger et al., Translated by Sadao Kanno                 "Basics of silicon integrated device technology"               6 prints (Showa 56-3-10) Jishin Shokan               P. 243-247                 JAPANESE JOURNAL               OF APPLIED PHYSIC               S, VOL. 18 (1979) SUPPL               EMENT 18-1, PP. 57-62

Claims (1)

(57) [Claims] In an active matrix panel having a complementary thin film transistor including a first conductivity type thin film transistor and a second conductivity type thin film transistor, channel regions of the first and second conductivity type thin film transistors are formed of a non-single crystal silicon deposition film of the same layer, An active matrix panel, characterized in that the silicon film thickness of each channel region of the first and second conductivity type thin film transistors is formed to be thinner than any of the maximum widths of the depletion layer that can spread in each thin film transistor.