JP2812182B2 - Method for manufacturing complementary thin film transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary thin film transistor in which a P-channel thin film transistor and an N-channel thin film transistor are integrated on the same insulating substrate . 2. Description of the Related Art In recent years, techniques for forming a thin film transistor on an insulating substrate have been actively studied. This technology uses an active matrix panel that realizes a high-quality thin display using an inexpensive transparent insulating substrate, a three-dimensional integrated circuit that forms active elements such as transistors on a normal semiconductor integrated circuit, or an inexpensive high-performance Many applications are expected, such as simple image sensors or high-density memories. [0003] In these applications, it is required not only to use a thin film transistor as a mere data switching element, but also to constitute a logic circuit with the thin film transistor. In this case, since the number of elements generally increases,
In order to reduce power consumption, a complementary configuration (CMOS) is required. For example, when a peripheral circuit of an active matrix panel is built in a thin film transistor, shift registers, buffers, analog switches, and the like are required according to the number of pixels. Generally, 500 or more stages of shift registers must be built in . Further, it can be easily analogized that a large number of elements are required even in the case of a three-dimensional integrated circuit, an image sensor, a high-density memory, or the like. When the number of elements is large as described above, in order to reduce the power consumption, it is essential that the thin film transistors have a complementary structure. [0005] However, the complementary thin film transistor has a complicated manufacturing method because both a P-channel type and an N-channel type are integrated on the same insulating substrate .
Therefore, there is a problem that the manufacturing cost is high, and therefore, no sufficient study has been made so far, and it has not reached a practical use level. An object of the present invention is to eliminate such a problem, and an object of the present invention is to provide a complementary thin film transistor at a low cost by a simple manufacturing method. According to the present invention, there is provided a method of manufacturing a complementary type thin film transistor in which a first conductive type thin film transistor and a second conductive type thin film transistor are formed on an insulating substrate. Depositing a thin film, introducing a first dopant by ion implantation into regions of the deposited semiconductor thin film that will be the source and drain of the first and second conductivity type thin film transistors; Covering the region serving as the source / drain of the thin film transistor, and forming the first region in the region serving as the source / drain of the second conductivity type thin film transistor.
Introducing a second dopant of a type different from that of the first dopant by an ion implantation method, wherein the dose of the second dopant is at least 3 times greater than the equivalent of the dose of the first dopant. And a dose of the first dopant is within about 1 × 10 ¹⁵ cm ⁻² . According to the invention described in claims 1 to 3, the first
The source and drain of the conductive thin film transistor are formed
The first dopant is introduced into the region of
In the region where the source / drain of the film transistor is formed
Are the first dopant and the first dopant is of the type
A different second dopant is introduced and the second dopant is
The dose of the punt is equal to the dose of the first dopant.
By being more than the equivalent and not more than three times, the second conductivity type thin
In the source / drain region of the film transistor, the second
Punts offset the effect of the first dopant, and
Since the component acts as an impurity, it can be easily
It becomes possible to constitute a transistor. In addition, the second domain
-The dose of the punt is equal to the dose of the first dopant.
By reducing the amount to three times, the first conductivity type thin film
The first doped source / drain region of the transistor
A dopant and a source of the first conductivity type thin film transistor;
The amount of surplus second dopant present in the drain region
There is no great difference between the two. Therefore, balanced
Complementary complementary thin film transistors can be provided.
Wear. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. FIG. 1 is an example of a sectional view showing the structure of a complementary thin film transistor according to the present invention. 101 is a P-channel type thin film transistor, and 102 is an N-channel type thin film transistor, constituting a complementary type thin film transistor. Reference numeral 103 denotes an insulating substrate such as a semiconductor integrated circuit substrate including glass, quartz, and a passivation film. 104, 10
Reference numeral 5 denotes a semiconductor thin film serving as a channel region, reference numerals 106 and 108 denote source regions, and reference numerals 107 and 109 denote drain regions. 1
Reference numerals 10 and 111 are gate insulating films, 112 and 113 are gate electrodes, 114 is a source electrode, and 116 and 118 are drain electrodes. A feature of the present invention resides in the structure of the source and drain regions, and takes one of the following structures. (1) The source and drain regions of a P-channel thin film transistor contain both acceptors and donors, and the source and drain regions of an N-channel thin film transistor contain only donors. (2) The source / drain region of the P-channel type thin film transistor contains an acceptor, and the source / drain region of the N-channel type thin film transistor contains both a donor and an acceptor. That is, in the conventional complementary type thin film transistor, the P-channel type source / drain region contains only the acceptor, and the N-channel type source / drain region contains only the donor. The source / drain region contains both donor and acceptor. Even with such a configuration, P-type or N-type control of the semiconductor can be performed without any problem. FIG. 2 is a view showing a method of manufacturing the complementary thin film transistor according to the present invention shown in FIG. First, FIG.
As shown in (a), after depositing a semiconductor thin film on an insulating substrate 201, a desired pattern is formed to form a channel region 202 of a P-channel thin film transistor and a channel region 203 of an N-channel thin film transistor.
Thereafter, the gate insulating film 2 is formed by using a thermal oxidation method or a vapor growth method.
04, 205, and further, gate electrodes 206, 207
To form Next, as shown in FIG. 2B, boron 208 is implanted at 1 × 10 ¹⁵ cm ⁻² by ion implantation. The implanted boron is activated by a later heat treatment to become an acceptor and form a P-type semiconductor. This allows P
Source / drain region 2 of channel type thin film transistor
09 and 210 are formed. At this time, the region 2 to be the source / drain region of the N-channel thin film transistor
Acceptors are similarly added to 11, 212. Next, as shown in FIG. 2C, the P-channel type thin film transistor is covered with, for example, a photoresist 213, and phosphorus or arsenic 14 is implanted at 3 × 10 ¹⁵ cm ⁻² . The implanted phosphorus or arsenic is activated by a subsequent heat treatment and becomes a donor. Therefore, 1 × 1
Acceptor corresponding to 0 ¹⁵ cm ^-2 and 3 × 10 ¹⁵ cm ^-2
Are included. If the conditions for ion implantation are optimized and the activation rate is sufficiently high, this region is almost equivalent to the case where only the donor corresponding to 2 × 10 ¹⁵ cm ⁻² is included. Therefore, the conductivity type of this region becomes N-type, and the source / drain region of the N-channel thin film transistor is formed. Finally, as shown in FIG. 2D, after removing the photoresist used as a mask at the time of ion implantation, an interlayer insulating film 215 is deposited. After opening the contact holes, source electrodes 216 and 218 and drain electrodes 217 and 219 are formed, and the complementary thin film transistor according to the present invention is completed. FIG. 3 is a graph showing the ON current of the thin film transistor configured as described above. The horizontal axis represents the ON current of the thin film transistor. The transistor having a channel length of 10 μm and a channel length of 10 μm has a gate voltage of 16 V,
It is defined as a drain current when a drain voltage of 5 V is applied. The horizontal axis is the dose of boron initially implanted over the entire surface. The concentration of phosphorus implanted only into the N channel region for the second time is constant at 3 × 10 ¹⁵ cm ⁻² . As is clear from the graph, the ON current of the P-channel type thin film transistor increases with the increase in the dose of boron, and a saturation tendency is observed at 1 × 10 ¹⁵ cm ⁻² or more. On the other hand, the N-channel type thin film transistor O
Although N current varies little in 1 × 10 ¹⁵ cm ^-2 or less, it decreases rapidly at 1 × 10 ¹⁵ cm ^-2 or more. All of these phenomena can be explained by considering the resistance of the source / drain regions. That is, the ON current increases because the resistance of the source / drain region of the P-channel type thin film transistor decreases with an increase in the dose of boron. However, at 1 × 10 ¹⁵ cm ⁻² or more, the resistance of the source / drain region exceeds Also, since the channel resistance becomes more dominant, even if the dose is further increased, O
The N current does not change. On the other hand, Sadako in the source / drain region of the N-channel thin film transistor is determined by both the dose of boron and the dose of phosphorus (3 × 10 ¹⁵ cm ⁻² ).
If the dose of boron is small, phosphorus becomes dominant and the resistance of the source / drain region becomes sufficiently low.
^If it becomes ¹⁵ cm ^-2 or more, the resistance of the source / drain region is increased by offsetting the phosphorus concentration, and the ON current is reduced. As can be seen from FIG. 3, 1 × 10 ¹⁵ c is formed in the source / drain region of the P-channel type thin film transistor.
When boron of m ⁻² is dosed and boron of 1 × 10 ¹⁵ cm ⁻² and phosphorus of 3 × 10 ¹⁵ cm ⁻² are dosed in the source / drain region of the N-channel type thin film transistor, both transistors are used. Can obtain a high ON current. FIG. 4 is a graph showing characteristics of the complementary thin film transistor according to the present invention. The vertical axis is the logarithmic value of the drain current, and the horizontal axis is the gate voltage. For convenience, the polarity of the gate voltage of the P-channel thin film transistor is set to be the same as that of the N-channel thin film transistor. The drain voltage is 5V. Good transistor characteristics can be obtained without being affected by the resistance of the source / drain regions. Although the case where the source / drain region of the N-channel type thin film transistor includes both the donor and the acceptor has been described above, the present invention is also applied to the case where the source / drain region of the P-channel type thin film transistor includes the donor and the acceptor. Holds exactly the same. According to the present invention, the following effects can be obtained. (A) The first and second dopants of different types are introduced into the source / drain regions of the second conductivity type thin film transistor. The second dopant cancels the action of the first dopant, and the excess Acts as an impurity in the source / drain region of the second conductivity type thin film transistor, so that a complementary type thin film transistor can be formed without increasing the number of steps. (B) Since the introduction of the impurity is performed by the ion implantation method, it is easy to control the channel length of the semiconductor thin film into which the dopant is introduced, particularly the channel length of the semiconductor thin film into which the first dopant and the second dopant are introduced. It is. (C) By setting the dose of the first dopant to approximately 1 × 10 ¹⁵ cm ⁻² by ion implantation, a high-performance complementary thin film transistor with high mobility can be formed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the structure of a complementary thin film transistor according to the present invention. FIG. 2 shows a method of manufacturing a complementary thin film transistor according to the present invention. FIG. 3 shows the relationship between the ON current and the acceptor concentration of the complementary thin film transistor according to the present invention. FIG. 4 shows characteristics of a complementary thin film transistor according to the present invention.

Claims (1)

(57) [Claims] A method of manufacturing a complementary thin film transistor, wherein a first conductivity type thin film transistor and a second conductivity type thin film transistor are formed on an insulating substrate, comprising: a step of depositing a semiconductor thin film on the insulating substrate; The first and second conductivity type thin film transistors are provided with a first
Introducing the dopant of the first conductivity type thin film transistor by ion implantation, and covering the region serving as the source / drain of the first conductivity type thin film transistor, the first conductivity type thin film transistor in the region serving as the source / drain of the second conductivity type thin film transistor. Introducing a second dopant of a type different from the dopant by an ion implantation method, wherein the dose of the second dopant is at least three times as large as the dose of the first dopant. And the dose of the first dopant is approximately 1 × 10
^A method for manufacturing a complementary thin film transistor, wherein the thickness is ¹⁵ cm ^-2 .