JPH04177873A - Complimentary mis semiconductor device - Google Patents

Abstract

PURPOSE:To enable hot carrier effect to be restricted and a threshold voltage (Vth) to be set easily by forming NMOS and PMOS channel regions with a nearly intrinsic semiconductor layer and then constituting a gate electrode with a material having a Fermi level which is separated from the Fermi level of the intrinsic semiconductor. CONSTITUTION:A nearly intrinsic Si layer exists as a channel region 10 on a supporting substrate 1-1 such as an Si wafer and an insulation layer 1-2 such as SiO2, a gate electrode 14 of NMOS is p<+> polySi, and a gate electrode 15 of PMOS is n<+> polySi. Then, a Fermi level of p<+> polySi is located at an upper edge of a band gap and that of n<+> polySi is located at a lower edge of the band gap, thus achieving a sufficient energy level difference with the Fermi level of the nearly intrinsic Si forming a channel region and achieving a desired Vth, thus preventing hot carrier effect from being generated.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a CMOS type integrated circuit device formed on an SOI substrate.
The purpose is to realize a structure in which both types of transistors have the desired V tb when the semiconductor layers that are the channel regions of the transistors are of the same conductivity type, and which prevents the occurrence of hot carrier effects due to miniaturization of devices. The semiconductor layer of the channel region is made substantially intrinsic, the Fermi level of the gate electrode material of NMO8 is near the upper end of the valence band of the semiconductor layer, and the Fermi level of the gate electrode material of PMO8 is of the semiconductor layer. The materials for both types of gate electrodes are selected and configured so that they are located near the lower end of the conduction band.

[Industrial application field]

The present invention relates to an integrated circuit structure in which both n-channel and p-channel MOS (MOS) transistors are formed on a so-called SOI substrate in which a semiconductor element formation layer is provided on an insulating substrate.

A complementary integrated circuit (hereinafter simply referred to as a C
MO8) has the feature of low power consumption, and many types of circuits are integrated into ICs as CMO8.

On the other hand, an SO2 substrate in which a semiconductor layer is provided on an insulating substrate is an I
It has the feature of completely insulating and isolating each element constituting the C, and has come into widespread practical use as SOI substrate manufacturing technology progresses.

Although the present invention can be widely applied to MIS transistors, in this specification, a MOS transistor, which is a typical structure thereof, is used.
) Explain about transistors. Further, a typical SOI substrate has a structure in which a semiconductor layer, which is an element formation layer, is provided on a silicon wafer with an insulating film such as an oxide film interposed therebetween.

When forming the CMO 8 on a normal bulk substrate, a region called a well or a tub is required for forming a transistor of either conductivity type. The normal structure is that this region is usually separated from the substrate by a p/n junction, but as the well is made smaller to increase the integration density of ICs, undesirable situations such as the effects of parasitic thyristors become apparent. Occur. If this is formed on an SOI substrate,
Since such problems can be avoided, the development of highly integrated CMO8 with fine patterns or using OI substrates is progressing.

However, if an SOI substrate is used, isolation between elements is perfect, but as the elements become smaller, new problems arise due to the small thickness of the element formation layer. In the case of a MOS transistor, the threshold voltage (V, ,
) is difficult to adjust. The high performance of semiconductor devices in recent years is largely due to improved performance of elements through miniaturization, so this is a problem that must be solved.

A typical SOI type CMO8 transistor has a structure as shown in FIG. In the figure, 11 is a supporting substrate such as a Si wafer, and 1-2 is an insulating layer such as SiO□. There are two n-type S/D regions 11 formed in the Si layer on this insulating layer, a p-type channel region 10-1 sandwiched between them, and a gate insulating film (not shown) on the channel region. The gate electrode 13 makes the NMOS and two p-type S
/D region 12 and n-type channel region 10 sandwiched therebetween
-2 and the gate electrode I4 present on the channel region constitute 2MO8.

When forming a MOS (MOS) transistor on a bulk substrate such as a Si wafer, an easy-to-handle material such as n-type poly-Si is used for the gate electrode, and Vtb is usually adjusted by doping the channel region with impurities. However, S
In a MOS transistor formed in a thin film such as a semiconductor layer of an OI substrate, V
There are situations in which the dependence of lb becomes weaker.

This means that a larger amount of channel doping is required to shift V th by the same amount as in a bulk-formed MOS transistor, but the higher the impurity concentration in the channel region, the more likely the hot carrier effect is to occur. , miniaturization of transistors is hindered.

The small thickness of the channel region also makes the NMOS
results in a shift of V th to the negative side, and 2MO
8 results in a shift to the positive side.

This shift amount increases as the channel region becomes thinner, which also makes it difficult to control vth.

In addition to these, another problem is that the thickness of the semiconductor layer of the SOI substrate is not sufficiently uniform. That is, when adjusting V th by doping the channel region with impurities, even if the ion implantation dose control is sufficiently accurate, the impurity concentration after activation will differ if the thickness of the channel layer differs. This results in variations in V th.

In this way, it is difficult to adjust Vth of Sol type MOS transistors compared to MOS transistors formed on a bulk substrate, and in particular, in CMOS, it is necessary to adjust Vthh of both n-channel and p-channel transistors. , - layer becomes difficult.

[Prior art and problems to be solved by the invention] The factors that determine the V tb of a MOS transistor are the channel impurity concentration, which affects how the depletion layer spreads, the Fermi level of the semiconductor in the channel region, and the gate electrode material. This may be due to the difference in Fermi level.

In CMOS formed in bulk, an easily available material (for example, n-type polysilicon) is used for the gate material, and Vlh is adjusted by the channel impurity concentration. Conventionally, this type of configuration has also been adopted in SO■.

However, when n-type polysilicon is used for the gate in thin-film SOI, the impurity concentration in the p-type channel region does not become very high (although V lb can be adjusted to the desired value,
There is a problem in that the desired V th cannot be obtained unless the impurity concentration in the n-type channel region is extremely high. This is because in thin film SOI, the dependence of Vlk on impurity concentration is small (because the Fermi level of the gate electrode material is n
If the MOS transistor is close to type silicon, it is easy to adjust V and h of one MOS transistor, but it becomes difficult to adjust V th of the other MOS transistor.

To address this problem, the Fermi level is located approximately in the middle of the bandgap, i.e. for n-type and p-type
0MO8 has been proposed in which the gate electrode is made of a material that has a Fermi level difference of the same degree as that of silicon type silicon. If they are made equal, then there will be no bias in the Fermi level difference between the channel region and the gate electrode for PMO8 and NMO8, and vth can be controlled with the same impurity concentration for both.

FIG. 7 illustrates the relationship between the Fermi level and the band gap. The Fermi level Efw of W is Sl
Since the valence band 21 and conduction band 22 of
There is an energy difference of 1=EfW−EfN (<0), and there is a difference in energy between the Fermi level Efp of n-type Si and Vp=E
There is an energy difference of fw Efp (> O). M.O.
Since the vlb of the S transistor is equal to VN or V, and the bandgap of Si is ~1.2 e V, these energy differences are equal to the value of vth (0, 3 to 0.4 V) can be said to be sufficiently large to be realized by increasing the concentration of n-type or p-type silicon impurities in the gate electrode.

This prior art MOS transistor consists of NMO8 and PM
The formation of O8 is proceeded under the equality constraint, VI
This is advantageous in that the difficulty of b control is not biased towards one transistor. However, control of V th here also depends on adjusting the impurity concentration in the channel region, and as the impurity concentration in this region increases, the problem that hot carrier effects are more likely to occur remains unsolved. Therefore, additional measures such as adopting an LDD structure are required to avoid the hot carrier effect.

An object of the present invention is to provide an integrated circuit structure in which vth can be easily controlled and the occurrence of hot carrier effects is avoided in an SOI type CMO8.Another object of the present invention is to simplify the manufacturing process. As a structure, PMO8, NM
The object of the present invention is to provide a structure in which both types of transistors can have a desired V th when the semiconductor layers that are the channel regions of O8 are of the same conductivity type.

[Means to solve the problem]

In order to achieve the above object, the CMO8 structure of the present invention has a structure in which the channel regions of NMO8 and PMO8 are both substantially intrinsic semiconductor layers, and the Fermi level of the gate electrode material of NMO8 is near the upper end of the valence band of the semiconductor layer. The materials for both gate electrodes are selected such that the Fermi level of the gate electrode material of PMO8 is near the lower end of the conduction band of the semiconductor layer.

The influence of impurity concentration as a factor that determines vlb of MOSFET becomes smaller as the Sol silicon film thickness becomes thinner in thin film SOI and as the channel impurity concentration becomes lower. Most of v and h are determined by the difference between the Fermi level and the Fermi level of the gate electrode material. So PM
O8,! By changing the gate electrode material of =NMO8, each vlb is adjusted by the difference between the Fermi level of the semiconductor in the channel region and the Fermi level of the gate electrode material.

In a typical embodiment, 0MO8 is essentially Si.
The gate electrode of NMO8 is p-type poly-Si, and the gate electrode of PMO8 is n-type poly-Si. In addition, Si which is the element forming layer
Expressing the impurity concentration in terms of resistivity, it is greater than 10'ΩCll1 in a region where a transistor whose source region and channel region are of the same conductivity type is formed, and a transistor whose source region and channel region are of different conductivity types is formed. It is larger than 103 Ωcm in the region where

[For production]

FIG. 5 is a diagram showing the band structure of the element of the present invention. Here, with reference to the figure, the reason why the desired V lh can be obtained in 0MO8 of the present invention will be explained.

Assuming the valence band 21 and conduction band 22 of Si as shown in the figure, the Fermi level Ef of intrinsic Si in the channel region is
There is a band gap. On the other hand, the Fermi level E f of n-type poly-Si constituting the gate electrode and the Fermi level E f of p-type poly-Si
f, , are located near the lower end of the conduction band and near the upper end of the valence band, respectively.

Since the NMO 8 is composed of a combination of a substantially intrinsic channel region and an n-type poly-Si gate, V th is determined by the difference V p p between the energy levels of Ef and Efl. In addition, PMO8 is composed of a combination of a substantially intrinsic channel region and an n-type poly-Si gate, and here, Ef,
. vth is determined by the energy level difference V, , fi between and Ef, .

As a result, in the structure of the present invention, the required V l h can be achieved in either NMO8 or PMO8, similar to the W gate configuration of the prior art described above, but unlike the prior art described above, In the CMO8 structure of the present invention, since the impurity concentration in the channel region is low, variations in Vlb caused by concentration dependence and occurrence of hot carrier effects are suppressed, and device characteristics can be realized with sufficient accuracy.

Next, in order for the present invention to obtain the above effects, the extent to which Si in the channel region may deviate from the intrinsic semiconductor is determined.
Let us consider the range of impurity concentration allowed in the i-layer.

First, on the side where the source/channel junction is a p/n junction, the difference in Fermi level between substantially intrinsic Si and n-type or p-type poly-Si is slightly increased or decreased from about 0.6 eV, respectively.

In order to reliably pinch off the enhancement mode MOS transistor with a gate voltage of 0V, vth
Since it is desirable that the energy level difference be greater than 0.4V, it is desirable that the energy level difference be at least 0.4V. That is, in FIG. 5, with respect to Efo, or Ef, which is a fixed value, the Fermi level Ef of the channel region may vary up and down by about 0.2 eV. Note that the above values of V and h = 0.4 V are based on room temperature operation, and when operating with cooling with liquid nitrogen etc., Vtb = 0.3 V or smaller may be used. (The range of impurity concentration allowed for Si in the channel region becomes wider.

The impurity concentration when the Fermi level shifts by 0.2 eV from the intrinsic value is \゛10''0c when converted to resistivity.
It is m.

Next, a configuration in which the source and channel have the same conductivity type will be considered. In this case as well, a channel is formed by the gate voltage and the transistor becomes conductive, but there is no pinch-off at the gate voltage of 0V, and some leakage current remains. Since the leakage current value is determined by the resistance of the channel region, the allowable range of impurity concentration in the channel region is determined from the allowable value of the leakage current.

When an IC is a logic circuit, the degree of integration is approximately 10,000 gates per chip, which is a smaller number of elements than a memory IC or the like. Therefore, the leakage current restrictions for ensuring the circuit operation are stricter than the leakage current of the entire IC. Assuming operation with a normal power supply voltage, a value of 10-''A or less per 1 μm of gate width is required.

On the other hand, in a device with a large number of elements such as a memory IC, a large amount of leakage current increases heat generation in the entire circuit, so it is necessary to prevent this from exceeding the heat dissipation capacity of the package. This restriction becomes more severe as the degree of integration of the IC increases. Expressed in terms of element leakage current, in a 256Kb SRAM, it may be about 1O-9A per 1μm of gate width, but I
When it comes to Mb, it is required to suppress it to about 10-''A/μm.

Furthermore, in ICs such as DRAMs, which have stricter leakage current constraints, this value is less than 10-''A/μm.

Considering the degree of integration of today's ICs, 100% of the above numbers
The value -9A/μm is considered to correspond to the allowable limit, but this means that the drain voltage is 5V and the gate length is 0.
．． When the thickness of the silicon layer is 5 μm and the thickness of the silicon layer is 0.1 μm, this means that the specific resistance of the channel region is desirably 10′Ωcm or more.

When the resistivity is such a large value, the relationship that is inversely proportional to the impurity concentration as in the case of low resistance does not hold.

The relationship between resistivity and impurity concentration in such cases has been variously reported and is known empirically to those skilled in the art.

According to the present invention, the intrinsic semiconductor layer is NMOS and PMO8.
When used as both channel regions, since the impurity concentration in the region is extremely low, the occurrence of the hot carrier effect can be sufficiently suppressed without a special structure such as an LDD. Furthermore, since MOS transistors of different conductivity types are formed in the same semiconductor layer, there is no need to form regions of opposite conductivity types called wells or tubs.

〔Example〕

FIG. 1 is a schematic cross-sectional view showing the structure of an embodiment corresponding to claim 4. In the figure, 11 is a support substrate such as a Si wafer, and 1-2 is an insulating layer such as 5iOz. A substantially intrinsic Si layer exists as a channel region IO on this insulating layer,
The NMOS is formed by the two n-type S/D regions 11 that are sandwiched between the two n-type S/D regions 11 and the gate electrode 14 that is present on the channel region via a gate insulating film (not shown), and the channel region that is also a substantially intrinsic Si layer. A PMO 8 is constituted by two p-type S/D regions 12 that are present on both sides of the IO and a gate electrode 15 that is present on the channel region.

Here, the gate electrode 14 of NMOS is made of p+ poly-Si, and the gate electrode 15 of PMOS is made of n+ poly-Si. Also, the impurity concentration of the Si layer in the channel region is ~10
It is 12cF3 or less. The usual manufacturing method for SOI substrates is to bond two Si wafers with an oxide film and polish one to a specified thickness. A low concentration, high resistance layer can be obtained.

Since the Fermi level of p" poly-Si is located at the upper end of the band gap, and the Fermi level of n+ poly-Si is located at the lower end of the band gap, the difference between the Fermi level of almost intrinsic Si forming the channel region and the There is also a sufficient energy level difference, and the desired Vlk is achieved.

FIG. 2 is a schematic cross-sectional view showing the structure of an embodiment corresponding to claim 5. In this example, the S/D region and channel region of NMOS and PMO8 have the same structure as in the above example, only the gate electrode material differs from the above example;
Nickel (N i ) is used for S, titanium (T
i) is used.

Even in this configuration, since the Fermi level of Ni is near the valence band of Si and the Fermi level of Ti is near the conduction band of Si, both types of MOS transistors can be used as in the embodiment shown in FIG. CMOS is realized by using semiconductor layers with the same specifications in the channel regions of the two.

3(a) to 3(g) are cross-sectional views schematically showing the manufacturing process of the CMOS shown in FIG. 1. This will be explained below with reference to the drawings.

Figure (a) shows the SOI substrate used in this process, where ■-1 is a supporting substrate (Si), 12 is an insulating layer (Si), and
02), 2 is an element forming layer (Si). normal SOI
Unlike the substrate, the element forming layer 2 here has an impurity concentration of 1
It is made of high resistance Si of less than 0.012 cm-3 and has a thickness of about 1000 mm.

As shown in FIG. 2B, the element formation layer is divided into island regions 2-1 and 2-2, which are transistor formation regions, and a thermal oxide film 3 of 100 to 200 layers is formed on the surface thereof. After that, a poly S1 layer 4 with a thickness of 2000 was applied on the entire surface of the board.
Adhesion is formed by method D. At this stage, this poly-Si layer is not doped with impurities.

FIG. 4(c) shows an ion implantation step for making a part of the poly-Si layer for an NMOS gate electrode.

After a 200A 5iCh film 5 is deposited on the surface of the poly-Si layer 4, areas other than the NMOS region are masked with a photoresist 6-1, and B+ ions are implanted.

The processing conditions are an implantation energy of 30 to 40 keV and a dose of 1015 to 1016 cm-2. Through this treatment, a part of the poly-Si layer becomes a p+ type poly-Si layer 4-p.

The process shown in the next figure (d) is also an ion implantation process, and poly-Si
The regions other than those where the layer is to be of B+ type are masked with a photoresist 6-2, and P+ ions are implanted. The processing conditions are that the implantation energy is 40 to 50 keV and the dose is IO! 5-10
I10l8'. Through this treatment, a part of the poly-Si layer becomes an n''' type poly-Si layer 4-n.

After this, the formation of the S/D region begins, and as shown in FIG.
A photoresist layer 6-3 is provided to cover the region, and after selectively etching and removing the poly-Si layer using this as a mask, ions of As'' are implanted to form the S/D region 7-3 of NMO8.
Form 1.

A similar process is performed to form the S/D region of PMO8, and as shown in the same figure, the S/D region 7-2 of PMO8 is created by ion implantation of BF2''. If removed, N
MO8 and PMO8 are completed, and these transistors are combined to form 0MO8.

When the impurity concentration of the channel region is low as in the present invention, the hot carrier effect is unlikely to occur, but if an LDD structure is required, it can be formed by the steps shown in FIGS. 4(a) to (c). I can do it. The method for manufacturing the LDD structure according to the present invention will be described below with reference to FIG.

The element formation layer of the SOI substrate used in the present invention has extremely high resistance, but has a conductivity type of pn. The hot carrier effect occurs in MOs where the channel/drain has a pn junction.
Since this is a phenomenon that occurs in S transistors, the LDD structure to avoid this need only be either 8MO8 or PMO8. Here, the element forming layer is p
− type will be explained as an example.

After proceeding with the steps in FIGS. 3(a) to (d) as described above, in the ion implantation process in the step in FIG. 3(e), 1013 cF2 of P+ ions were implanted instead of As+ ions, and
Convert the S/D region of 8 to n-type. After proceeding with the process in Figure 3) as described above and removing the photoresist,
As shown in Figure (a), SiO2 is
Layer 8 is deposited to a thickness of 1000-2000 nm.

When this is etched using an anisotropic processing method such as RIE, gate electrodes 4-pG, 4 are etched as shown in FIG. 4(b).
A side wall 8-1.8-2 of SiO2 remains on the side surface of -nG.

If one transistor region is masked with photoresist 6-5 and As+ ions are implanted into the other transistor region to form an S/D region, NM
O8 has an LDD structure and PMO8 has p”/p−
/ 0MO8 with p+ tank structure is obtained.

In the above process shown in FIG. 3 or FIG. 4, gate electrodes with two types of conductivity are created from the same poly-Si layer by selective ion implantation, but the 0MO of the present invention
Another method for forming 8 is to first deposit poly-Si with one conductivity type to form one gate electrode, and then deposit poly-Si with the other conductivity type to form the other gate electrode. You can also take the following method.

〔Effect of the invention〕

In the SOI type CMO8 of the present invention, NMO8 and P, MOS
Since the channel region of each is formed of a substantially intrinsic semiconductor layer with the same specifications (same conductivity type, same specific resistance), the step of forming a well of the other conductivity type is omitted, and the substrate impurity concentration is low. E. It has the advantage that sothocarrier effects are unlikely to occur.

Further, as described in the section of the operation, by forming the gate electrode with a material having a Fermi level that is different from the Fermi level of the intrinsic semiconductor, it is possible to easily set the Vth of the MOS transistor.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional diagram showing the structure of the first embodiment of the present invention, FIG. 2 is a schematic cross-sectional diagram showing the structure of the second embodiment of the present invention, and FIG. 3 is manufacturing of the element of the present invention. FIG. 4 is a cross-sectional schematic diagram showing another manufacturing process of the device of the present invention. FIG. 5 is a schematic cross-sectional diagram showing the band structure of the device of the present invention. FIG. 6 is a known structure of 0MO8. FIG. 7 is a schematic cross-sectional view showing the band structure of a known CMO8, in which 11 is a supporting substrate (Si), 12 is an insulating layer (SiO2), and 2 is an element forming layer ( 2-1.2-2 is an island region, 3 is a thermal oxide film, 3-1 is a gate insulating film, 4 is poly-Si (non-doped), 4-n is an n-type poly-Si layer, 4-p is an n-type poly-Si layer, 4-nG is an n-type gate electrode (poly-Si), and 4-pG is a p-type
type gate electrode (poly-Si), 5 is a 5ift film, 6-1.6-2.6-3.6-4. is photoresist,
7-1.7-2. 8 is a 5iOz layer, 10 is a channel region, 10-1 is an n-type channel region, 10-2 is an n-type channel region, 11 is an n-type S/D region, 12 is a p-type S/D Regions 14 and 15 are gate electrodes, 21 is a valence band of Si, and 22 is a conduction band of Si. NMOS PMOS Fig. 1 is a cross-sectional schematic diagram showing the structure of the first embodiment of the present invention. Fig. 2 is a schematic cross-sectional diagram showing the structure of the second embodiment of the present invention. ＼h＼ NMO8PMC)S Schematic cross-sectional diagram showing the structure of a normal SOI type CMO8 Fig. 6 7'/

Claims (5)

[Claims] (1) In a substantially intrinsic semiconductor layer provided on an insulating substrate,
By providing an n-type source/drain region and a gate electrode made of a first conductive material via a gate insulating film,
A p-channel insulated gate field effect transistor is formed by providing a p-type source/drain region and a gate electrode of a second conductive material via a gate insulating film. (a) the Fermi level of the first conductive material forming the gate electrode of the n-channel transistor is close to the upper end of the valence band of the semiconductor material forming the channel region; (b) the Fermi level of the second conductive material constituting the gate electrode of the p-channel transistor is close to the lower end of the conduction band of the semiconductor material constituting the channel region; (c) the both types of transistor i) In a configuration in which the channel region and the source region are of different conductivity types, the resistivity of the semiconductor layer forming the channel region of the transistor is determined by An impurity concentration such that the difference from the Fermi level of the semiconductor layer located approximately in the center does not become less than the energy level difference necessary to realize V_t_h at which the transistor becomes reliably non-conductive when the gate voltage is 0V. ii) In a configuration in which the channel region and the source region are of the same conductivity type, the leakage current value at the operating temperature of the transistor prevents malfunction of a circuit configured using the transistor. A value that does not exceed the allowable value for leakage current, or a value determined from the allowable total current value of the integrated circuit configured using the transistor, whichever is smaller, is necessary to avoid exceeding the leakage current value. A complementary MIS semiconductor device characterized by: (2) The semiconductor layer provided on the insulating substrate is an n-type or p-type high-resistance silicon layer, and the specific resistance of the silicon layer is such that a transistor is formed whose source region and channel region are of the same conductivity type. 10 in the area where
2. The complementary MIS semiconductor device according to claim 1, wherein the resistance is greater than ^5 Ωcm, and is greater than 10^3 Ωcm in a region where a transistor whose source region and channel region are of different conductivity types is formed. (3) The first conductive material constituting the gate electrode of the n-channel transistor is below the Fermi level of intrinsic silicon by 0.3 eV or more, and the second conductive material constituting the gate electrode of the p-channel transistor is below the Fermi level of intrinsic silicon. 3. The complementary MIS semiconductor device according to claim 1, wherein the magnetic material is located above the Fermi level of intrinsic silicon at a distance of 0.3 eV or more. (4) The first conductive material constituting the gate electrode of the n-channel transistor is p^+ type polycrystalline silicon, and the second conductive material constituting the gate electrode of the p-channel transistor is n^+ type polycrystalline silicon. 4. The complementary MIS semiconductor device according to claim 3, wherein the semiconductor device is made of + type polycrystalline silicon. (5) The first conductive material constituting the gate electrode of the n-channel transistor is nickel (Ni), and the second conductive material constituting the gate electrode of the p-channel transistor is titanium (Ti). 4. A complementary MIS semiconductor device according to claim 3.