JPH04259259A - Mis transistor for thin film soi structure - Google Patents

Abstract

PURPOSE:To obtain a MIS transistor of a thin film SOI structure in which a potential under a channel can be secured and adapted for a high temperature IC. CONSTITUTION:In a MOS transistor formed on a thin SOI film 1 on an insulator 10, a drain region 4 is diffused to the insulator 10. On the other hand, a source region 5 is so formed that diffusion is stopped on the way of the film 1. Thus, a potential of a channel region 6 can be biased from a bias region 7 through a bias passage 8 under the region 5. A connecting area of the region 4 is reduced, and a reverse leakage current can be suppressed at the time of a high temperature.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to MI of thin film SOI structure.
The present invention relates to an S transistor, and particularly to one in which the potential under the channel (hereinafter referred to as substrate potential) is fixed from the surface electrode side.

0002

[Prior Art] Silicon used as a semiconductor material (
At high temperatures, Si) undergoes physical property changes such as an increase in reverse leakage current in the PN junction, a decrease in carrier mobility, and a fluctuation in the Fermi level. In particular, an increase in reverse leakage current causes an increase in offset voltage or a latch-up phenomenon when an analog circuit is created, for example, and is a factor that has the greatest effect on the characteristics of an IC. Therefore, the operating temperature limit of bulk Si is about 150°C at most, and the operating temperature range of commonly used ICs is usually -55 to 125°C.

On the other hand, as seen in wheel speed sensors and combustion pressure sensors used in automobiles, for example, the operating temperature is 150°C.
In fact, some temperatures actually reach 200°C. Therefore, in recent years there has been a desire to develop ICs that can be used even at high temperatures.
The SOI structure thin film transistor shown in 3(a) is attracting attention as a structure capable of reducing reverse leakage current. This is because the reverse leakage current (current generated) generated in the depletion region is reduced by suppressing the extension of the depletion layer by the insulator 10 due to the SOI structure, and also because the source/drain regions 4 and 5 are By diffusing into the insulator 10, the junction area can be significantly reduced compared to the transistor formed in the bulk Si 20 shown in FIG. This is because the reverse leakage current (diffusion current) can be significantly reduced.

Furthermore, when constructing a CMOS, bulk Si inevitably creates a parasitic transistor that causes latch-up when the temperature rises, but in the SOI structure, N-channel elements and P-channel elements are each placed on separate Si islands. Since it can be configured as follows, it is possible to make it latch-up free.

[0005]

[Problems to be Solved by the Invention] Incidentally, in order to operate an IC stably, it is necessary to fix the substrate potential. When the substrate potential is not fixed (floating), the switching characteristics become unstable, and such a transistor is expected to cause IC malfunction and performance deterioration.

As shown in FIG. 13(b), bulk Si20
In the case where the substrate potential is formed as shown in FIG.
In the thin film transistor with the SOI structure shown in FIG. 1, the drain region 4 and the source region 5 are diffused into the insulator 10 under the Si film 1 in order to reduce the PN junction area as described above, so the channel 6 part is the drain region. 4 and the source region 5, making it appear as if they are isolated, making it difficult to set the substrate potential.

[0007] In other words, in order to operate the IC accurately and stably by taking advantage of the features of the SOI structure, such as being latch-up free and suppressing reverse leakage current, which are advantageous at high temperatures, it is important to ensure the substrate potential. be. As a method of fixing the substrate potential, it is possible to fix the substrate potential from the lateral direction of the channel 6 as shown in FIG. 12, but in this case, as shown in the plan view of FIG. A wraparound region (bias path 8) is required, which increases the overall transistor size, making it unsuitable for high integration. In addition, the area that can be biased (Figure 1
The shaded area in 2(a) is only the lateral end (channel end) of the device that can be determined by the gate length, and there is also the problem that the device becomes smaller as the device becomes finer.

The present invention has been made in view of the above-mentioned circumstances, and provides an MIS with a thin film SOI structure that is particularly suitable as a high-temperature IC, and is capable of responding to miniaturization of elements and easily fixing the substrate potential. The purpose is to provide transistors.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present inventors have studied the mechanism of reverse leakage current of MIS transistors, and have found that between the drain and the substrate and between the source and the substrate where a PN junction is formed. In this study, we focused on the fact that since the source and substrate are generally at the same potential, the problem with leakage current is between the drain and the substrate.
In the OI structure, the drain diffuses until it reaches the insulator in order to reduce the junction area to suppress reverse leakage current, while the source stops diffusion in the middle of the Si film, and the potential under the channel passes under the source. It was found that the

That is, the MIS transistor according to the present invention includes an insulating substrate, a semiconductor film of a first conductivity type formed on the insulating substrate, and a semiconductor film formed in a predetermined region of the semiconductor film. a drain region of a second conductivity type having a diffusion depth reaching from the insulating substrate to the insulating substrate; a source region of a second conductivity type formed such that a PN junction with the film is terminated and having a predetermined diffusion depth at which diffusion ends in the semiconductor film; A gate electrode is formed on the semiconductor film on the source region side with respect to the channel region, and a gate electrode is formed on the semiconductor film on the source region side with respect to the channel region. , which is of a first conductivity type and has a higher impurity concentration than the semiconductor film, to which a bias voltage for biasing the potential of the channel region is applied through a region of the first conductivity type left under the source region. It is characterized by comprising a bias region.

[0011]

[Operation] Therefore, in the semiconductor film, the drain region is diffused to the insulating substrate, so the junction area is
It is provided only by the PN junction surface with the semiconductor film in the lateral direction of the drain region, which is determined by the thickness of the semiconductor film, and can be small.

On the other hand, the source region is not diffused to the insulating substrate, and the diffusion is completed within the semiconductor film due to the predetermined diffusion depth. Therefore, a region of the first conductivity type of the semiconductor film remains under the source region, and the potential of the channel region is applied to the bias voltage applied to the bias region via this region of the first conductivity type. Fixed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on embodiments shown in the drawings. FIG. 1 shows a linear N-channel MOS transistor to which a first embodiment of the present invention is applied. Figure (a) shows a plan view, and figure (b) shows its AA sectional view. In the figure, 1 is an island-shaped SOI film formed on an insulator 10, 2 is a gate oxide film, 3 is a gate electrode, 4 is a drain region, and 5 is a gate oxide film.
1 is a source region, 6 is a channel region, 7 is a bias region for fixing the potential under the channel, and 8 is a bias path thereof.

As shown in FIG. 1(b), in the SOI film 1, the drain region 4 is diffused to the insulator 10, so the junction area is given only by the lateral direction of the drain region 4, and it is difficult to make it small. Can be done. Therefore, Figure 1
The generation of reverse leakage current at high temperatures can be suppressed to a much greater extent than that formed in bulk Si as shown in FIG. 3(b).

On the other hand, the source region 5 is not diffused to the insulator 10, and the diffusion is stopped in the middle of the SOI film 1. Therefore, the substrate potential under the channel 6 can be fixed to the bias voltage Vs applied to the bias region 7 via the bias path 8 passing under the source region 5 . In this manner, the structure shown in FIG. 1 can prevent reverse leakage current, which becomes a problem at high temperatures, and can also fix the substrate potential, thereby stabilizing the switching characteristics of the transistor. It is also expected that the kink phenomenon and charge pumping phenomenon will be eliminated.

Furthermore, the substrate potential can be fixed using the bias region 7.
Since this is carried out from the same surface side of the SOI film 1 as the source region 5 etc., it is possible to fix the potential of each N-channel element and P-channel element, for example, when configuring a CMOS or the like. In other words, the N-channel device connects the substrate potential to ground,
In P-channel devices, the substrate potential is generally fixed to the power supply voltage, and it is advantageous to be able to fix the individual potentials.

Next, an example of the manufacturing method of the first embodiment shown in FIG. 1 will be explained with reference to FIGS.
This will be explained using cross-sectional views of S in the order of manufacturing steps. First, a sapphire substrate, which is an oxide single crystal substrate, is prepared as the insulator 10, and the SOI film 1 is formed on its surface by vapor phase growth or the like. In addition, spinel, magnesia, etc. may be used as the insulator 10. In addition, S is relatively easy to obtain.
Of course, an OS (Silicon-On-Sapphire) substrate may be used. The SOI film thickness is approximately 1 μm.

After the pad oxide film is formed, as shown in FIG. 2, a lateral insulation isolation region 11 is formed by, for example, the LOCOS method, and the SOI film 1 is isolated in the form of an island in each of the P-channel transistor and N-channel transistor formation regions. Insulate and separate. After removing the nitride film formed at that time, phosphorus (P) and boron (B) are selectively introduced into each region and drive-in is performed to form an N- well and a P- well, respectively.
Well. At this time, each well concentration is set as described later.

After removing the pad oxide film described above, a gate oxide film 2 is formed on the surface of each well, N+ polycrystalline silicon is deposited by the LPCVD method, and patterned in a linear shape as shown in FIG. 1(a). By doing so, the gate electrode 3 is formed. At this time, in order to facilitate the positioning of the source region and bias region that will be formed in the later process,
The masking polycrystalline silicon film 3a may be left as is. Then, the surface of this gate electrode 3 is oxidized (
(see Figure 2).

Next, the drain region 4 of the P-channel transistor and the bias region 7 of the N-channel transistor
The photoresist film 1 has a pattern with openings in the area where it is planned to be formed.
00, and ions of boron (B), which is a P-type impurity, are implanted (see FIG. 3). In addition, this photoresist forming process involves selectively exposing and exposing the resist to the entire surface.
This is done through a photo process for development. Further, the drain region 4 is formed in self-alignment with the gate electrode 3, and the bias region 7 is formed in self-alignment with the masking polycrystalline silicon film 3a.

Similarly, arsenic (As), which is an N-type impurity, is ion-implanted into the regions where the bias region 7 of the P-channel transistor and the drain region 4 of the N-channel transistor are to be formed, using the photoresist film 110 as a mask (FIG. 4). reference). Note that the process shown in FIG. 3 and the process shown in FIG. 4 may be performed in reverse order. Then, as shown in FIG. 5, it is diffused into both wells by heat treatment to also activate the drain region 4 and bias region 7 of each of the P-channel transistor and N-channel transistor.

Next, P-type impurity is introduced again. In this case, unlike the step shown in FIG. 3 described above, ions are also implanted into the source region 5 of the P-channel transistor. That is, ions such as boron (B) are implanted into the source region 5 and drain region 4 of the P-channel transistor and the bias region 7 of the N-channel transistor using the photoresist film 120. At this time, the source region 5 of the P-channel transistor is introduced in a self-aligned manner by the gate electrode 3 and the masking polycrystalline silicon film 3a (see FIG. 6).

Similarly, an N-type impurity (eg, As) is introduced using the photoresist film 130 as a mask. In this case as well, unlike the process shown in FIG. 4 described above, ions are implanted into the source region 5 of the N-channel transistor in addition to the drain region 4 of the N-channel transistor and the bias region 7 of the P-channel transistor (see FIG. 7). . Note that the steps shown in FIGS. 6 and 7 may be performed in the reverse order.

Then, heat treatment is performed on both the P-channel transistor and the N-channel transistor to also activate the source region 5, drain region 4, and bias region 7, and as shown in FIG. The bias region 7 is diffused until it reaches the insulator (sapphire substrate) 10. Note that while the impurity introduction into the drain region 4 is carried out in two steps, the impurity introduction step into the source region 5 is performed once, so that the diffusion in the SOI film 1 is completed.

Then, the interlayer insulating film 12 is formed, the contact holes are opened, and the electrode (source, drain) wiring 13 is patterned, thereby manufacturing the CMOS shown in FIG. Note that in the above-described manufacturing method, the lateral isolation regions 11 are formed by the LOCOS method, but lateral isolation may be achieved using trenches or the like. In that case,
Drain region 4 and bias region 7 can also be seen from the trench hole wall surface.
Impurities can be introduced into.

Next, the well concentration set in the process shown in FIG. 2 will be explained using an N-channel transistor as an example. Here, in this embodiment, as shown in FIG. 1, the substrate potential is fixed via the bias path 8 under the source region 5. Therefore, if the SOI film 1 under the source region 5 is completely depleted, biasing from the bias region 7 becomes extremely difficult. Therefore, in order to obtain a bias effect, it is necessary to design the device so that the bias path 8 exists under the source region 5 in relation to the junction depth of the source region 5 and the width of the depletion layer under the source region 5. .

Generally, the PN junction in the source region can be approximated by a step junction, and the depletion layer width Xd in the source region is given by the following equation.

[0028]

[Math 1]

##EQU1## where Cs is the source concentration and CB is the substrate concentration. From formula 1, for example, the gate oxide film is 85
The relationship between the substrate concentration CB and the depletion layer width Xd when it is 0 Å is calculated as shown in FIG. Therefore, S.O.
The thickness of the I film 1 is 1 μm, and the diffusion depth of the source region 5 is approximately 0.
．． In the case of 5 μm, in order to secure the bias path 8 under the source region 5, the depletion layer width Xd needs to be smaller than 0.5 μm. That is, as shown in FIG. 9, in this embodiment, the P-
The concentration of the well is about 1016 cm-3.

The characteristics of the N-channel transistor manufactured as described above are shown in FIGS. 10(a) and 10(b). Same figure (
a) is a Vg-logID characteristic showing the relationship between gate voltage Vg and drain current ID. As shown in the figure,
Since the characteristics also change when the substrate potential (bias potential) Vs is changed, it can be confirmed that the substrate bias is maintained. On the other hand, Figure (b) shows the relationship between drain voltage VD and drain current ID. As shown in the figure, good transistor characteristics were obtained.

Furthermore, since the substrate potential is biased through the bottom of the source region 5, the biasable region is also a region given by the gate width shown by diagonal lines in FIG. 11(a). When forming such a transistor with a large gate width, the region that can be biased is larger than that of the transistor of the same size shown in FIG. 12, which is advantageous. Further, compared to the structure shown in FIG. 12, since a wraparound region for biasing is not required, the transistor size can be reduced. In addition, in the case shown in FIG. 12, when the transistor is turned on at the channel end, the drain current flows around the outside of the channel, and it is expected that the current value will not be as designed. In this embodiment, where there is no wraparound area, such a problem can be prevented.

Next, a second embodiment of the present invention will be explained. FIG. 14 shows an N-channel MO to which the second embodiment of the present invention is applied.
It is an S transistor, and Figure (a) shows a plan view, and Figure (b) shows its AA cross-sectional view. Note that the same components as in the first embodiment shown in FIG. 1 are given the same reference numerals. As can be seen from FIG. 14, this embodiment has a structure in which the drain region 4 is surrounded by the gate and source regions 5, and the bias region 7 is set at the outermost periphery of the SOI film 1.

Also with this structure, the substrate potential can be fixed by the bias voltage Vs applied to the bias region 7 via the bias path 8 under the source region 5. Further, since the drain region 4 is diffused to the insulator 10, the junction area is small and the occurrence of reverse leakage current at high temperatures can be suppressed. In addition, in a linear MOS device, there is a plane with a different crystal orientation from the SOI film surface at the channel end face, so it is thought that the influence of the channel end face will affect the transistor characteristics.
As shown in 4(a), in this embodiment, the drain region 4 is surrounded by the channel region, so in principle, no end face is formed in the channel portion, and the above-mentioned effects, such as leakage at the channel end face, occur. Never. Also, Figure 1
Since there is no detour path for the drain current in the case shown in 2, it is possible to obtain the designed current value.

As shown in FIG. 1, the drain region is surrounded.
The round MOS transistor shown in No. 4 is advantageous in that there is no leakage at the end face of the channel portion and there is no current flowing around outside the channel. The planar pattern of a round MOSFET in which the drain region is surrounded is shown in Fig. 15(a).
), (b), all of the regions 4, 6, 5, and 7 may be circular or rectangular.

Next, FIG. 16 shows a third embodiment of the present invention. In this embodiment, in addition to the bias effect described above, the electric field concentration at the gate edge portion of the drain region 4 is alleviated by the low impurity concentration drain region 4a, and the spread of the lateral electric field between the source and drain is suppressed. Therefore, devices can be miniaturized. Next, a fourth embodiment of the present invention will be described.

FIG. 17 shows a P-channel MOS transistor to which the fourth embodiment of the present invention is applied. As mentioned above, SOI
If the film is completely depleted, it becomes very difficult to fix the potential from the bias region 7. In this embodiment, as shown in FIG. 17, a heavily doped layer 9 communicating from below the source region 5 to below the channel region is provided to suppress complete depletion below the source region 5 and channel region 6. ing. The other configurations are the same as those shown in FIG. 1, and the same reference numerals as in FIG. 1 are given.

According to the fourth embodiment, since the expansion of the depletion layer under the source region 5 is stopped at the heavily doped layer 9, the bias path 8 is secured by the heavily doped layer 9, and the substrate potential is fixed. It becomes easier. Therefore, in P-channel transistors, which have lower carrier mobility than N-channel transistors and require larger device size or lower substrate concentration when configuring CMOS, the width of the depletion layer under the source This is especially advantageous since it is possible to easily secure a bias path without any problems.

Furthermore, since this heavily doped layer 9 is provided to the bottom of the channel, the resistance under the channel can be reduced, and a large number of carriers (N channel In this case, the holes) are not accumulated in the SOI film 1, but can be quickly absorbed to the power supply Vs side through the heavily doped layer 9, and the kink phenomenon can be suppressed.

Next, an example of a method for manufacturing the P-channel MOS transistor shown in FIG. 17 will be described with reference to FIGS. 18 to 21. First, an N-type Si substrate 1a on which an IC will be formed is prepared, and in order to form a heavily doped layer 9 on one main surface thereof, N-type impurities (for example, As) are introduced at a high concentration (
(See Figure 18).

[0040] Then, a Si substrate 10b having a SiO2 film 10a formed on its main surface is prepared as an insulating substrate 10, and
The i-substrate 1a and the insulating substrate 10 are bonded together using a known Si-SiO2 direct bonding technique, with the main surfaces on which the highly doped layer is formed and the main surfaces on which the SiO2 film 10a is formed facing each other. (See Figure 19). According to this method, the crystallinity of the SOI film on the insulating substrate 10 is not impaired.

After that, the Si substrate 1 on the side into which impurities have been introduced
A is lap-polished to a desired thickness (see FIG. 20), and the P-channel MOS transistor having the SOI structure shown in FIG. 21 is manufactured through the same steps as those shown in FIGS. 2 to 8 described above. Although the fourth embodiment has been described using a P-channel transistor as an example, it is of course applicable to an N-channel transistor as well. Also, Figure 14
The round MOS transistor shown in Figure 16 or the L shown in Figure 16
The fourth embodiment may be applied to a device having a DD structure.

Furthermore, in the above various embodiments, MO
Although an S-structure transistor has been described, the present invention is not limited to this.
The present invention may be applied to a NOS structure.

[0043]

Effects of the Invention As detailed above, in the present invention, the drain region is diffused into the insulating substrate in the semiconductor film, so the junction area can be reduced, and reverse leakage that occurs at high temperatures can be reduced. Current can be suppressed. In addition, since diffusion of the source region ends in the middle of the semiconductor film, the potential of the channel region is changed by the bias voltage applied to the bias region.
It can be easily fixed via the conductivity type region.

Furthermore, since the bias path is set under the source region in this way, there is no need to set a wraparound bias path for fixing the potential from the lateral direction of the channel, and the overall transistor size can be minimized. can be made as small as possible. That is, according to the present invention, it is possible to provide a MIS transistor having a thin film SOI structure that is suitable for use as a high-temperature IC, which can respond to miniaturization of elements, and can easily fix the substrate potential. is played.

[Brief explanation of the drawing]

FIG. 1 shows a linear N-channel MOS transistor to which a first embodiment of the present invention is applied; FIG.
Figure (b) is its AA sectional view.

FIG. 2 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 3 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 4 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 5 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 6 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 7 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 8 is a cross-sectional view showing a CMOS manufacturing process to which the first embodiment of the present invention is applied.

FIG. 9 is a characteristic diagram showing the relationship between the substrate concentration CB and the depletion layer width Xd under the source region.

FIG. 10 is a characteristic diagram showing transistor characteristics of an N-channel MOS transistor to which the present invention is applied;
a) is Vg-logId characteristic, figure (b) is VD-ID
It is a characteristic.

FIG. 11 is a P-channel MOS transistor with a large gate width to which the first embodiment of the present invention is applied; FIG. 11(a) is a plan view, and FIG. 11(b) is an AA sectional view thereof.

FIG. 12 is a diagram illustrating a method of fixing the substrate potential of an SOI structure used to explain the problems of the present invention; FIG. 12 is a plan view;
Figure (b) is its AA sectional view.

[Figure 13] A diagram showing a conventional structure, where figure (a) is an SOI
Cross-sectional view of an N-channel MOS transistor with the structure, figure (b
) is a cross-sectional view of an N-channel MOS transistor using a bulk.

FIG. 14 is a round N-channel MOS transistor to which the second embodiment of the present invention is applied; FIG.
b) is its AA sectional view.

15A and 15B are both plan views showing a modification of the second embodiment of the present invention shown in FIG. 14. FIG.

FIG. 16 is a cross-sectional view of an N-channel MOS transistor to which a third embodiment of the present invention is applied.

FIG. 17 is a cross-sectional view of a P-channel MOS transistor to which a fourth embodiment of the present invention is applied.

18 is a cross-sectional view showing a method of manufacturing the transistor shown in FIG. 17. FIG.

19 is a cross-sectional view showing a method of manufacturing the transistor shown in FIG. 17. FIG.

20 is a cross-sectional view showing a method of manufacturing the transistor shown in FIG. 17. FIG.

21 is a cross-sectional view showing a method of manufacturing the transistor shown in FIG. 17. FIG.

[Explanation of symbols]

1 SOI film 2 Gate insulating film 3 Gate electrode 4 Drain region 5 Source area 6 Channel 7 Bias area 8 Bias passage 9 Highly doped layer 10 Insulator

Claims (5)

[Claims] 1. An insulating substrate, a first conductivity type semiconductor film formed on the insulating substrate, and a diffusion layer formed in a predetermined region of the semiconductor film and reaching from the surface of the semiconductor film to the insulating substrate. a drain region of a second conductivity type having a depth; and a surface of the semiconductor film, leaving a gap along a termination of a PN junction between the drain region and the semiconductor film;
a source region of a second conductivity type formed such that a PN junction with the semiconductor film terminates and having a predetermined diffusion depth at which diffusion ends in the semiconductor film; the drain region and the source region; and a gate electrode formed at least on the channel region via a gate insulating film, and a gate electrode formed on the semiconductor film on the source region side with respect to the channel region. a first conductivity type semiconductor film having a higher impurity concentration than the semiconductor film, to which a bias voltage for biasing the potential of the channel region is applied via a first conductivity type region left under the source region. A MIS transistor characterized by comprising a bias region of high concentration. 2. The predetermined diffusion depth of the source region is such that a region of the first conductivity type left under the source region has a width larger than a depletion layer formed under the source region. M according to claim 1, characterized in that it is set.
IS transistor. 3. A semiconductor film of the first conductivity type for suppressing the spread of a depletion layer formed under the source region, in a region of the first conductivity type left under the source region. 2. The MIS transistor according to claim 1, further comprising a heavily doped layer having an impurity concentration higher than that of the MIS transistor. 4. The MIS transistor according to claim 1, wherein the drain region is formed such that a terminal end of a PN junction on the surface thereof is surrounded by the channel region. 5. A low concentration drain region of a second conductivity type having a relatively low impurity concentration in order to alleviate electric field concentration at the end of the gate electrode of the channel region, at the end of the PN junction of the drain region. The MIS according to any one of claims 1 to 4, characterized in that:
transistor.