JPH0590492A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a capacitive element free of breakdown strength deterioration efficiently by removing a step from a silicon nitride film. CONSTITUTION:The lower electrode 23 and the dielectric film 25 of a capacitive element are made by patterning the two layers of a polysilicon layer and a silicon nitride film at the same time. At the same time with it, a gate electrode 15 consisting of the said two layers is made. An interlayer insulating film 28 is made on the dielectric film 25, and an upper electrode 26 is made. The step of a silicon nitride film is removed by arranging the dielectric film 25 along the top of the lower electrode 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a capacitive element and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a capacitive element incorporated in an integrated circuit has a PN junction junction capacitance, a gate capacitance between a gate electrode and a diffusion layer, or an electrode wiring and an electrode wiring. It is known to use an insulating film capacitance between them. The one using an insulating film capacitor has an advantage that a material having a high dielectric constant can be used and there is no voltage dependency.

FIG. 8 shows a structure disclosed in, for example, Japanese Patent Laid-Open No. 2-226755. In the figure, (1)
Is a silicon substrate, (2) is a silicon oxide film, (3) is a polysilicon layer, (4) is an interlayer insulating film, (5) is a dielectric thin film such as a silicon nitride film (SiN), and (6) is an Al electrode. Is.

[0004]

However, in the capacitive element having the above-mentioned structure, since the dielectric thin film (5) is formed so as to cover the opening of the interlayer insulating film (4), the step around the opening is stepped. In (A in the figure), the dielectric thin film (5) is liable to cause step breakage and the like, and there is a defect that breakdown voltage is likely to occur between the upper electrode and the lower electrode.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and is polysilicon which will be a gate electrode (15) of a MOS element (16) and a lower electrode (23) of a capacitor element (24). A silicon nitride film (SiN) which becomes a dielectric thin film (25) of the capacitive element (24) is formed on the entire surface of the layer, and an opening (34) is provided in an interlayer insulating film (28) covering the lower electrode (23), The upper electrode (26) of the capacitive element (24) is formed so as to cover the opening (34).

[0006]

According to the present invention, since the dielectric thin film (25) extends substantially horizontally along the surface of the lower electrode (23), the step disappears and there is no fear of step breakage. Further, by simultaneously forming the gate electrode (15) of the MOS element (16), a silicon nitride film can be deposited on the surface of the gate electrode (15).

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which the present invention is applied to a Bi-CMOS integrated circuit will be described in detail below with reference to the drawings. In FIG. 1, (11) is a P-type silicon semiconductor substrate, (12)
Is an N ⁺ type buried layer, (13) is a P ⁺ type isolation region for junction isolation of the epitaxial layer formed on the surface of the substrate (11), (14) is a LOCOS oxide film for element isolation, (1
5) is the gate electrode of the P-channel type MOS device (16), (17) is the P-type source / drain region of the MOS device (16), and (18) is the P-type of the NPN transistor (19).
Type base region, (20) P ⁺ type base contact region, (21) N ⁺ type emitter region of NPN transistor (19), (22) N ⁺ type collector contact region, (23) capacitive element (24) ) Lower electrode, (25)
Is a dielectric thin film, (26) is an upper electrode of the capacitive element (24), (27) is an extraction electrode of the lower electrode (23), (2)
8) is an interlayer insulating film, (29) is an Al electrode, (30) is S
iN insulating film, (31) polyimide insulating film, (32)
Is the second layer Al wiring. In the finished product, a polyimide insulating film for a jacket is further formed on the second layer Al wiring (32).

Gate electrode (15) of MOS device (16)
And the lower electrode (23) of the capacitive element (24) has R _S = 10
It is composed of a polysilicon layer doped with phosphorus so as to have a resistance of 20 Ω · cm, and is arranged on the gate oxide film (33) in the element region surrounded by the LOCOS oxide film (14). It is arranged on a thick LOCOS oxide film (14) having a thickness of about 6 to 1.0 μm to form the lower electrode (23). The polysilicon layer also becomes a part of the electrode wiring extending on the LOCOS oxide film (14).

Dielectric thin film (25) on the lower electrode (23)
Is a heat-generated silicon nitride film (Si ₃ N ₄ ) having a film thickness of 100 to 300 Å formed by the LPCV method. And the surface of a part of the electrode wiring made of the polysilicon layer. The interlayer insulating film (28) is made of a BPSG film heavily doped with phosphorus (P) and boron (B). The BPSG film is deposited and then reflowed to planarize the surface. The SiN insulating film (30) thereon is a nitride film formed by the plasma CVD method.
It was provided in order to compensate for the drawback of the SG film having poor moisture resistance.

The interlayer insulating film (28) covering the dielectric thin film (25) of the capacitive element (24) has an opening (34) of a size corresponding to the capacitance value and a contact hole for the lower electrode (23). (35) is provided. The opening (34) exposes the surface of the dielectric thin film (25), and the contact hole (35).
Penetrates the dielectric thin film (25) to expose the surface of the lower electrode (23).

The upper electrode (26) of the capacitive element (24) is
It is provided on the dielectric thin film (25) extending substantially horizontally along the surface of the lower electrode (23) so as to cover the opening (34). The dielectric thin film (25) is the interlayer insulating film (2
8), the upper electrode (26) adheres to the interlayer insulating film (28) around the side wall of the opening (34) and the opening (34). The extraction electrode (27) of the lower electrode (23) makes ohmic contact with the lower electrode (23) through the contact hole (35). When electrically connecting to the gate electrode (15) of the MOS element (16) or a part of the electrode wiring made of the polysilicon layer, the same procedure as for the extraction electrode (27) of the lower electrode (23) is performed.

According to the above-described structure of the present invention, the dielectric thin film (25) of the capacitor element (24) extends substantially horizontally along the surface of the lower electrode (23), and the interlayer insulating film (25) is formed thereon. Two
Since 8) is provided, there is no step in the dielectric thin film (25).
Therefore, there is no deterioration in breakdown voltage between the upper electrode (26) and the lower electrode (23) due to breakage of the dielectric thin film (25). Moreover, since there is no step breakage, the dielectric thin film (25) can be made thin. If the thickness can be reduced, the capacitance value per unit area can be increased.

Further, since the surface of the gate electrode (15) of the MOS element (16) and a part of the electrode wiring made of the polysilicon layer are also covered with the silicon nitride film (36), the gate electrode is formed by the passivation effect of the nitride film. (15)
Etc. reliability is improved. Especially as a flattening technology, BPSG
In the structure of the present invention in which the SiN insulating film (30) is formed by the plasma CVD method in order to supplement the moisture resistance, a hydrogen ion (H ⁺ ) unavoidably present in the SiN insulating film (30) is used. Of the change (slow trapping phenomenon) of the threshold value (V _T ) of the MOS element (16) due to the movement of
This can be prevented by blocking the entry of the hydrogen ions by the heat-generated silicon nitride film (36) provided on the gate electrode (15). Furthermore, since the multilayer wiring material (Poly-Si and Al) is used for the counter electrode that sandwiches the dielectric thin film (25), the series resistance is reduced and the capacitive element (24).
In addition to improving the characteristics of the capacitor, the capacitive element (24) is changed to LOCOS.
Since it is arranged on the oxide film (14), there is no leakage current to the substrate (11), and the parasitic effect peculiar to the integrated circuit can be completely prevented.

The manufacturing method of the present invention will be described in detail below with reference to the drawings. First, on the surface of a P-type silicon semiconductor substrate (11), an N ⁺ -type buried layer (12) and a P ⁺ -type isolation region (1
3) Form the lower part and other necessary areas, and
1) Form an N-type epitaxial layer on top. Then, the P-type impurities are diffused from the surface of the epitaxial layer to form the upper portion of the isolation region (13) for forming the island region,
Further, the surface of the epitaxial layer is selectively oxidized to a film thickness of 0.8.
˜1.0 μ LOCOS oxide film (14) is formed, and FIG.
Get the structure of.

A film thickness of 500 to be the gate oxide film (18)
A 800 Å silicon oxide film is formed by thermal oxidation, and a film is formed on the entire surface.
Deposit 0.4-0.8μ thick undoped polysilicon
It Dope the deposited polysilicon with impurities (phosphorus)
To provide conductivity, and then a film is formed on the entire surface by the LPCVD method.
A silicon nitride film (S
i₃N_Four) Is deposited. Polysilicon layer and silicon nitride film
The two-layer film of
A MOS element is formed on the gate oxide film surrounded by the S oxide film (14).
The gate electrode (15) of the child (16) as a LOCOS oxide film
The lower electrode (23) of the capacitive element (24) is placed on (14).
Formed (FIG. 3). The method is, for example, CF _Four+ O₂By gas
It is a continuous anisotropic etch.

The formation of the selective mask using photoresist and the ion implantation of impurities are repeated a plurality of times to form all the diffusion regions of the bipolar element such as the NPN transistor (19) and the diffusion region of the MOS element (16) (FIG. 4). ). The NPN transistor (19) comprises a P type base region (18), an N ⁺ type emitter region (21), a P ⁺ type base contact region (20), and an N ⁺ type collector contact region (22). The PchMOS transistor (16) is composed of a gate electrode (15) formed previously and P ⁺ type source / drain regions (17) formed on both sides of the gate electrode (15). The source / drain region (17) of the PchMOS transistor (16) is NP
Base contact region (2) of N-transistor (19)
0) and the source of the NchMOS transistor (not shown)
The drain region is also used as the emitter region (21) of the NPN transistor (19).

A film thickness of 1.0 is formed on the entire surface by the LPCVD method or the like.
A BPSG (boron phosphorus silicate glass) film of ˜2.0 μ is deposited to form an interlayer insulating film (28) and reflowed to flatten the surface. Then, a first resist pattern is formed, and the interlayer insulating film (28) is etched with a hydrofluoric acid buffer solution to form an opening (34) exposing the dielectric thin film (25) (FIG. 5).

After removing the first resist pattern, a second resist pattern is formed, and an interlayer insulating film (2
8) and the dielectric thin film 25 are continuously etched to form a contact hole 35 (FIG. 6). At this time,
Not only the contact hole (35) on the polysilicon layer but also the contact hole on the diffusion region of each element is formed at the same time. The etching is performed by anisotropic dry etching in a CF ₄ + O ₂ gas atmosphere, for example.

Al or Al-Si is deposited on the entire surface and photo-etched to form electrode wiring (2) of each device.
9), the upper electrode (26) of the capacitive element (24), and the lower electrode extraction electrode (27) are formed (FIG. 7). According to such a manufacturing method, the gate electrode (1) of the MOS element (16) is
5) Simultaneously with formation, the lower electrode (2) of the capacitive element (24)
Since 3) and the dielectric thin film (25) are formed, the process can be simplified.

[0020]

As described above, according to the present invention,
Since there is no step in the dielectric thin film (25) of the capacitive element (24), there is an advantage that it is possible to provide the capacitive element (24) without deterioration in breakdown voltage due to step breakage or the like. Further, a silicon nitride film (36) is similarly formed on the gate electrode (15) of the MOS device (16).
Since it is covered with, there is an advantage that a highly reliable element free from fluctuations in threshold value can be incorporated.

Furthermore, since the gate electrode (15) of the MOS element (16) and the lower electrode (23) of the capacitor element (24) can be formed simultaneously, there is an advantage that the process can be simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a first cross-sectional view for explaining the manufacturing method of FIG.

FIG. 3 is a second cross-sectional view for explaining the manufacturing method in FIG.

FIG. 4 is a third cross-sectional view for explaining the manufacturing method in FIG.

5 is a fourth cross-sectional view for explaining the manufacturing method in FIG.

FIG. 6 is a fifth cross-sectional view for explaining the manufacturing method in FIG.

FIG. 7 is a sixth cross-sectional view for explaining the manufacturing method in FIG.

FIG. 8 is a cross-sectional view for explaining a conventional example.

Claims (5)

[Claims] 1. A semiconductor integrated circuit in which at least a capacitive element is integrated, the lower electrode of the capacitive element provided on an insulating film, and the dielectric thin film of the capacitive element covering the entire surface of the lower electrode, An interlayer insulating film covering the dielectric thin film, an opening provided in the interlayer insulating film to expose the surface of the dielectric thin film, and the lower electrode penetrating the dielectric thin film provided in the interlayer insulating film. A semiconductor integrated circuit, comprising: a contact hole exposing a surface of the capacitor; an upper electrode of a capacitor provided so as to cover the opening; and an extraction electrode contacting the lower electrode through the contact hole. 2. A semiconductor integrated circuit in which at least a MIS type element and a capacitive element are integrated, wherein a LOCOS oxide film for element isolation and an M arranged in an element region surrounded by the LOCOS oxide film.
A gate electrode of the OS element, a lower electrode of the capacitive element made of the same material as the gate electrode material disposed on the LOCOS oxide film, a dielectric thin film covering substantially the entire surface of the gate electrode and the lower electrode, An interlayer insulating film covering the dielectric thin film; an opening provided in the interlayer insulating film to expose a surface of the dielectric thin film on the lower electrode; and the dielectric thin film provided in the interlayer insulating film. A lower electrode contact hole penetrating to expose the surface of the lower electrode, a contact hole exposing the surface of a diffusion region forming each element, an upper electrode of a capacitive element formed to cover the opening, An electrode contacting the lower electrode through a contact hole for the lower electrode, and an electrode contacting the diffusion region through the contact hole. And a semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the dielectric thin film is a silicon nitride film. 4. A step of forming a LOCOS oxide film for element isolation, a step of depositing an electrode material to be a gate electrode of a MOS element and a lower electrode of a capacitor on the entire surface, and a dielectric thin film of the capacitor on the entire surface. A step of depositing an insulating material comprising: forming a gate electrode of the MOS element, a lower electrode of the capacitive element on the LOCOS oxide film, and a dielectric thin film by simultaneously patterning the insulating material on the electrode material. A step of depositing an interlayer insulating film covering the entire surface, and forming an opening in the interlayer insulating film to expose the surface of the dielectric thin film on the lower electrode by one resist process, and by another resist process. A lower electrode contact hole that penetrates the dielectric thin film and exposes the surface of the lower electrode, and a capacitor that covers the opening by depositing and patterning an electrode material. A step of forming an upper electrode of an element and an electrode wiring of each element. 5. The method of manufacturing a semiconductor integrated circuit according to claim 3, wherein the one resist process is a wet method and the other resist process is a dry method.