JP2531680B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a transistor having a structure in which an electrode in an operation region is taken out by a conductive film connected to the operation region of the transistor, and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device suitable for flattening an element and a manufacturing method thereof.

[Conventional technology]

In order to achieve high performance of bipolar semiconductor integrated circuits, a structure in which the base electrode is taken out from the side of the base region using a polycrystalline silicon film (SICOS: Sidewall Base Contact Structure (Sidewall Base Cont
Act structure) transistors have been proposed (see Japanese Patent Laid-Open No. 56-1556).

In the conventional device described above, in order to form a polycrystalline silicon film for extracting a base electrode connected to a base region of a transistor, first, an insulating film is formed on a semiconductor substrate on which a convex single crystal semiconductor layer for an active region is formed. After depositing the polycrystalline silicon film on the entire surface through the film, the surface of the polycrystalline silicon film is flattened by using a photoresist. Then, the polycrystalline silicon film is patterned by using known photolithography and dry etching techniques to remove unnecessary portions. After that, the region where the polycrystalline silicon film for electrode extraction is not formed is selectively oxidized to be an oxide film for element isolation, and the active regions such as the base regions of the transistors are electrically isolated.

[Problems to be solved by the invention]

However, in the conventional transistor in which the polycrystalline silicon film for taking out the base electrode is formed by the steps as described above,
If the element spacing of the transistor or the like is narrowed to improve the degree of integration, the step due to the patterning of the polycrystalline silicon film for taking out the base electrode becomes sharp, and as a result, Al or the like in a later step is There is a problem that it has a bad influence such as difficulty in forming wiring.

An object of the present invention is to solve the above-mentioned problems of the conventional element, and to integrate a semiconductor integrated circuit having a transistor whose concept is to take out an electrode using a conductive film such as a polycrystalline silicon film with good flatness and high density. And to provide a manufacturing method thereof.

[Means for solving problems]

That is, in order to achieve the above-mentioned object, the semiconductor device of the present invention is formed around a convex single crystal semiconductor layer on a semiconductor substrate and has an operating region of a transistor formed in the convex single crystal semiconductor layer. In a semiconductor device having at least a transistor having a structure in which an electrode in the operating region is taken out by using a conductive film connected to at least one region, the conductive film is adjacent to the conductive film on substantially the same plane as the conductive film. The present invention is characterized by further including a planarizing dummy layer formed in the above manner.

In the semiconductor device of the present invention, a step of forming a convex single crystal semiconductor layer on a semiconductor substrate, and a conductive film connected to the upper convex single crystal semiconductor layer via an insulating film on the semiconductor substrate are formed. And a step of patterning the conductive film, and a step of forming a planarizing dummy layer adjacent to the conductive film patterned via an insulating film.

Further, it is desirable that the distance between the conductive film and the planarizing dummy layer is as small as possible within a limit that can be insulated by an insulating film, but in order to planarize the element surface, the thickness of the conductive film ( That is, the depth of the groove when the conductive film is entirely deposited)
3 times or less is desirable.

Further, the flattening dummy layer is formed of, for example, the same material as the conductive film.

[Action]

Conventionally, since a conductive film for taking out a base electrode is patterned by photolithography and dry etching techniques and then separated by selectively oxidizing a region where the conductive film is removed, when devices are integrated, a sharp step is formed. occured. On the other hand, in the present invention, when patterning the conductive film, a planarizing dummy layer formed on the same plane as the conductive film and adjacent to the conductive film with an insulating film interposed therebetween is used. Since it is embedded, the element surface can be made flat. In the present invention, in planarizing the element surface, the distance between the conductive film and the planarizing dummy layer (that is, the groove width) is the thickness of the conductive film (that is, the depth of the groove). It is desirable to make it about 3 times or less.

Note that the narrow groove formed between the conductive films after patterning can be easily filled with an insulating film or a conductive film by using a method such as a CVD (chemical vapor deposition) method.

The required film thickness of the conductive film or the planarizing dummy layer and the flatness at the time of completion depend on the groove width. The narrower the groove width, the smaller the required film thickness and the better the flatness. Therefore, if it falls, it is desirable to unify the groove width to 1 μm when using a processing technique in which the minimum processing dimension determined by the resolution limit of photolithography is 1 μm, but when it is difficult due to the layout. It is possible to widen it to about 2 μm. Further, when the distance is 3 μm or more, the flattening dummy layer can be inserted in between to keep the groove width at 1 μm.

In addition, the effective groove width is Therefore, considering this point, set the groove width narrow, or
It is desirable to avoid crossing groove patterns (avoid crossing and T-crossing is acceptable).

〔Example〕

Embodiment 1 FIG. 1 is a sectional view of a completed bipolar transistor of the first embodiment of the present invention.

In the figure, 1 is a P-type silicon substrate, 2 is an N-type buried layer for collector, 7 is a thick SiO ₂ film for element isolation, and 14 is P
Type base diffusion layer, 16 is an N type emitter diffusion layer, 9 is a polycrystalline silicon film for taking out a base electrode, 9'is a polycrystalline silicon film deposited and patterned simultaneously with the polycrystalline silicon film 9 for planarization, 11 is a polycrystalline silicon film for flattening (dummy layer for flattening) formed in a process different from that of the polycrystalline silicon film 9, and 7'is polycrystalline silicon film 9, 9'or
An insulating SiO ₂ film interposed between 11, an N-type diffusion layer for taking out a collector electrode, 12 an SiO ₂ film, 15 a polycrystalline silicon film for forming an emitter diffusion layer, 17 a passivation film, 18 base electrode 19 emitter electrode, 20 is a collector electrode, d ₁ to d ₃ is the distance to what polycrystalline silicon film 9, 9 '.

Conventionally, since the polycrystalline silicon film 9 for taking out the base electrode was patterned by photolithography and dry etching techniques and then separated by selective oxidation, a steep step was generated when the elements were integrated. In the semiconductor integrated circuit of the embodiment, the silicon groove is filled with the polycrystalline silicon film 9 ′ that is deposited and patterned simultaneously with the polycrystalline silicon film 9 and the polycrystalline silicon film 11 formed by another process. As a result, since the element surface is flattened, there is an effect that it is possible to prevent disconnection of wiring such as Al in a subsequent step. Incidentally, the polycrystalline silicon film 9, 9 'and 11, respectively SiO ₂ film 7' are completely insulated and separated by.

2 to 6 are process cross-sectional views showing a method of manufacturing the transistor shown in FIG.

First, as shown in FIG. 2, a P-type silicon substrate 1 is doped with impurities to form an N ⁺ -type diffusion layer 2 for collector,
A silicon epitaxial growth layer 3 is formed thereon by an epitaxial growth method, and further, a SiO ₂ film 4 is formed by thermal oxidation, a Si ₃ N ₄ film 5 and a SiO ₂ film are formed by a CVD (chemical vapor deposition) method.
After the films 6 were sequentially formed, the three-layer films 4 to 6 were processed by using ordinary photolithography and dry etching techniques.

Next, using a known SICOS transistor manufacturing process, as shown in FIG. 3, a device isolation SiO ₂ film 7, a graft base contact hole 8, and a base electrode extraction polycrystalline silicon film 9 are entirely deposited. And it was formed through planarization using a photoresist.

Next, after the SiO ₂ film 6 shown in FIG. 3 is removed by etching, as shown in FIG. 4, pattern intervals (groove widths) d _{1 to} d ₃
The polycrystalline silicon films 9 and 9'are processed by photolithography and dry etching techniques using a mask designed to have a predetermined dimension (for example, about 2 .mu.m) or less. Then, thermal oxidation is performed to form the polycrystalline silicon film 9
A SiO ₂ film 10 having a film thickness of 30 to ₂₀₀ nm was formed on the surfaces 9 and 9 '.

Next, the polycrystalline silicon film 11 is formed by the CVD method to form the groove widths (d _{1 to} d
After being deposited to a thickness equal to or larger than ₃ ), etching was performed by this thickness to leave a polycrystalline silicon film 11 in the groove as shown in FIG.

Next, thermal oxidation is performed using the Si ₃ N ₄ film 5 as a mask, and as shown in FIG. 6, polycrystalline silicon films 9, 9'and 11 are formed.
A thick SiO ₂ film 12 having a film thickness of 200 to 500 nm was formed on the upper surface. As a result, the entire surface of the polycrystalline silicon film was covered with the SiO ₂ film, the steep step disappeared, and the surface became flat. In this embodiment, the polycrystalline silicon films 6'and 11 are present in addition to the polycrystalline silicon film 9 for extracting the base electrode, but since they are completely separated by the SiO ₂ film, they adversely affect the electrical characteristics. There is no such thing.

Then, the Si ₃ N ₄ film 5 shown in FIG. 6 is removed, and as shown in FIG. 1, the N-type diffusion layers 1 and P for extracting the collector electrode are formed.
The type base diffusion layer 14 was formed by impurity doping, and the N type emitter diffusion layer 16 was formed by doping impurities through the polycrystalline silicon film 15. Then, after depositing a passivation film 17 using a Si ₃ N ₄ film or a PSG film, a contact hole is opened, and a base electrode 18, an emitter electrode 19 and a collector electrode 20 made of Al or the like are formed to form FIG. The transistor shown in is completed.

Second Embodiment FIG. 7 is a sectional view of a transistor according to a second embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same things (the same applies to all the following drawings).

In the figure, 21 is a Si ₃ N ₄ film, 22 is a polycrystalline silicon film, 2
3 is a SiO ₂ film. In the first embodiment, the groove formed by patterning the polycrystalline silicon film for extracting the Beew electrode is filled only with polycrystalline silicon. However, as in the present embodiment, the polycrystalline silicon film is patterned to form a surface. After being thinly oxidized, a Si ₃ N ₄ film 21 is deposited and then a polycrystalline silicon film 22 is embedded. Therefore, after this, the SiO ₂ film
Since the stress generated when forming 23 is relaxed by the Si ₃ N ₄ film 21, there is an advantage that crystal defects are less likely to occur in the single crystal silicon layer, and as a result, it is possible to manufacture an integrated circuit with high yield. You can Further, it is possible to omit the SiO ₂ film 23 in order to further reduce the strain.

Third Embodiment FIG. 8 is a sectional view of a transistor according to a third embodiment of the present invention.

This embodiment is similar to the second embodiment shown in FIG.
After laying the Si ₃ N ₄ film 21, instead of the polycrystalline silicon film 22 and the SiO ₂ film 23 in the _second embodiment, SiO ₂ , PSG, BSG,
Since it is embedded with the insulating film 24 such as oxynitride or Si-containing SiO _2, a high-performance integrated circuit with low parasitic capacitance can be realized.

Fourth Embodiment FIG. 9 is a sectional view showing a transistor of the fourth embodiment of the present invention.

In the first to third embodiments described above, in order to flatten the surface of the element, the polycrystalline silicon film 9'and the polycrystalline silicon film 11 formed in a separate process are used. The flatness which is the purpose of can be expressed also by making the polycrystalline silicon films 9 and 11 or 9'and 11 common. This embodiment shows this example.

The groove for filling and flattening the polycrystalline silicon film or the like is not formed only by the conventional conductive film pattern for extracting the base electrode, but is formed between the conductive films (distance d _{1 in} FIG. 9) or the conductive film. And element area pattern (spacing in Fig. 9
d ₂ ′, d ₃ ′). However, in this case, the distance d ₂ in consideration of the deviation of mask alignment between the conductive pattern and the device region pattern ', d _3' to, or the same as d _1, d ₁
Need to be designed smaller than.

Fifth Embodiment FIG. 10 is a sectional view of a transistor of the fifth embodiment of the present invention.

In this embodiment, instead of the polycrystalline silicon film 22 and the SiO ₂ film 23 in the fourth embodiment shown in FIG. 9, SiO ₂ , PSG, BSG, etc. are used as in the third embodiment shown in FIG. This is an example in which the insulating film 24 made of oxynitride, Si-containing SiO ₂ or the like is embedded and planarized.

8 and 10, even if the Si ₃ N ₄ film 21 is not provided, the characteristics and flatness are not hindered, and the object of the present invention is achieved.

Although the first to fifth embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments.
For example, in the above embodiment, a polycrystalline silicon film was used as the conductive film for extracting the base electrode, and the SiO ₂ film was formed thereon, but instead of the polycrystalline silicon, a metal silicide film (tungsten, molybdenum, platinum, palladium, The present invention can be implemented by using a silicide film such as titanium) and forming a silicide oxide film or a CVD insulating film (oxide film or nitride film) thereon.

Further, the dummy layer for filling and flattening the groove formed after the patterning of the conductive film for extracting the base electrode is not limited to the conductive film such as polycrystalline silicon, but as described in the above embodiment, silicon oxide, PSG, BSG , Oxynitride,
It is possible to use an insulating film such as Si-containing silicon oxide.

Further, in the present embodiment, although the electrode in the operating region of the transistor is taken out by using the conductive film, only the case where the base region of the vertical bipolar transistor is taken out has been described. However, the present invention makes the emitter and collector electrodes conductive. A horizontal bipolar transistor with a structure that takes out with a film,
A structure in which the source and drain electrodes are taken out using a conductive film
It is also possible to implement it in a MOS transistor.

〔The invention's effect〕

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the step difference on the element surface such as the underlying step difference of the wiring made of Al or the like is significantly reduced from the conventional about 1.0 μm to about 0.3 μm, The number of wire disconnections and short circuits has been reduced, and the yield and reliability of integrated circuits have been improved by about twice.

[Brief description of drawings]

FIG. 1 is a sectional view of a bipolar transistor showing a first embodiment of the present invention, FIGS. 2 to 6 are sectional views showing a manufacturing process of the transistor of FIG. 1, and FIGS. FIG. 4 is a cross-sectional view showing a bipolar transistor of each of second to fifth embodiments of the present invention. 1 ... Si substrate 2 ... Collector buried layer 3 ... Epitaxial growth layer 4, 6 ... SiO ₂ film 7, 7 ', 10, 12 ... SiO ₂ film for element isolation 5 ... Si ₃ N ₄ film 9 ...... Polycrystalline silicon film for electrode extraction 9 ', 11, 22 …… Polycrystalline silicon film for planarization 14 …… Base region 15 …… Polycrystalline silicon film for forming emitter diffusion layer 16 …… Emitter regions 18, 19, 20 …… Al electrode 21 …… Si ₃ N ₄ film 23 …… SiO ₂ film 24 …… Insulating film for planarization

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Akihisa Uchida 1450, Kamisuihonmachi, Kodaira City Computer Development Department, Hitachi, Ltd. Device Development Center (72) Inventor, Toru Koizumi 1450, Josuimotomachi, Kodaira City Hitachi, Ltd. (72) Inventor Hiromitsu Enonami 1450, Kamisuihonmachi, Kodaira-shi, Hitachi Ltd. Computer Development Department, Computer Division

Claims (6)

(57) [Claims] 1. A conductive film which is formed around a convex single crystal semiconductor layer on a semiconductor substrate and which is connected to at least one operation region of a transistor formed in the convex single crystal semiconductor layer. In a semiconductor device having at least a transistor having a structure for taking out an electrode in the operation region, a planarizing dummy layer formed on the same plane as the conductive film and adjacent to the conductive film via an insulating film is provided. A semiconductor device further comprising: 2. The semiconductor device according to claim 1, wherein the distance between the conductive film and the planarization dummy layer is about three times or less the thickness of the conductive film. . 3. The flattening dummy layer is made of the same material as that of the conductive film.
3. The semiconductor device according to item 2 or 2. 4. A step of forming a convex single crystal semiconductor layer on a semiconductor substrate, and a step of forming a conductive film connected to the convex single crystal semiconductor layer on the semiconductor substrate via an insulating film. A method of manufacturing a semiconductor device, comprising: a step of patterning the conductive film; and a step of forming a planarizing dummy layer adjacent to the patterned conductive film via an insulating film. 5. The semiconductor according to claim 4, wherein the distance between the conductive film and the planarizing dummy layer is about three times or less the thickness of the conductive film. Device manufacturing method. 6. The flattening dummy layer is made of the same material as that of the conductive film.
Item 5. A method for manufacturing a semiconductor device according to Item 5.