JPH01133350A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify process control, by using a P-type or an N-type diffusion region which is formed before performing an emitter diffusion process as a lower electrode region having MIS type capacity and depositing a nitriding film by making use of an oxide film pattern for forming a lower electrode region as it is. CONSTITUTION:An oxide film pattern 27 for forming a capacity part at the surface of an epitaxial layer 23 is formed and a lower electrode region 28 is formed by selecting P or N-type impurities after making use of the oxide film pattern 27. Then, a nitriding film is deposited at the whole surface and after forming a dielectric thin film 29 which coats opening parts of the oxide film pattern 27, an emitter region 31 of an NPN transistor is formed by diffusing selectively the N-type impurities. Then, most part of the surface of the dielectric thin film 29 is exposed and further, after forming a contact hole 35 which passes through the dielectric thin film 29 by utilizing a dry-etching process, an upper electrode 36 is arranged at the exposed dielectric thin film 29 and an electrode 35 which comes into ohmic contact with the lower electrode region 28 is arranged at the contact hole 35. Thus, process control is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit incorporating an MIS type capacitive element, which facilitates the hyar control of an NPN transistor.

(b) Conventional technology A bipolar IC is a vertical NPN formed by doubly diffusing a base and an emitter on the surface of a semiconductor layer that serves as a flip-flop.
It is mainly composed of transistors. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation process for each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since various conditions for the base and emitter diffusion steps are set with the most important consideration given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, the basic N
A new process may be added not for the purpose of forming a PN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, P is used to form an anode region that controls the Zener voltage of the Zener diode together with the cathode region formed by the emitter diffusion.
4 Diffusion process, R diffusion process to form a resistance region with a different resistivity from the base region, implant resistance formation process, MOS
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the mold, and the collector low resistance region formation process to further reduce the collector series resistance of NPN) transistors, all of which are used for bipolar ICs. This is a process (optional process) that is determined whether or not to be added based on consideration of the process, purpose, and cost.

FIG. 3 shows an MIS type capacitor formed using the above optional process. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N+ type buried layer, (4) is a P'' type isolation region, (5) is an island,
(6> is the N+ type lower electrode region formed by emitter diffusion, (
7) is a silicon nitride film (si$
N4), (8) are upper electrodes made of aluminum material;
(9) is an oxide film, and (10> is an electrode. As an MIS type capacitor using a nitride film, for example, JP-A-60-2
It is described in Publication No. 44056.

(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since it uses the emitter region of a PN transistor,
After depositing the N-type impurity for forming the emitter region, a nitride film must be formed, and then the N-type impurity must be driven in. Then, the 8
Because heat treatment at around 00"C diffuses the emitter region,
NPN transistors have a drawback that their h□ (current amplification factor) varies widely and is difficult to control.

Additionally, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not the optional process required to form the nitride film is added, which requires process management for each model, which has the disadvantage that management cannot be standardized. .

(d) Means for Solving the Problems The present invention has been made in view of the serious drawbacks, and includes a method for manufacturing a semiconductor integrated circuit incorporating an MIS type capacitor. A step of forming an oxide film pattern (27), a step of forming a lower electrode region (28) by selecting a P or N type impurity using this oxide film pattern (27), and a step of forming a nitride film (28) on the entire surface. NP by depositing Si3N4) and forming a dielectric thin film (29) covering the opening portion of the oxide film pattern (27), and selectively diffusing N-type impurities.
A step of forming the emitter region (31) of the N transistor, and a contact hole (35) exposing most of the surface of the dielectric thin film (29) and penetrating the dielectric thin film (29) using a dry etching method. forming an upper electrode (36) on the exposed surface of the dielectric thin film (29);
(e) Feature characterized in that the contact hole (35) is provided with a step of disposing an electrode (35) in ohmic contact with the lower electrode region (28).According to the present invention, an emitter is used as the lower electrode. Since the region formed before forming the emitter region (31) is used without using diffusion, and the emitter is diffused after devoting the nitride film, the hF of the NPN transistor after forming the emitter region (31) is
It is possible to eliminate the heat treatment process that affects 1. In addition, an oxide film pattern (
Since the oxide film pattern (27) for disposing the dielectric thin film (27) and the dielectric thin film (29) can be used in common, the photoresist process can be omitted.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (
The surface of the N+ type buried layer (22) is selectively doped with N type impurities such as antimony (Sb) or arsenic (As).
), and an N-type epitaxial layer (23) with a thickness of 5 to 10 μm is laminated on the entire surface of the substrate (21).

Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the epitaxial layer (23),
Epitaxial layers (
A P+ type isolation region (24) is formed passing through (23). an epitaxial layer (23) surrounded by an isolation region (24);
) is an island (25) for forming each circuit element.
becomes. Then, by selectively implanting or diffusing boron (B) into the surface of one island (25) using a positive or negative photoresist, a base region (26) that will become the base of the NPN transistor is formed. .

Next, as shown in FIG.
An oxide film pattern (27) having openings is formed in the region where a) is to be provided. Next, this oxide film pattern (2
7) to form a lower electrode region (28) that will become the lower electrode of the MIS type capacitor by introducing P or N type impurities from the surface of the epitaxial layer (23).The impurities include phosphorus (P), arsenic, etc. (As), boron (B), etc. are used, and selective diffusion or ion implantation is used as the introduction method.

The impurity concentration is relatively high due to the hysteresis characteristics of the MIS type capacitor, for example, 10" atoms-Cm-
``It is desirable that there be more than that.

Next, as shown in the first diagram, by using a technique such as atmospheric pressure CVD, the epitaxial layer (23) with the oxide film pattern (27) left intact is formed to a thickness of several hundred to several hundred.
A silicon nitride film (sial) is deposited on the surface of the silicon nitride film. Silicon nitride film has a higher dielectric constant than silicon oxide film, so it is possible to form a large capacitance. A resist pattern is formed and selectively removed using a dry etching technique such as reactive ion etching (RIE) to form a MIS type capacitor that covers the entire exposed portion of the lower electrode region (28). A dielectric thin film (29) is formed. Then, a CVD oxide film is deposited on the entire surface so as to cover the dielectric thin film (29).

Next, as shown in FIG. 1E, holes are opened in the oxide film (30) on the surface of the base region (27) and the surface of the island (25) of the NPN transistor. By selectively diffusing P), an N8 type emitter region (31) and collector contact region (32) are formed. After that, a non-doped or phosphorus-doped oxide film is deposited again on the entire surface.

Next, as shown in FIG. 1F, a resist pattern (33) made of negative or positive photoresist is placed on the oxide film (30).
), and a desired region on the dielectric thin film (29) is opened by wet etching with hydrochloric acid. In wet etching, the selectivity between silicon oxide film (Sign) and silicon nitride film (SiJ4) is high, so the dielectric thin film (SiJ4) is
29) can be exposed.

However, an oxide film (30) is left on a part of the surface of the dielectric thin film (29) in order to take out the lower electrode region (28) and arrange an electrode thereon.

Next, as shown in Figure 1G, a resist pattern (34) is again formed on the oxide film (30), and this time a dry etching technique such as reactive ion etching is applied to open the silicon nitride film. A contact hole (35) is formed to expose the surface of the lower electrode region (28).At the same time, a contact hole (36) for a pace-emitter-collector contact of the NPN transistor is opened.

For example, in dry etching using CF or gas, silicon oxide film (Si02) and silicon nitride film (sisN
Since the selection ratio of a> is small, six contact holes (35) for the lower electrode region (28) and six contact holes (36) for the base/emitter/collector can be opened at the same time. Figure 1 F
The steps shown in FIG. 1G may be reversed. However, the steps of forming the contact holes (35) and (36) and exposing the surface of the dielectric thin film (29) must not be performed at the same time.

Next, as shown in FIG. 1H, an aluminum layer is formed on the entire surface of the epitaxial layer (23) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode (35) in a desired shape and a dielectric thin film. (2
9) Form the top electrode (36).

According to the above-mentioned manufacturing method of the present application, since the P or N type diffusion region formed before the emitter diffusion step is used as the lower electrode region (28) of the MIS type capacitor, the dielectric thin film (
The manufacturing process 29) can be placed before the emitter diffusion process. Then, there is no need to perform heat treatment for forming the MIS type capacitor between the phosphorus (P) deposit for forming the emitter region (31) and the phosphorus (P) drive-in, and the phosphorus (P) is Immediately from the diffused state, the NPN transistor can be bonded and a heat treatment (drive-in) process for controlling the current amplification factor can be performed. Therefore, there is little variation in the NPN transistor thickness, and the hF
E-control difficulty can be solved.

Further, since the heat treatment conditions for the emitter region (31) can be unified regardless of whether an MIS type capacitor is incorporated, process control for each model becomes extremely easy.

Furthermore, according to the manufacturing method of the present application, the lower electrode region (28)
Since the nitride film (SisN4) can be deposited using the oxide film pattern (27) as it is, there is no need to perform patterning again to form the dielectric thin film (29), which simplifies the process.

(G) As described in detail, according to the present invention, there is little variation in the thickness of the NPN transistor due to the addition of the MIS type capacitor as an optional device, and it is extremely easy to control the h□ of the NPN transistor. It has the advantage of providing a method for manufacturing semiconductor integrated circuits. In addition, since the processing conditions for the emitter region (31) can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model can be simplified, and wafers of different models can be spread in the same manner. It also has the advantage of being able to produce a wide variety of products in small quantities by heat treatment in a furnace.

Furthermore, since the oxide film pattern (27) for forming the lower electrode region (28) and the oxide film pattern (27) for depositing the nitride film (SisNa) can be used in common, it also has the advantage of simplifying the process. .

[Brief explanation of the drawing]

1A to 1H are sectional views for explaining the present invention, and FIG. 2 is a sectional view for explaining a conventional example. (21) is a P-type semiconductor substrate, (26) is a P-type base region, (27) is an oxide film pattern, (28) is a lower electrode region, (29) is a dielectric thin film, and (31) is an emitter region. .

Claims (1)

[Claims] (1) A step of forming a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, and a step of removing impurities of one conductivity type from the surface of the epitaxial layer. A step of forming an isolation region by selective diffusion to form a plurality of islands, and a step of selectively introducing impurities of one conductivity type from the surface of the epitaxial layer to form a vertical bipolar transistor on the surface of one island. Step of forming a base region, selectively removing the insulating film on the surface of the epitaxial layer to form an insulating film pattern, and using this pattern as a mask to introduce impurities of one conductivity type or the opposite conductivity type.
a step of forming a lower electrode region of an IS type capacitor; a step of depositing and forming a dielectric thin film of an MIS type capacitor covering all the openings of the insulating film pattern on the lower electrode region; forming an emitter region of a vertical bipolar transistor by selectively diffusing conductive type impurities, exposing most of the surface of the dielectric thin film, and using dry etching to forming a conductive film on the entire surface, and forming an upper electrode of an MIS type capacitor on the exposed dielectric thin film in the contact hole part; A method of manufacturing a semiconductor integrated circuit, comprising the step of providing an electrode in ohmic contact with the lower electrode region.