JPH01133347A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To control easily the amplification factor of an electric current in an NPN transistor, by using a lower electrode region which is formed by a diffusion process at a collector low resistance region as the lower electrode where MIS type capacity is formed. CONSTITUTION:A lower electrode region 27 which is formed by making use of a diffusion process at a collector low resistance region 26 of an NPN transistor is used as a lower electrode of MIS type capacity and an emitter diffusion process of the NPN transistor is carried out as well after forming a dielectric thin film 30 of MIS type capacity at the surface of the lower electrode region 27 by depositing its film. In this way, deposition of a nitriding film is performed prior to the emitter diffusion process and heat-treatment which makes hFE of the NPN transistor disperse after forming the emitter region 31 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention provides a manufacturing method that facilitates h□ control of an NPN transistor in a semiconductor integrated circuit incorporating an MIS type capacitive element.

(b) Conventional technology Bipolar ICs are mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer serving as a flip-flop. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation process for each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic process as much as possible from the viewpoint of process simplification. Since conditions are set, it is often difficult to integrate the above basic steps alone. Therefore, the basic N
A new process may be added not for the purpose of forming a PN transistor but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, the P+
Diffusion process, R diffusion process and implant resistance formation process to form a resistance region with a different resistivity from the base region, nitride film formation process to form a nitride film capacitor that can obtain a larger capacitance than the MOS type, This includes the process of forming a flefter low resistance region to further reduce the collector series resistance of the NPN transistor, and whether or not to add it is determined by considering the use and purpose of the bipolar IC as well as cost aspects. option process).

The MIS type capacitor formed using the above optional process is shown in Figure 3. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, and (3> is an N1-type buried layer). , (4) is a P+ type isolation region, (5) is an island, (
6) is the N9 type lower electrode region by emitter diffusion, (7
) is a silicon nitride film (51sN) as a high dielectric constant insulator.
a), (8) are upper electrodes made of aluminum material, (
9) is an oxide film, and (10) is an electrode.

Incidentally, an MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056.

(8) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since it uses the emitter region of a PN transistor,
After depositing N-type impurities for forming an emitter region, a nitride film must be formed, and then drive-in of the N-type impurities must be performed. Then, the 8
Because heat treatment at around 00°C diffuses the emitter region,
NPN) transistors have a large variation in hrm (current amplification factor), which has the disadvantage of being difficult to control.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.

(d) Means for Solving the Problems The present invention was developed in view of the drawbacks, and the lower electrode of the MIS type capacitor is formed by using the diffusion process of the collector low resistance region (26) of the NPN transistor. A lower electrode region (27) is used, and after a MIS type capacitor dielectric thin film (30) is deposited and formed on the surface of the lower electrode region (27), an emitter diffusion process of the NPN transistor is performed. do.

(*) Function According to the present invention, the lower electrode of the MIS type capacitor is NPN)-
Since it was formed using the transistor collector low resistance region (26) formation process, the nitride film (sisN4) could be deposited first by the emitter diffusion process, and the NPN transistor's hFt after the emitter region (31) was formed. It is possible to eliminate heat treatment that causes variations in the

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the cross-sectional structure of the semiconductor integrated circuit of the present invention, (
21) is a P-type silicon semiconductor substrate, (22) is a substrate (
21) A plurality of N+ buried layers provided on the surface, (23) is an N-type epitaxial layer m laminated on the entire surface of the substrate (21), and (24) is a P+ layer that penetrates the epitaxial layer ff1 (23). The separation area of the mold (25) is the separation area (24
), an island in which the epitaxial layer (23) is formed in the form of an island, (26) is an NPN (NPN) which reaches from the surface of one island (25) to the buried Jlii (22) - N" type collector low resistance region of the transistor, (27 ) is NPN)
- N9 type lower electrode region (28) of MIS type capacitor formed on the surface of another island (25) different from the island (25) forming the transistor at the same time as the collector low resistance region (26) of the NPN transistor. The P-type base region of the NPN transistor formed on the surface of the one island (25), (29) is the epitaxial layer (23).
) Silicon oxide film (Sin) covering the surface, (30) is a MIS type capacitor dielectric thin film deposited on the surface of the lower electrode region (27), and (31) is formed on the surface of the base region (28). NI type emitter region of the NPN transistor, (32) is an electrode made of aluminum material that makes ohmic contact with each region through a contact hole;
33) is a lower electrode region (27) on the dielectric thin film (30).
) is provided to face the upper electrode. The collector low resistance region (26) serves to reduce the collector resistance of the NPN transistor by being connected to the buried layer (22), thereby forming a low saturation type NPN transistor.

According to the structure of the present application, the collector low resistance region (2
Since the lower electrode region (27) formed at the same time as 6) was used, a low saturation type NPN transistor and an MIS with good characteristics were used.
The mold capacity can coexist efficiently. In addition, the lower electrode area (
Since the formation process of the collector low resistance region (26) of the NPN transistor was used to form the dielectric thin film (3
The formation step 0) can be placed before the emitter diffusion.

Hereinafter, the manufacturing method of the present invention will be explained using FIGS. 2A to 2F.

First, as shown in FIG. 2A, a P-type silicon semiconductor substrate (
21) is selectively doped with N-type impurities such as antimony (Sb) or aluminum (A9) to form an N''-type buried layer (21).
2), and a 5 to 10 μm thick layer of N is formed on the entire surface of the substrate (21).
A mold epitaxial layer (23) is deposited.

Next is the first one! As shown in ffB, the epitaxial layer (22
) By selectively diffusing boron (B) from the surface, P+ type isolation regions (24) are formed that penetrate the epitaxial layer (23) so as to surround the buried Jl (22). The epitaxial layer (23) surrounded by the isolation region (24) forms an island (23) for forming each circuit element.
25〉.

Furthermore, by selectively diffusing N-type impurities such as phosphorus (P) from the surface of the epitaxial layer (23) again, the collector of the N+ type NPN transistor reaching from the surface of the island (25) to the buried layer (22) is A low resistance region (26) and a lower electrode region (27) of an MIS type capacitor are formed. Since the collector low resistance region (26) is formed by saturated diffusion, the impurity concentration on its surface is i o "atom
It will be around s-cm-''.

Next, as shown in FIG. 2C, the base region (28) of the NPN transistor is formed on the surface of the island (25) by selectively ion-implanting or diffusing boron (B) from the surface of the epitaxial layer (23). .

Next, as shown in the second diagram, the thermal oxide film or CVD oxide film (29) on the surface of the epitaxial layer (23) is patterned to form an oxide film pattern having openings in a part of the surface of the lower electrode region (27). and form an epitaxial layer (23)
A silicon nitride film (StJ4) is deposited on the entire surface using a technique such as atmospheric pressure CVD to a thickness of several hundred to several thousand. Then, by selectively removing the silicon nitride film using a technique such as dry etching, a dielectric thin film (30) of an MIS type capacitor is formed. Silicon nitride film (SisNa)
Since Sing has a higher dielectric constant than a silicon oxide film (Sing), it is possible to form a large capacity. After that, an oxide film (2) is formed by CVD to cover the dielectric thin film (30).
9) is deposited.

Next, as shown in FIG. 2E, holes are selectively opened in the oxide film (29) on the surface of the base region (28) of the NPN transistor.
Using this oxide film (29) as a mask, phosphorus (P) is selectively diffused to form an N4'' type emitter region (31).

Next, as shown in FIG. 2F, a negative or positive photoresist pattern is formed on the oxide film (29), the oxide film (29) on the dielectric thin film (30) is removed, and wet or dry etching is performed. A contact hole for electrical connection is opened in a desired portion of the oxide film (29) by the following steps. Then, an aluminum layer is formed on the entire surface of the substrate (21) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned to form an electrode (32) in a desired shape and an upper electrode (33) on the dielectric thin film (30). form.

According to the manufacturing method of the present application, since the lower electrode region (27) formed by the diffusion process of the collector low resistance region (26) is used as the lower electrode forming the MIS type capacitor, the dielectric thin film (30) The manufacturing process can be placed before the emitter diffusion process.

Then, there is no need to perform heat treatment for forming the MIS type capacitor between the phosphorus (P) deposit for forming the emitter region (31) and the phosphorus (P) drive-in, and the phosphorus (P) is Immediate NP from the diffused state
A heat treatment (drive-in) process can be performed to increase the h□ (current amplification factor) of the N transistor.

Therefore, there is little variation in h□ of the NPN transistor, which is due to the inclusion of the MIS type capacitor. Can solve the difficulty of Huntroll. Furthermore, since the heat treatment conditions for the emitter region (31) can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

(G) As described in detail, the present invention has the advantage that a low saturation type NPN transistor and a high performance MIS type capacitor can coexist efficiently. Furthermore, by performing nitride film deposition before forming the emitter region (31), there is little variation in h□ of the NPN transistor, which has the advantage of providing a method for manufacturing semiconductor integrated circuits that is extremely easy to control. . Furthermore, since the processing conditions for the emitter region (31) can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model can be simplified.
Furthermore, it has the advantage that it is possible to produce many different types of wafers in small quantities by heat-treating different types of wafers in the same diffusion furnace.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining the present invention, FIGS. 2A to 2F are sectional views for explaining the manufacturing method of the present invention, respectively.
FIG. 3 is a sectional view for explaining a conventional example. (21) is a P-type semiconductor substrate, (27) is the lower electrode region of the MIS type capacitor, (28> is the P-type base region of the NPN transistor, (30) is the dielectric thin film, (31) is the N
N′″ type emitter region of PN transistor, (33)
is the upper electrode of the MIS type capacitor.

Claims (2)

[Claims] (1) An epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of opposite conductivity type formed on the surface of the substrate, and an epitaxial layer penetrating the epitaxial layer so as to surround each of the buried layers. an isolation region of one conductivity type, a plurality of islands formed by the isolation region, a base region of a vertical bipolar transistor of one conductivity type formed on the surface of one island, and an opposite conductivity type isolation region formed on the surface of the base region. The emitter region of the vertical bipolar transistor, the collector low resistance region of the vertical bipolar transistor of the opposite conductivity type reaching from the surface of the one island to the buried layer, and the collector low resistance region of the other island surface are formed in the same process as the collector low resistance region. a lower electrode region of a MIS type capacitor of opposite conductivity type formed by the method, a dielectric thin film provided to cover a part of the surface of the lower electrode region, and a dielectric thin film that faces the lower electrode region with the dielectric thin film sandwiched therebetween. MI formed on the dielectric thin film so as to
A semiconductor integrated circuit comprising an upper electrode of an S-type capacitor. (2) A step of forming a buried layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, and a step of removing impurities of one conductivity type from the surface of the epitaxial layer. A step of forming an isolation region by selectively diffusing and forming a plurality of islands; a step of selectively diffusing impurities of opposite conductivity type from the surface of the epitaxial layer to form the buried layer and the buried layer on the surface of one island; forming a collector low resistance region of a vertical bipolar transistor to be connected, and simultaneously forming a lower electrode region of an MIS type capacitor on the surface of another island; selectively diffusing impurities of one conductivity type on the surface of the one island; forming a base region of a vertical bipolar transistor by exposing a part of the surface of the lower electrode region, and depositing and forming a dielectric thin film of the MIS type capacitor, forming the dielectric thin film. forming an emitter region of the vertical bipolar transistor by selectively diffusing impurities of opposite conductivity type on the surface of the one island; forming a conductive layer on the entire surface; The above M
1. A method of manufacturing a semiconductor integrated circuit, comprising the step of providing an upper electrode of an IS type capacitor in desired regions, and an electrode that makes ohmic contact with each region.