JPH01133349A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify process control, by using a P-type or an N-type diffusion region which is formed before performing an emitter diffusion process as a lower electrode region having MIS type capacity and coating the surface of a nitriding silicon film acting as a dielectric thin film with a CVD oxide film as well before depositing phosphorus for use in forming an emitter region. CONSTITUTION:A lower electrode region 26 is formed prior to performing an emitter diffusion process and after forming a dielectric thin film 29 having MIS type capacity at the surface of the above region 26, a CVD oxide film 28 is deposited at the whole surface of the thin film so as to cover the dielectric thin film 29. Then, the oxide film is selectively removed and an emitter region 30 of an NPN transistor is formed by depositing N-type impurities. Thus, a heat-treating process which has an effect on hFE of the NPN transistor after forming the emitter region 30 is eliminated and the dielectric thin film 29 is protected from a phosphorus deposit for use in forming the emitter region.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention is directed to a semiconductor integrated circuit incorporating an MIS type capacitive element. The present invention relates to a manufacturing method that facilitates h□ control of an l transistor.

(b) Conventional technology Bipolar IC is a vertical NPN in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector.
It is mainly composed of transistors. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration embedding formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation of each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration being given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, basic NP
A new process may be added not for the purpose of forming an N transistor but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, a P+ diffusion process to form an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion, an R diffusion process to form a resistance region with a different resistivity from the base region, and an implant resistance. These include the formation process, the nitride film formation process to form a nitride film capacitor that can obtain a larger capacitance than the MOS type, and the collector low resistance region formation process to further reduce the collector series resistance of the NPN transistor. The process where it is decided whether or not to add an IC after considering its use, purpose, and cost aspects (
option process).

FIG. 2 shows an MIS type capacitor formed using the above optional process. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N+ type buried layer, (4) is a P'' type isolation region, (5) is an island,
6) is the N+ type lower electrode region due to emitter diffusion, (
7) is a silicon nitride film (Si,
N, ), (8) is an upper part electrode made of aluminum material, (9) is an oxide film, and (1o) is an electrode.

Incidentally, an MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056.

(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since the emitter diffusion process of a PN transistor is used, the entire nitride film formation process must be performed after the emitter region is formed. Then, the heat treatment at around 800''C used when devoting the nitride film diffuses the emitter region, resulting in large variations in h□ (current amplification factor) of the NPN transistor, which has the drawback that it is difficult to control hrt.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.

(d) Means for Solving the Problems The present invention was made in view of the drawbacks, and in a method for manufacturing a semiconductor integrated circuit incorporating an MIS type capacitor, a lower electrode region (26) is formed prior to an emitter diffusion step. death,
A process of forming a dielectric thin film (29) of MIS type capacitance on the surface, and a CVD process on the entire surface so as to cover the dielectric thin film (29).
NPN is formed by depositing an oxide film (28), selectively removing the oxide film, and depositing N-type impurities.
The method is characterized by comprising a step of forming an emitter region (30) of a transistor.

(*) Effect According to the present invention, since emitter diffusion is performed after forming the dielectric thin film (29), the NP after forming the emitter region (30)
N) A heat treatment process that affects the hrt of the transistor can be eliminated. Furthermore, since the emitter diffusion is performed after forming the CVD oxide film (28) to cover the dielectric thin film (29), the dielectric thin film (29) can be protected from the deposit of phosphorus (P) for emitter formation. Can be done.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (
21) by selectively doping N-type impurities such as antimony (Sb) or arsenic (As) to the surface of the N1-type buried Jffi.
(22) to a thickness of 5 to 10μ over the entire surface of the substrate (21).
An N-type epitaxial layer (23) is stacked.

Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the epitaxial layer (23),
Epitaxial layers (
A P1 type isolation region (24) is formed which penetrates through the P1 type isolation region (23). Epitaxial fl? surrounded by isolation regions (24). (
23> is an island (2
5).

Next, as shown in FIG. 2C, by selectively diffusing P or N type impurities from the surface of the epitaxial layer (23), a lower electrode region (26), which will become the lower electrode of the MIS type capacitive element, is formed on the surface of the island (25). Form.

And boron (B) is on the surface of the other island (25).
NPN by selectively ion implanting or diffusing
A base region (27) that will become the base of the transistor is formed. The lower electrode region (26) is an N-type region using phosphorus (P) or antimony (As) or a P-type region using boron (B), and even if the process is performed before the base diffusion process, the base diffusion process It does not matter if it is performed after the base diffusion process or by using the base diffusion process itself, but it is essential to form it before the emitter diffusion. Moreover, the impurity concentration is MI regardless of the diffusion depth of the lower electrode region (26).
Due to the hysteresis characteristics of the S-type capacitance, it is desirable to use a relatively high concentration, for example, 10 ``atoms-cm'' or more.

Next, as shown in the first diagram, the oxide film (28) on the surface of the epitaxial layer (23) is selectively etched away to expose a part of the surface of the lower electrode region (26), and the entire surface of the epitaxial layer (23) is etched. A silicon nitride film (SisN) having a thickness of several hundred to several hundred layers is deposited using a technique such as atmospheric pressure CVD. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance.

A well-known resist pattern is then formed on the surface of the silicon nitride film, and a dielectric thin film (
29).

Next, as shown in FIG. 1E, a non-doped oxide film (28) with a thickness of about 2,000 nm is deposited on the entire surface to cover the dielectric thin film (29) by normal pressure or low pressure CVD method, and then heated to about 800°C. The CVD oxide film (28) is baked at the same temperature.

Next, as shown in FIG. 1F, the base region (26) surface and the island (25) are
The oxide film (28) on the surface is selectively etched to open holes, and an N-type impurity such as phosphorus (P) is diffused using the oxide film (28) pattern as a mask to form the emitter region (30) and collector of the NPN transistor. Contact area (3
1) Form. For example, a liquid source containing phosphorus (P) is used for diffusion, and a phosphorus silicate glass (PSG) film (
32) as the diffusion source. At this time, the surface G of the oxide film (28)
It reacts with the phosphorus (P) of the QPSG film (32) to form a glassy altered layer, but since the surface of the dielectric thin film (29) is protected by the CVD oxide film (28) formed in the previous step, no alteration occurs. do not.

Next, as shown in FIG. 1G, the PSG film (32) is removed using an etching solution of 10 to 30% HF. The glassy altered layer exhibits an etching rate comparable to that of the PSG film (32), and its selectivity is small, making it difficult to control the remaining film thickness of the CVD oxide film (28). 29) silicon nitride film (si
ai<) has not changed in quality, so the silicon oxide film (Si
log), and there is no reduction in the thickness of the dielectric thin film (29) due to etching. Therefore, PSG film (
32) may be removed until the dielectric thin film (29) is exposed, and then a non-doped or phosphorus-doped oxide film is deposited over the entire surface again by CVD. This prevents heat treatment in an oxidizing atmosphere after forming the emitter region (30) to suppress variations in temperature, and thermal oxidation may be used depending on the case.

Next, as shown in FIG.
8) Drill a contact hole for electrical connection in a desired portion. Further, the surface of the dielectric thin film (29) is exposed by wet etching.

Next, as shown in FIG. 1I, an aluminum layer is formed on the entire surface of the epitaxial layer (23) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned to form an electrode (33) of a desired shape and a dielectric thin film. (29)
An upper upper electrode (34) is formed.

According to the manufacturing method of the present application, since the P or N type diffusion region formed before the emitter diffusion step is used as the lower electrode region (26) of the MIS type capacitor, the dielectric thin film (26) is
The manufacturing process 29) can be placed before the emitter diffusion process. Then, there is no need to perform heat treatment for forming the MIS type total capacitance between the deposition of phosphorus (P) for forming the emitter region (30) and the drive-in of phosphorus (P), and the phosphorus (P) is Heat treatment (drive-in) for controlling h□ (current amplification factor) of the NPN transistor can be performed immediately from the initial diffused state. Therefore, there is little variation in hF* of NPN transistors, and hF* due to the built-in MIS type capacitor
□Can eliminate the difficulty of control.

Further, since the heat treatment of the emitter region (30) can be carried out in a single step for a model incorporating an MIS type capacitor and a model without it, process management for each model becomes easy.

Furthermore, prior to the deposition of phosphorus (P) for forming the emitter region (30), the surface of the silicon nitride film (sisNa) of the dielectric thin film (29) is covered with a CVD oxide film (28). This prevents glassing of the surface of the nitride film, thereby preventing reduction in the thickness of the silicon nitride film during etching of the PSG film (32).
The thickness of the dielectric thin film (29) of the MIS type capacitor can be controlled extremely accurately.

(G) As described in detail, according to the present invention, there is almost no variation in h□ of the NPN transistor due to the addition of the MIS type capacitor as an optional device, and the control of the NPN transistor is extremely easy. It has the advantage of being able to provide a method for manufacturing semiconductor integrated circuits. In addition, the surface of the silicon nitride film (Si8N4) of the dielectric thin film (29) was
Since it protects the D oxide film (28)-C'', there is no reduction in the thickness of the silicon nitride film, and it has the advantage that the thickness of the dielectric thin film (29) can be controlled extremely accurately. Since the processing conditions for the emitter region (30) can be unified for different types of models and models that are not, process management for each model can be simplified, and furthermore, wafers of different models can be heat-treated in the same diffusion furnace. It also has the advantage of making it possible to produce small quantities of models.

[Brief explanation of the drawing]

1A to 1I are sectional views for explaining the present invention, and FIG. 2 is a sectional view for explaining a conventional example. (21) is the P-type semiconductor substrate, (26) is the lower electrode region of the MIS type capacitor, (27) is the P-type semiconductor substrate of the NPN transistor.
(28) is the oxide film, (29) is the dielectric thin film, <30) is the N+ type emitter region of the NPN transistor, and (34) is the upper electrode.

Claims (1)

[Claims] (1) A step of forming a buried layer of an opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, and a step of separating the epitaxial layer into a plurality of layers. A step of forming an island on the surface of one island, forming a lower electrode region of one conductivity type or the opposite conductivity type, which becomes the lower electrode of the MIS type capacitor, and forming a lower electrode region of one conductivity type or the opposite conductivity type on the surface of the other island, in a process different from that of the lower electrode region or in the same process as the lower electrode region. forming a base region of one conductivity type of the vertical bipolar transistor by a process, exposing a part of the surface of the lower electrode region;
a step of depositing and forming a dielectric thin film of S-type capacitance, a step of depositing a CVD oxide film over the entire surface so as to cover the dielectric thin film, selectively removing the oxide film on the surface of the epitaxial layer,
forming an emitter region of a vertical bipolar transistor by diffusing impurities of opposite conductivity type using this oxide film as a mask; forming a conductive film on the entire surface;
A method for manufacturing a semiconductor integrated circuit, comprising the step of providing an upper electrode of an IS type capacitor, and an electrode in ohmic contact with the lower electrode region on the surface of the lower electrode region.