GB2060253A - MIS Capacitors - Google Patents

Abstract

A metal-oxide semiconductor capacitor of substantially reduced internal resistance, is formed by making a plurality of generally parallel, spaced-apart, mutually electrically connected ohmic contacts 109 to a semiconductor substrate, serving as a first capacitor plate, interdigitating dielectric material with the ohmic contacts, and overlaying the dielectric material with conducive material 103 serving as a second capacitor plate. <IMAGE>

Description

SPECIFICATION Low Resistance Interdigitated Contact MOS Capacitor Background of the Invention 1. Field of the Invention The present invention relates to metal-oxidesemiconductor ("MOS") capacitors, and more particularly, to MOS capacitors with low resistance interdigitated electrical contacts.

2. Prior Art Prior art MOS capacitors are typically multilayered devices consisting of a doped semiconductor substrate acting as one capacitor plate, a dielectric layer, and a metallized top layer acting as the second plate of the capacitor.

Typically, one electrical connection to the device is made to the metallized top plate, and the second connection is made to the bottom of the semiconductor substrate.

In some applications it is desirable to have both terminals of the MOS capacitors accessible on the top face of the multilayered device. Prior art MOS capacitors having such top mounted contacts are constructed by forming an ohmic contact through an etched hole in the dielectric layer to one edge of the bottom substrate capacitor plate, and in electrical isolation from the metalized top capacitor plate. However, such a structure has a very low ratio of reactance to resistance (hereinafter "Q factor") at high frequencies (1-4 gigahertz). The resistive component of the device impedance dominates at such frequencies because the ohmic contact to the bottom plate silicon substrate has a limited current cross-section.Another contribution to the resistance of the device results from the long mean current path length in the bottom substrate, caused by placing the contact along one of the edges of the substrate.

The overall properties of the described prior art structure at high frequencies are electrically equivalent to a resistor in series with a small capacitor. This restricts the number of applications in which such a device may be used, since the relatively high resistance results in an undesirably low Q factor for the capacitor, typical values being 30-40 in a 50 picofarad device.

The present invention overcomes these shortcomings of the priot art by forming contacts to the bottom plate through a multitude of openings in the dielectric. A plurality of bottom substrate contacts are interdigitated with a plurality of conductive contacts forming the top plate. This innovative structure reduces the contact resistance to the lower plate by increasing the overall current cross-section of the contacts and reducing the mean current path length in the bottom substrate to the contacts.

Interdigitated contact geometries have been used previously in integrated circuitry but never for the purpose of reducing the Q factor of a MOS capacitor.

Sauerman, et al. (U.S. patent No. 3,906,539) for example, discloses an interdigitated geometry for a diode-capacitance device wherein the interdigitation of a field electrode serves to diminish the reduction of an inversion layer adjacent to a P-N junction.

Similarly, Lehmann (U.S. Patent No.

3,675,095) discloses a thick film capacitor wherein an interdigitated electrode geometry is utilized to insure a high tolerance for the value of the capacitor.

Neither of these devices disclose a method for reducing the series resistance (and thus increasing the Q factor) of a MOS capacitor by increasing the ohmic contact area to the semiconductor plate of the capacitor and reducing the mean current path in that plate to its electrical terminal.

Accordingly, an object of the present invention is to reduce the resistive impedance of a MOS capacitor and allow a high Q factor at high frequencies by utilizing an interdigitated contact geometry to increase the current cross-section of the ohmic contacts made to the semiconductor substrate plate of the capacitor.

Another object of this invention is to further reduce the resistive impedance of a MOS capacitor by reducing the mean current path length in the semiconductor plate to its terminal contacts by means of interdigitating those electrical contacts, which penetrate the dielectric, with the electrical contacts forming the top capacitor plate.

Summary of the Invention The present invention discloses a low resistance interdigitated electrical contact geometry for a MOS capacitor. The device is fabricated on a doped semiconductor substrate, typically of silicon. The substrate functions as the lower plate of the capacitor. A dielectric layer, typically consisting of silicon oxide or silicon nitride, is then applied on top of the substrate.

Next, multiple parallel electrical contacts in spaced relationship are made to the substrate by chemically removing parallel oblong strips of the dielectric by known photoetch methods, and then depositing ohmic contacts, typically of platinum silicide, in the gaps created thereby and in electrical contact with the substrate. The unremoved dielectric is thus interdigitated with the ohmic contacts. The ohmic contacts are then metallized on their top surfaces and electrically connected along at least one edge of the capacitor. Provision is made for connecting the metal-covered contacts to external circuitry at either the top or bottom of the device.

Interdigitated between the bottom plate ohmic contacts, and in spaced relation with them, are conductive strips deposited on top of the unremoved dielectric layer. These conductive strips are electrically connected together, and form the second, or top, plate of the capacitor.

In operation, electrical charge is stored on the conductive strips of the top plate of the capacitor and on the bottom plate semiconductor substrate, thereby forming an electric field in the unremoved dielectric layer. The multiple ohmic contact strips connected to the substrate provide a reduced resistance to current flow by affording greater contact area than prior art contacts. Further, resistance is reduced by minimizing the effective mean current path length in the bottom capacitor substrate to its multiple ohmic contacts. Such reduced resistance affords high Q values for the capacitor at high frequencies, typically allowing a Q factor of as much as 100-300 at 1 gigahertz for a 50 picofarad capacitor.

Brief Description of the Drawings The invention will be further described in connection with the accompanying drawings, in which the numbers in different Figures describe like parts: Figure 1 is a top view of a low resistance interdigitated contact MOS capacitor.

Figure 2 is a view in vertical cross-section of a low resistance interdigitated contact MOS capacitor along line 2-2' of Figure 1.

Figure 3 is a detailed vertical cross-sectional view of a plated-through conductive groove in the substrate of the present invention, along line 33' of Figure 1.

Figure 4 is a detailed top view of the present invention.

Figure 5 is a sectional perspective view of a prior art top contact MOS capacitor.

Detailed Description Figure 1 is a top view of the present invention, showing the interdigitated electrical contact geometry of the preferred embodiment. A doped semiconductor substrate 100, typically of silicon, serves as a first, or bottom, plate of a MOS capacitor. The top plate 102 of the capacitor comprises a multitude of parallel thin metallic (or conductive) fingers 103 in spaced-apart relationship. The top plate metallic fingers 103 extend laterally across the capacitor substrate 100 from both sides of a central region 105 which is common to all of the top plate fingers 103. A bonding pad 106 overlaying the central region 105 is provided for convenient electrical connection of the top plate 102 to external circuitry.

The electrical contacts to the bottom plate semiconductor substrate 100 comprise a multitude of parallel metallic (or conductive) strips 107 radiating inward from opposing edges of the substrate 100 and interdigitated with the parallel fingers 103 of the top plate 102, and in spacedapart relationship to said top plate fingers 103 as is shown in Figure 2. It should be noted that the top plate fingers 103 and bottom plate contact strips 107 are electrically isolated by a separating gap. All of the bottom plate contact strips 107 on each side of the top plate central region 105 are electrically connected along their respective edge of the substrate 100 by a conductive interconnection bus 108.

Referring now to Figure 2, each of the bottom plate contacts 107 overlays a corresponding ohmic contact 109, typically of platinum silicide.

(In Figure 1, the ohmic contacts 109 are seen as long rectangles in outlined relief within the confines of the bottom plate contact strips 107).

However, as an alternative embodiment, certain other materials, such as aluminum, could be used in place of the distinct ohmic contacts 1 09 and the overlying metallic contact strips 107, since such other materials are suitable for bonding purposes and also form adequate ohmic contacts to a semiconductor substrate.

It is to be noted that the ohmic contacts 109 are also interdigitated with the top plate fingers 103.

Associated with each of the ohmic contacts 109, is an elongated opening through the dielectric 1 10, the openings thereby allowing direct physical and electrical contact between the ohmic contacts 109 and the bottom plate semiconductor substrate 100. As is shown in Figure 2, each of the top plate fingers 103 is insulated from the bottom plate semiconductor substrate 100 by an associated dielectric underlayer 1 10, typically formed of silicon oxide or silicon nitride. It is to be noted that the dielectric material 110 underlying the top plate fingers 103 is also interdigitated with the bottom plate contact strips 107 and the ohmic contacts 109. Figure 4 shows a detailed view of the present device, including the sloping edge of the bottom plate contact strips 107 where said strips conform to the underlying ohmic contacts 109.

Referring once more to Figure 1, the two interconnection buses 108 are accessible for connection to external circuits at the top of the capacitor structure by attaching leads directly to their exposed surface. In such a configuration, the two buses 108 are usually electrically connected together. Alternatively, referring now to Figure 3, the interconnection buses 108 are accessible, via conductive contact 1 13, for connection to external circuitry at the bottom of the capacitor substrate 100 by means of associated conductive plated-through grooves 1 12 in the substrate 100, each electrically connected to a nearby bus 108.

A A plated-through groove 1 12 is formed by etching a V-shaped groove at the edge of the substrate 100 to a depth of only few microns from the bottom surface of the substrate, and then forming an ohmic contact 1 14 within the groove. A metallic overlay 11 6 is then formed over the ohmic contact 1 14, which may be electrically connected to a nearby interconnection bus 108 as desired. The few microns of a semiconductor substrate 100 remaining beneath the groove vertex and separating the ohmic contact 114 and conductive contact 113 offer negligible resistance to electric current flow in comparison to the resistance of the entire substrate thickness. The conductive contact 1 13 may be formed on the bottom side of the substrate by conventional means.

In operation, the interdigitated top contact MOS capacitor is electrically connected to external circuitry by means of the bonding pad 106, acting as one terminal of the capacitor, and either the interconnection buses 108 or the bottom conductive contact 11 3, acting as the second terminal of the capacitor. When an electrical source is applied to these terminals, charge can be stored on the top plate fingers 103 and the bottom plate semiconductor substrate 100, which are separated by the dielectric layer 110. The geometry of the present invention provides for a reduction in the total contact resistance to the bottom plate substrate 100 by the use of a multitude of ohmic contacts 109 connected thereto in parallel, thereby significantly increasing the total bottom plate electrical contact area compared with the prior art.Further, the resistive component of the capacitor impedance is also diminished by reducing the mean current path length in the bottom plate semiconductor substrate 100 to the multiple ohmic contacts 109.

In prior art top contact MOS capacitors, as shown in Figure 5, the ohmic contact 121 to the bottom plate substrate 122 is made through an oblong hole formed through the dielectric 123 and in electrical contact with the bottom plate 100 along one of its edges. The top capacitor plate 124 overlays the ramaining dielectric 123, but in electrical isolation from the bottom plate ohmic contact 121. In such a device, the mean current path length in the bottom plate 122 is effectively half the horizontal width of the device.

In the present invention however, the maximum current path length in the bottom plate substrate 100 of Figure 2 is one half of the distance between adjacent ohmic contacts 109, thereby reducing the resistive component of the device impedance due to the resistance of the substrate 100.

The reduction in resistance accomplished by the interdigitated contact geometry of the present invention provides for a high Q factor value at high frequencies, typically a factor of over 100 for a 50 picofarad device operated at 1 4 gigahertz.

The capacitance of the present invention may be altered by varying the number of interdigitated bottom plate contacts 107 with their associated ohmic contacts 109 and the top plate fingers 103. Alternatively, the thickness of the dielectric layer may be varied to alter the capacitance of the device. Direct capacitance between the interdigitated bottom plate metallic contacts 107 or ohmic contacts 109 and the top plate fingers 103 is very slight, typically about 1% of the total capacitance.

While a specific embodiment of the low resistance interdigitated top contact MOS capacitor device has been described, since variations will occur to those skilled in the art the scope of the present invention is not limited to this particular embodiment. Rather, the scope is set forth in the following claims.

Claims (6)

Claims

1. A metal-oxide-semiconductor capacitor, comprising: a doped semiconductor substrate; a plurality of spaced-apart ohmic electrical contacts affixed to the upper surface of said substrate, said ohmic contacts being electrically connected together; a dielectric material interspersed with said ohmic contacts and affixed on the upper surface of said substrate; and conductive material overlaying said dielectric material, said conductive material being electrically isolated from said ohmic contacts, and being electrically connected together.

2. A metal-oxide-semiconductor capacitor, comprising: a doped semiconductor substrate; a plurality of generally parallel spaced-apart ohmic electrical contacts affixed to the upper surface of said substrate, said ohmic contacts being electrically connected together; a dielectric material interdigitated with said ohmic contacts and affixed on the upper surface of said substrate; and conductive material overlaying said dielectric material, said conductive material being electrically isolated from said ohmic contacts, and being electrically connected together.

3. A metal-oxide-semiconductor capacitor comprising: a doped semiconductor substrate; a first set of generally parallel spaced-apart ohmic electrical contacts affixed to the upper surface of said first substrate, said first set of ohmic contacts being arrayed juxtaposed and perpendicular to a first edge of said substrate, being terminated less than halfway across said substrate, and being electrically connected together along the ends juxtaposed to said first edge of said substrate;; a second set of generally parallel spaced-apart ohmic contacts affixed to the upper surface of said substrate, said second set of ohmic contacts being arrayed juxtaposed and perpendicular to a second edge of said substrate, said second edge being parallel to said first edge, said second set of ohmic contacts being terminated less than halfway across said substrate and being electrically connected together along the ends juxtaposed to said second edge of said substrate; a dielectric material interdigitated with said first and second sets of ohmic contacts and affixed on the upper surface of said substrate; and conductive material overlaying said dielectric material said conductive material being electrically isolated from said first and second sets of ohmic contacts, and being electrically connected together by a central conductive region parallel to and approximately midway between said first edge and said second edge of said substrate.

4. The capacitor according to any preceding claim wherein said ohmic contacts are overlayed with conductive material before electrically connecting together said ohmic contacts.

5. The capacitor according to claim 1, claim 2 or claim 3 further comprising at least one conductive plated-through groove in said semiconductor substrate, said plated-through groove being electrically connected to said ohmic contacts.

6. A capacitor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.