DE3034445A1 - MOS CONDENSER - Google Patents

Description

PATENTANWÄLTE ZENZ & HELBER ■ £> .4ί · 0θ ESSEN T- AW RXiHRSTEIN 1 · TEL .: (Ο2Ο1) 412687 Page . - - - T 110

TRW INC.
10880 Wilshire Blvd., Los Angeles, California 90024, V.St.A.

MOS capacitor

Known MOS capacitors are typically multilayered Components that have a doped semiconductor substrate acting as a capacitor plate, a dielectric Layer and have a metallic cover layer acting as a second plate of the capacitor. There are in the '■ Usually an electrical connection to the metallic cover plate and a second connection to the bottom part of the semiconductor substrate .

For some applications it is desirable to have both terminals of the MOS capacitor from the top of the multilayer To make component accessible from. In known MOS capacitors with those attached to the top Contacts is an ohmic contact through an etched hole in the dielectric layer to an edge of the bottom substrate capacitor plate and formed by electrical insulation from the metallized capacitor cover plate. However, such a structure has a very low reactance / resistance ratio (hereinafter "Q factor" called) at high frequencies (1-4 gigahertz). At such frequencies, the ohmic component of the impedance dominates of the component, since the ohmic contact to the silicon substrate forming the base plate has a limited current

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Has passage cross-section. Another contribution to the ohmic resistance of the component results from the relatively long mean current path length in the soil substrate, due to the arrangement of the contact along one of the edges of the substrate.

The overall characteristics of the described known Structure are electrically equivalent to one with a small capacitor in series at high frequencies switched resistor .. This limits the number of possible uses for such a component. since the relatively high resistance leads to an undesirably low Q factor of the capacitor, which is typically 30-40 for a 50 picofarad device.

• The invention is based on the object of the ohmic resistance, in particular the contact resistance of MOS capacitors to reduce thereby that the current passage cross-section of the ohmic contacts to the semiconductor substrate plate of the capacitor increases and the mean current path length in the semiconductor plate to the Contacts is reduced in order to achieve a high Q factor, especially at high frequencies.

For this purpose, contacts to the substrate plate on the bottom side are made through a large number of openings in the Dielectric.formed. A variety of soil substrate contacts are in interdigitated configuration with a plurality of conductive ones forming the cover plate Contacts provided. Due to this intermeshing contact geometry, the current passage cross-section of the ohmic contacts to the semiconductor substrate plate of the Capacitor enlarged, and due to the interlocking Arrangement of the electrical intervening in the dielectric Contacts with the electrical contacts forming the cover-side capacitor plate becomes the mean current path length in

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the semiconductor plate to the terminal contacts is considerably reduced.

U.S. Patent 3,906,539 (Sauermann et al.) Discloses an interlocking Contact geometry for a diode capacitance component known per se, the tooth-shaped design and arrangement of a field electrode there, however, to reduce one adjacent to a pn junction Inversion layer is used.

According to US Pat. No. 3,675,095 (Lehmann), there is a thick film capacitor with an interdigitated electrode geometry provided for the purpose of ensuring a high tolerance of the value of the capacitor.

However, it is new and surprising in the art that interlocking contact geometry in integrated circuit technology for the purpose of reducing the series resistance and thus increasing the Q factor of a MOS capacitor can be used, the ohmic contact zone to the semiconductor plate of the Capacitor is increased and the mean current path length in this' plate for electrical connection is reduced.

The invention provides a MOS capacitor is provided, the electric by interlocking or nested contact geometry low "active ¹ 'resistance has. The component wird.auf a doped semiconductor substrate formed in typical embodiments from silicon. The The substrate serves as the lower plate of the capacitor. A dielectric layer, which in a preferred embodiment consists of silicon oxide or silicon nitride, is then applied to the top of the substrate

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Strips of the dielectric are removed by known photo-etching methods and then ohmic contacts, as a rule, are removed Platinum silicide are deposited in the crevices thus formed and in electrical contact with the substrate. The remaining dielectric then has an interlocking or nested geometry with the ohmic Contacts. The ohmic contacts are then metallized on their upper sides and at least along them an edge or an edge of the capacitor is electrically connected or connected. The metal-plated contacts are either on the top or the bottom of the component is connected to an external circuit.

In an interlocking arrangement between the ohmic base plate contacts and at a distance from them are conductive ones Strips are deposited on the top of the remaining portion of the dielectric layer. This senior Strips are electrically connected together and form the second or top plate of the capacitor.

In operation, electrical charge is stored on the conductive strips of the top plate of the capacitor and on the semiconductor substrate forming the bottom plate, as a result of which an electrical field is formed in the remaining part of the dielectric layer. The ohmic multiple contact strips are connected to the substrate in order to create a reduced resistance for the flow of current, in that a larger contact zone is made available than with contacts of conventional components of the same type. Der.Widerstand is also reduced in that the effective mean current path length in the bottom substrate of the capacitor for the ohmic multiple contacts is minimized. Such reduced resistance gives high Q values for the capacitor at high frequencies and allows a Q factor of 100-300 at 1-4 gigahertz for a typical 50 picofarad capacitor.

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The invention is explained in more detail below with reference to an exemplary embodiment shown in the drawing. In the drawing show:

Fig. 1 is a plan view of an embodiment of the MOS capacitor according to the invention a (comb-shaped) interlocking contact geometry to reduce the (ohm- ■ see) resistance;

Figure 2 is a vertical cross-sectional view of the MOS capacitor taken along section line 2-2 in Fig. 1;

Fig. 3 is a more detailed sectional view along the

Section line 3-3 of FIG. 1 by a waste t cut of the substrate, in which a lei

tend groove is formed;

4 shows a more detailed illustration of part of the capacitor from above; and

Fig. 5 is a perspective sectional view through a known MOS capacitor with a contact on the deck side.

Fig. 1 shows a plan view of an embodiment of the new MOS capacitor in which the interdigitated finger-shaped Geometry of the electrical contacts can be seen. A doped semiconductor substrate 100, which in typical Made of silicon, it serves as the first or bottom plate of the MOS capacitor. The cover plate 102 of the capacitor has a plurality of parallel, thin, more metallic (or conductive) fingers 103, which are in mutual Are arranged spaced. The cover-side metallic fingers 103 extend laterally over the capacitor substrate 100 from both sides of a central region 105 which is common to all fingers 103 on the cover. A connector lug 106, which is arranged above the central area 105, is used for the appropriate electrical connection of the cover plate 102 to external circuits.

The electrical contacts to the one forming the base plate

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Semiconductor substrate 100 have a plurality of parallel metallic (or conductive) strips 107, which extend from opposite edges of the substrate 100 extend and between the parallel fingers 103 of the cover plate 102 in a comb-like manner and at a distance from them (Fig. 2) intervene. It should be noted that the top plate fingers 103 and the bottom plate contact strips 107 by a separating gap are electrically isolated. All floor slab contact strips 107 on each side of the central region extend along the associated edge of the substrate 100 a conductive connecting bar 108 connected together.

Reference is made to FIG. 2 below. Everyone who Base plate contacts 107 covers a corresponding ohmic contact 109, which is typically made of platinum silicide consists. (In Fig. 1, the ohmic contacts are as strip-shaped rectangles within the limits of the Floor panel contact strips 107. Alternatively, other materials, e.g. Aluminum in the place of the special ohmic contacts .109 and as overlying metallic contact strips can be used as such other materials are suitable for connection purposes and suitable ohmic contacts form for a semiconductor substrate.

It should be noted that the ohmic contacts 109 also mesh with the cover plate fingers 103 in a comb shape.

Each of the ohmic contacts 109 is assigned an elongated opening through the dielectric 110, the Openings provide direct mechanical and dielectric contact between the ohmic contacts 109 and the die Allow semiconductor substrate 100 forming the bottom plate. As shown in Figure 2, each of the cover plate is fingers 103 from the bottom plate semiconductor substrate 100 by a

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associated dielectric layer 110, which is typically made of silicon oxide or silicon nitride consists. It should be noted that the dielectric material arranged under the cover plate fingers 103 is also used 110 with the base plate contact strips 107 and the Ohmic contacts 109 intermeshing in a comb shape is arranged. Fig. 4 shows a more detailed view of the component described with the inclined edge of the Base plate contact strips 107, where the contact strips are adapted to the shape of the ohmic contacts 109 below are.

Reference is again made to FIG. 1 below. The two connecting rails 108 are for connecting external ones Circuits on top of the capacitor structure by attaching leads directly to its exposed Surface accessible. With such a configuration the two connecting rails 108 are usually electrically connected together. In an alternative arrangement and referring to FIG. 3, the connecting bars 108 are accessible via a conductive contact 113, which is a Connection to an external circuit from the bottom side of the capacitor substrate 100 by means of associated through-plated Allows grooves 112 in the substrate 100, each of the plated-through grooves 112 with a nearby Connecting bar 108 is electrically connected. A through-plated groove 112 is formed by etching. a V-shaped Groove on the edge of the substrate 100th formed, the groove only ends a few µm from the bottom surface of the substrate whereupon an ohmic contact 114 is formed within the groove. A metallic coating layer 116 is then formed over the ohmic contact 114, which is then in the desired Way is electrically connected to the nearby connecting rail 108. The remaining few yum of the semiconductor substrate 100 below the top of the groove, which the

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Separate ohmic contact 114 from the conductive contact 113, form a compared to the resistance of the total substrate thickness negligible resistance for the flow of electrical current. The leading contact 113 can be formed on the bottom side of the substrate by conventional means.

In operation, the MOS capacitor with comb-shaped interlocking cover contacts is used as a capacitor connection serving terminal lug 106 and either the connecting bar 108 or the bottom-side conductive Contact 113 connected as a second capacitor connection to an external circuit. When an electrical power source is applied to these terminals, charge can flow to and from the cover plate fingers 103 The semiconductor substrate 100 separated from the dielectric layer 110 and forming the bottom plate can be stored. The geometry described leads to a reduction in the total contact resistance to the base plate substrate 100 due to the use of a plurality of ohmic contacts 109 which are arranged in parallel with the substrate are connected, whereby the existing electrical contact zone to the base plate compared to conventional Capacitor designs is considerably enlarged. Also, the resistance component is related to capacitor impedance also reduced by the fact that the mean current path length in the bottom plate semiconductor substrate 100 to the Ohmic multiple contacts 109 is reduced.

In the case of known MOS capacitors with contact on the top, one of which is shown in Fig. 5, the ohmic contact 121 to the bottom plate substrate 122 is made by an elongated one Hole made that goes through the dielectric 123, the ohmic contact 121 with the bottom plate 122 is made along one edge thereof. the

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Cap-side capacitor plate 124 spans the remaining dielectric 123 and is from the ohmic contact 121 to Electrically insulated base plate. In the case of such a component, the mean current path length is in the base plate 122 effectively equal to half the horizontal width of the component.

In the training according to the invention, however, is the maximum Current path length in the bottom plate substrate 100 (FIG. 2) is equal to half the distance between adjacent resistive ones Contacts 109, whereby the (active) resistance component of the component impedance caused by the Resistance of the substrate 100 is reduced.

The reduction in the effective resistance due to the comb-shaped interlocking contact geometry results in a high Q-factor at high frequencies, in typical execution a factor of more than 100 for 50 pF components, which operate at 1-4 GHz.

In the embodiment according to the invention, the capacitance of the component can be changed by changing the number of base plate contacts 107 interlocking in a comb shape and the associated ohmic contacts 109 and cover plate fingers 103. In an alternative embodiment, the thickness of the dielectric layer can be changed in order to change the capacitance of the component. The direct capacitance between the interlocking base plate contacts 107 or the ohmic contacts 109 and the cover plate fingers 103 is very low and is typically around 1 % of the total capacitance.

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Claims (6)

PATENTANWÄLTE 2ENZ & HELBER: .Ο 4300 "frSSEN'i · * ΛΜ RUHfiSTEIN 1 · TEL .: (0201) 412687 Page - ** - * T 110 TRW INC. Claims 1. MOS capacitor with a doped semiconductor substrate, characterized in that a plurality of mutually spaced, ohmic electrical Contacts (109, 107) attached to the top of the substrate (100) and electrically connected to one another are that between the ohmic contacts (109, 107) strips of dielectric material (110) on the surface of the substrate (100) are arranged and that on the Streif.en of dielectric material (110) strips Conductive material (103) are arranged, which are electrically isolated from the ohmic contacts (109, 107) and from one another are electrically connected. 2. MOS capacitor according to claim 1, characterized in that the ohmic electrical contacts (109, 107) in parallel run towards each other and in a comb shape with the strips interdigitated dielectric material (110). 3; MOS capacitor according to Claim 1 or 2, characterized in that that at least one fully plated conductive groove (1L2, 114) is provided in the semiconductor substrate (100), which is electrically connected to the ohmic contacts (109, 107). 130016/0671 Z / bu. 4. MOS capacitor according to one of claims 1 to 3, characterized in that a first group of generally ohmic electrical contacts (109, 107) running parallel and at a mutual distance on top of the doped semiconductor substrate (100) ' adjacent and at right angles to a first edge of the substrate (100), less than half of the Substrate spanned and electrically connected together at the ends adjacent to the first edge of a substrate is that a second group of parallel, mutually spaced ohmic contacts (109, 107) is attached to the top of the substrate (100), from one parallel to the first edge of the substrate Edge goes out and runs at right angles to this, spans less than half of the substrate and on the ends adjacent to the second edge of the substrate is electrically connected together, that both the first and the second group of ohmic contacts is interlocked with strips of dielectric material (110) and that the strips of conductive material (103) covering the dielectric material from both the first ohmic contact group as well as the second ■ ohmic contact group and electrically isolated by a central conductive area (106) that is parallel and approximately midway between the first and second edges of the substrate is electrically connected. 5. MOS capacitor according to claims 3 and 4, characterized in that the plated-through groove (112, 114) is connected to at least one of the first or second group of ohmic contacts (107, 109). 130016/0671 _{! f} OFHGiNAL INSPECTED 6. A method for producing a capacitor according to any one of claims 1 to 5, characterized in that several Ohmic electrical contacts (109) at a mutual distance on the top of a doped semiconductor substrate (100) applied between zones (HO) made of dielectric material protruding from the top side of the substrate and with conductive Material (107) are coated and then electrically connected to one another at least in groups. 130016/0671