JPH01133354A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To make exceedingly easy control of hFE of an NPN transistor and simplify process control for each device, by forming a lower electrode region having MIS type capacity and a dielectric thin film and after that, in addition to performing emitter diffusion, by arranging lower electrodes at the lower electrode region in the form of the teeth of a comb. CONSTITUTION:A part of the surface of a lower electrode region 26 of an oxide film 27 which is formed at the surface of an epitaxial layer 23 is exposed and a resist pattern is formed by depositing a nitriding silicon film Si3N4 and then, its pattern is coated with a dielectric thin film 28 to deposit an oxide film 27. Holes of the oxide film 27 are made at the surfaces of a base region 32 and islands 25 and N<+> type emitter and collector contact regions 33 and 34 are formed by diffusing selectively phosphorus P. The resist pattern is formed on the oxide film 27 and contact holes are made so as to perform electrical connection at desired parts. An aluminum layer is formed at the whole surface of the epitaxial layer 23 and electrodes 35 having desired forms, an upper electrode 29 on the dielectric thin film 28 as well as a lower electrode 30 are formed by performing a patterning step again.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention provides a manufacturing method that facilitates the h-control of an NPN transistor in a semiconductor integrated circuit incorporating a resistance element formed by ion implantation.

(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor formed by doubly diffusing a base and an emitter on the surface of a semiconductor layer serving as a flip-flop. Therefore, the base and emitter diffusion process for manufacturing the front NPN transistor is an essential process, as well as the high concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation of each element. This is an indispensable process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for electrical connection and the electrode formation process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the process conditions for the base and emitter expansion 11 are set with the utmost importance placed on the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter expansion 11 using only the basic process. Therefore, a new process may be added not for the purpose of forming a basic NPN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, the P1 diffusion process to form an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion, the R diffusion process to form a resistance region with a different resistivity from the base region, and the implant resistance. Forming process, M.O.
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than S-type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN transistors, all of which are used for bipolar ICs. This is a step (optional step) in which it is decided whether or not to add it after consideration from the viewpoint of purpose, cost, and cost.

The MIS type capacitor formed using the above optional process is shown in Figure 3. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, and (3) is an N0-type buried layer. , (4) is a P+ type isolation region, (5) is an island, (
6) is an N+ type lower electrode region by emitter diffusion, (7
) is a silicon nitride film (Si, N
4), (8) are upper electrodes made of aluminum material, (
9) is an oxide film, and (10) is an electrode. Incidentally, as an MIS type capacitor using a nitride film, for example, Japanese Patent Application Laid-Open No. 60-24
It is described in Publication No. 4056.

(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since the emitter diffusion process of a PN transistor is used, a nitride film must be formed after N-type impurities for forming an emitter region are deposited, and then the N-type impurities must be driven in.

Then, the heat treatment at around 800°C used when depositing the nitride film re-diffuses the emitter region, resulting in large variations in the h□ (current amplification factor) of the NPN transistor.
It had the disadvantage that it was difficult to hunt down.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.

(d) Means for Solving the Problems The present invention has been made in view of the serious drawbacks, and in a method of manufacturing a semiconductor integrated circuit incorporating an MIS type capacitor, the MIS type capacitor is The lower electrode area of the capacitor (26) and the dielectric thin film (
28) is formed, and then the emitter of the NPN transistor is diffused, and a lower electrode (30) is arranged in a comb-like shape to make ohmic contact with the lower electrode region (26).

(E) Operation and Use According to the present invention, the region formed before forming the emitter region (30) is used as the lower electrode without using emitter diffusion, and the emitter diffusion is performed after depositing the nitride film. (30) ha of NPN transistor after formation
A heat treatment step that affects t can be eliminated.

Furthermore, since the formation of the lower electrode region (26) is arranged in the first half of the process, the impurity concentration on the surface of the lower electrode region (26) decreases and the extraction resistance of the lower electrode (30) increases. Since the lower electrode (30) is arranged in a comb-teeth shape, the resistance to take out the lower electrode (30) can be reduced.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

1A and 1B show the semiconductor integrated circuit of the present invention, (21) is a P-type silicon substrate, (22) is a substrate (21).
) N′″ type buried layer provided on the surface, (23) is the substrate (2
1) N-type epitaxial layer laminated on the entire surface, (24) is a P+ layer that penetrates the epitaxial layer (23)
The isolation region of the mold (25) is an island in which the epitaxial layer (23) is formed into an island shape by the isolation region (24);
(26) is the lower electrode region of the P-type or N-type MIS type capacitor formed on the surface of the island (25), and (27) is the silicon oxide film (SiO2) covering the surface of the epitaxial layer (23).
*), (28) is a dielectric thin film made of a silicon nitride film (sisNa) deposited on the surface of the exposed lower electrode region (26), and (29) is a dielectric thin film formed on the surface of the lower electrode region (26). upper electrode consisting of a layer of aluminum (30
) are the lower electrode area (26) and the contact hole (31)
This is the lower electrode that makes ohmic contact through the .

The lower electrode region (26) is an example of the isolation region (24) forming process.
Although it is formed by high impurity concentration diffusion, the surface concentration decreases because it is diffused quite deeply and because it is formed in the first half of the process. Removal resistance increases,
The voltage dependence, frequency dependence, and hysteresis characteristics of the MIS type capacitor deteriorate. Therefore, by arranging the lower electrode (30) in a comb-like shape as a feature of the present application, the lower electrode (30) can be improved. Reduces extraction resistance and prevents deterioration of cable characteristics.

According to the structure of the present application, by forming the lower electrode region (26) of the MIS type capacitor using the isolation region (24), it is possible to deposit the dielectric thin film (28) before emitter diffusion. become.

Hereinafter, the manufacturing method of the present application will be explained using FIGS. 2A to 2F.

First, as shown in FIG. 2A, a P-type silicon semiconductor substrate (
The surface of the N+ type buried layer (22) is selectively doped with N type impurities such as antimony (Sb) or arsenic (As).
), and an N-type epitaxial layer (23) with a thickness of 5 to 10 μm is laminated on the entire surface of the substrate (21).

Next, as shown in FIG. 2B, by selectively diffusing boron (B) from the surface of the substrate (21), the buried layer (22
) to form P+ type isolation regions (24) penetrating the epitaxial layer (23) so as to surround the
The epitaxial layer (23) surrounded by 24) becomes an island (25) for forming each circuit element. At the same time, boron (B) from the separation region (24) diffusion process is also diffused into the region corresponding to the buried layer (22) on the surface of the island (25), and the buried layer (22) is diffused from the surface of the epitaxial layer (23).
A lower electrode region (26) is formed that reaches 22). The entire bottom of the lower electrode region (26) is formed so as to be in contact with the buried layer (22), and the lower electrode region (26) is formed so as to be in contact with the buried layer (22).
26) is electrically insulated from the ground potential of the substrate (21). Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration. The separation region (24) is diffused by saturated diffusion, but since it penetrates the epitaxial layer (23), the surface concentration of the lower electrode region (26) is 10'''atOI.
It will be around IIS-cITI-ffi.

Next, as shown in FIG. 2C, boron (B) is selectively ion-implanted or diffused into the surface of an island (25) different from the island (25) on which the lower electrode region (26) is formed. A base region (32) that will become the base of the transistor is formed. At this time, the lower electrode area (26)
If boron (B) is also diffused on the surface, the lower electrode region (2
6) The surface concentration can be improved.

Next, as shown in the second diagram, the thermal oxidation or CVD oxide film (27) formed on the surface of the epitaxial layer (23) is selectively etched away to expose a part of the surface of the lower electrode region (26), and Normal pressure CV on the entire layer (23)
Using a technique such as the D method, a silicon nitride film (sisNa) is deposited to a thickness of several hundred to several hundred. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dry etching technique such as RWE is used to form the exposed lower electrode region (
A dielectric thin film (28) is formed to cover the surface of (26). Thereafter, an oxide film (27) is deposited by CVD so as to cover the dielectric thin film (28).

Next, as shown in FIG. 2E, holes are opened in the oxide film (27) on the surface of the base region (32) and the surface of the island (25) of the NPN transistor, and using this oxide film (27) as a mask, ) by selectively diffusing the
form.

Next, as shown in FIG. 2F, a resist pattern of negative or positive photoresist is formed on the oxide film (27), and the oxide film (27) on the dielectric thin film (28) is removed by wet or dry etching. Remove the oxide film (
27) A contact hole (31) for electrical connection is opened in a desired portion. And epitaxial Jff
An aluminum layer is formed on the entire surface of l (23) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode (35) of a desired shape and an upper electrode (29) on the dielectric thin film (28). and the lower electrode (
30).

According to the manufacturing method of the present application, since the diffusion region formed by the diffusion process of the isolation region (24) is used as the lower electrode region (26) of the MIS type capacitor, the dielectric thin film (
The manufacturing step 28) can be placed before the emitter diffusion step. Then, there is no need to perform heat treatment for forming the MIS type capacitor from the phosphorus (P) deposit for forming the emitter region (33) to the phosphorus (P) drive-in, and the phosphorus (P) is initialized by the deposit. A heat treatment (drive-in) process for controlling the NPN transistor ('M current amplification factor) can be performed immediately from the diffused state. Therefore, there is little variation in h□ of NPN transistors, and hF by incorporating MIS type capacitance
It can solve the difficulty of I-control. Furthermore, the heat treatment conditions for the emitter region (33) can be unified regardless of whether MIS type capacitance is incorporated.
Process management by model becomes extremely easy.

The lower electrode region (26) of the present application takes various embodiments.
For example, one using upper and lower separation technology, one using only the upper diffusion region of upper and lower separation technology, - base region (32
) using a P+ type diffusion region for forming the anode of a Zener diode with a deeper impurity concentration, NP reaching from the surface of the epitaxial layer (23) to the buried layer (22)
These include those using an N-type collector low resistance region for the purpose of reducing collector resistance of an N transistor. Since both are performed before emitter diffusion, the surface concentration thereof will be lower than that of the emitter region (33).

(g) As described in detail, according to the present invention, by adding MISJI as an optional device, there is little variation in hFF of NPN transistors, and the hF of NPN transistors can be extremely easily controlled. It has the advantage of providing a method for manufacturing integrated circuits. Also, M
Processing conditions for the emitter area (33) can be unified for models with IS-type capacitance and models without, simplifying process management for each model, and even allowing wafers of different models to be placed in the same diffusion furnace. It also has the advantage of being able to produce a wide variety of products in small quantities by heat treatment.

According to the present application, the extraction resistance of the lower electrode (30) is reduced by forming the lower electrode (30) into a comb-like shape, so the lower electrode region (26) has a lower surface concentration than the emitter region (33). It also has the advantage that deterioration of the characteristics of the MIS type capacitor can be prevented even though the area is used.

[Brief explanation of the drawing]

1A and 1B are a plan view and a sectional view taken along line AA, respectively, for explaining the present invention, and FIGS. 2A to 2F are sectional views, respectively, for explaining the manufacturing method of the present invention, FIG. 3 is a sectional view for explaining a conventional example. (21) is the semiconductor substrate, (26) is the lower electrode region,
28〉 is a dielectric thin film, (29) is an upper electrode, (30
) is the bottom electrode.

Claims (2)

[Claims] (1) An epitaxial layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of the opposite conductivity type formed on the surface of the substrate, and the epitaxial layers are separated so as to surround each of the buried layers. an isolation region of one conductivity type, a plurality of islands formed by the isolation region, and a lower electrode of an MIS type capacitor of one conductivity type or an opposite conductivity type formed on the surface of this island prior to emitter diffusion of a vertical bipolar transistor. a dielectric thin film deposited prior to the emitter diffusion to cover the lower electrode region, a lower electrode of an MIS type capacitor in ohmic contact with the surface of the dielectric thin film, and a dielectric thin film deposited to cover the lower electrode region; A semiconductor integrated circuit comprising an upper electrode disposed on the dielectric thin film so as to sandwich and face the lower electrode region, and the lower electrode is disposed in a comb-like shape. (2) a step of forming a buried layer of an opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type; a step of forming an epitaxial layer of an opposite conductivity type on the substrate; and a step of separating the epitaxial layer into a plurality of layers. a step of forming a lower electrode region of one conductivity type or an opposite conductivity type to serve as a lower electrode of a MIS type capacitor on the surface of one island; exposing a part of the surface of the lower electrode region; Said MI
A step of depositing a dielectric thin film of S-type capacitance to form a comb-teeth shape, after forming the dielectric thin film, selectively diffusing impurities of the opposite conductivity type to form the reverse conductivity type of the vertical bipolar transistor. Step of forming an emitter region: forming a conductive film on the entire surface, and forming the M on the dielectric thin film.
A method for manufacturing a semiconductor integrated circuit, comprising the step of disposing an upper electrode of an IS type capacitor in a comb-teeth shape on the surface of the lower electrode region in ohmic contact with the lower electrode region.