JP2707646B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a bipolar semiconductor device provided with a capacitor.

[Conventional technology]

As a conventional technique, as shown in FIG. 3, an N-type epitaxial layer 3 formed on a P-type silicon
N-type diffusion layer 10 for leading out the collector of N-transistor
After forming an N-type diffusion layer 22 at the same time as forming the oxide film 11, an oxide film 11 is formed on the N-type diffusion layer 22 to a thickness of 30 nm, and a silicon nitride film 13 is formed on the oxide film 11 to a thickness of 100 nm. The oxide film 11 and the silicon nitride film 13 are used as a dielectric film, and an N-type diffusion layer is formed.
A capacitor was formed by using the electrode 22 with the aluminum layer 22.

[Problems to be solved by the invention]

In the conventional capacitor described above, one electrode is formed of an N-type diffusion layer, and the N-type diffusion layer and the N-type epitaxial layer are electrically continuous. There is a disadvantage that the junction capacitance that can be formed with the isolated P-type diffusion layer 5 is provided as a parasitic capacitance.

[Means for solving the problem]

The manufacturing apparatus of the main body device of the present invention includes a step of forming a second conductivity type impurity layer in the first conductivity type epitaxial layer;
Forming an insulating film on the first conductive type epitaxial layer and on the second conductive type impurity layer, and etching the insulating film to form on the second conductive type impurity layer and the first conductive type epitaxial layer Forming a through hole in the
Depositing a polycrystalline silicon layer on the insulating film, forming an insulating film on the polycrystalline silicon layer, and introducing a first conductivity type impurity into the polycrystalline silicon layer by ion implantation; Performing annealing to form a first conductivity type impurity in the second conductivity type impurity layer and the first conductivity type epitaxial layer and to make the polycrystalline silicon layer a second conductivity type; Etching the insulating film on the layer while leaving a portion serving as a dielectric film of the capacitor; and etching the polycrystalline silicon layer together with the polycrystalline silicon layer on the first conductivity type impurity layer. Forming a first electrode for a capacitor while leaving an insulating film, which is a film, and a polycrystalline silicon layer of a lead portion; and forming a metal wiring on the polycrystalline silicon layer and The capacitor on the crystal silicon layer 2
Forming an electrode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, after an N-type buried layer 2 is formed on a P-type silicon substrate 1, an N-type epitaxial layer 3 is grown. An oxide film 4 having a thickness of 400 nm is formed on the N-type epitaxial layer 3 by, for example, steaming at 1000 ° C. for 65 minutes, and the oxide film 4 at a desired position is removed by photolithography. For this purpose, a P-type impurity, for example, boron is applied at 1060 ° C. using the oxide film 4 as a mask.
Diffusion is performed for 20 minutes, and a press is performed to form a P-type diffusion layer 5.

Next, as shown in FIG. 1 (b), after removing the oxide film 4, a thin oxide film 6 is grown to a thickness of 30 nm on the entire surface, and a silicon nitride film 7 of 150 nm is formed on the oxide film 6. It is formed to a thickness. After removing the silicon nitride film 7 at a desired location by photolithography, pressure oxidation is performed at 950 ° C. and 5 atm for 100 minutes,
A field oxide film 9 is grown on the silicon surface to a thickness of 1 μm. At this time, a thin oxide film 8 is formed on the silicon nitride film 7.

Next, as shown in FIG. 1 (c), after a desired portion of the thin oxide film 8, silicon nitride film 7, and oxide film 6 is removed by photolithography, the oxide film 8 and the silicon nitride film 7 are subjected to field oxidation. Using the film 9 as a mask, an N-type impurity such as phosphorus is
The N-type impurity layer 10 is formed by diffusion for 0 minutes.

Next, as shown in FIG. 1 (d), after removing the oxide film 8, the silicon nitride film 7, and the oxide film 6, a thin oxide film having a thickness of 70 nm is formed on the N-type epitaxial layer 3 and the N-type impurity layer. The film 11 is formed. Next, P is applied to a desired portion using a photoresist as a mask.
After ion implantation of boron as a type impurity at an acceleration energy of E = 30 keV and a dose of Φ = 7.5 × 10 ¹³ cm ⁻² , the photoresist is removed, and annealing is performed in N ₂ at 900 ° C. for 30 minutes to perform base of the NPN transistor A region 12 is formed.

Next, as shown in FIG. 1E, after a silicon nitride film 13 is formed on the entire surface, the N ⁺ -type impurity layer 10 is formed by photolithography.
The silicon nitride film 13 at a desired position on the upper portion and the P-type base region 12 is removed, and the exposed oxide film 11 is removed.

Next, as shown in FIG.
14 is formed to a thickness of 150 nm, and then oxidized in dry O ₂ at 900 ° C. for 30 minutes to form a thin oxide film 15. N-type impurities on the entire surface,
For example, arsenic is accelerated with an energy E = 70 keV and a dose Φ =
Ion implantation is performed at 1 × 10 ¹⁶ cm ⁻² . Annealing is performed in N ₂ at 950 ° C. for 60 minutes to form an emitter region 16 of the NPN transistor in the P-type base region 12. At the same time, the N-type impurity layer 10
An N ⁺ -type impurity layer 16a is formed therein. Next, after a silicon nitride film 17 is formed on the oxide film 15 to a thickness of 30 nm, the silicon nitride 17 is removed by photolithography, leaving only the portion on the oxide film 9 where a capacitor is to be formed, and the others are removed.

Next, as shown in FIG. 1 (g), the N-type emitter region 16, the N-type emitter region 16, the polycrystalline silicon layer 14 on the N-impurity layer 16a, and the multi-portion of the portion forming the capacitor electrode are formed by photolithography. The other polycrystalline silicon layer 14 is removed except for the crystalline silicon layer 14. After that, the oxide film 11 is removed simultaneously with the oxide film 15 on the remaining polycrystalline silicon layer 14 with hydrofluoric acid or the like.

Next, as shown in FIG. 1 (h), after aluminum is formed on the entire surface, the aluminum is etched by photolithography to form the electrode 18 of the transistor and the electrode 19 of the capacitor and the polysilicon layer of the capacitor. 14
Are simultaneously formed.

2 (a) to 2 (c) are sectional views shown in the order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2 (a), the same steps as in FIG. 1 (e) of the first embodiment are formed in the same manner.
14 is deposited, a thin oxide film 15 is formed thereon, and the other portions are removed by photolithography except for the portion where the dielectric film of the capacitor is to be formed.

Next, as shown in FIG. 2B, the polysilicon layer 14 is etched using the photoresist 21 as a mask,
After leaving the electrode portions of the emitter and collector of the transistor and the electrode portion of the capacitor, the oxide film 11 is etched with hydrofluoric acid or the like.

Next, as shown in FIG. 2 (c), after removing the photoresist, electrodes 18, 19 and 20 are formed of aluminum.

In this embodiment, the dielectric film of the capacitor is a thin oxide film.
Since it is only 15, there is an advantage that the capacity per unit area can be increased.

〔The invention's effect〕

As described above, according to the present invention, the polysilicon layer used for forming the emitter is used as one electrode of the capacitor, and the oxide film on the polysilicon layer is used as the dielectric film of the capacitor. There is an effect that a capacitor having no capacity can be formed.

[Brief description of the drawings]

1 (a) to 1 (h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are second views of the present invention. FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device shown in the order of steps for explaining the embodiment. 1 ... P-type silicon substrate, 2 ... N-type buried layer, 3 ... N
Type epitaxial layer, 4 oxide film, 5 P-type diffusion layer, 6 oxide film, 7 silicon nitride film, 8 oxide film, 9 field oxide film, 10 N-type impurity Layer, 11
... oxide film, 12 ... P-type base region, 13 ... silicon nitride film, 14 ... polycrystalline silicon layer, 15 ... oxide film, 16 ... N
Mold emitter area, 17 silicon nitride, 18, 19, 20 electrodes.

Claims (1)

(57) [Claims] A step of forming a second conductive type impurity layer in the first conductive type epitaxial layer; and a step of forming an insulating film on the first conductive type epitaxial layer and on the second conductive type impurity layer. Forming a through-hole on the second conductivity type impurity layer and the first conductivity type epitaxial layer by etching the insulating film; depositing a polycrystalline silicon layer on the insulating film; Forming an insulating film on the polycrystalline silicon layer, introducing a first conductive type impurity into the polycrystalline silicon layer by ion implantation, performing annealing in the second conductive type impurity layer and the first conductive type impurity layer; Forming a first conductivity type impurity in the first type epitaxial layer and setting the polycrystalline silicon layer to the second conductivity type; and forming a portion of the insulating film on the polycrystalline silicon layer to be a dielectric film of the capacitor. And etching the polycrystalline silicon layer to leave an insulating film which is a dielectric film of the capacitor and a polycrystalline silicon layer of a lead portion together with the polycrystalline silicon layer on the first conductivity type impurity layer. Forming a first electrode for a capacitor, and forming a metal wiring on the polycrystalline silicon layer and forming a second electrode for a capacitor on the polycrystalline silicon layer. A method for manufacturing a semiconductor device.