JPS63140561A - Manufature of semiconductor integrated circuit - Google Patents
Manufature of semiconductor integrated circuitInfo
- Publication number
- JPS63140561A JPS63140561A JP28815386A JP28815386A JPS63140561A JP S63140561 A JPS63140561 A JP S63140561A JP 28815386 A JP28815386 A JP 28815386A JP 28815386 A JP28815386 A JP 28815386A JP S63140561 A JPS63140561 A JP S63140561A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- impurity layer
- oxide film
- type
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000012535 impurity Substances 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路の製造方法に関し、特にツェ
ナーダイオードを備えた半導体集積回路の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a semiconductor integrated circuit including a Zener diode.
従来、この程の半導体集積回路におけるツェナーダイオ
ードは第２図に示すように、Ｐ型不純物層であるＰウェ
ル５ｂを絶縁拡散領域であるＰ型拡散領域５ａと同時に
形成し、Ｎ型不純物層９ｃをＰＮＰトランジ、スタのベ
ースコンタクト領域９ａと同時に形成していた。Conventionally, as shown in FIG. 2, in the Zener diode in such a semiconductor integrated circuit, a P well 5b, which is a P type impurity layer, is formed simultaneously with a P type diffusion region 5a, which is an insulating diffusion region, and an N type impurity layer 9c. was formed at the same time as the base contact region 9a of the PNP transistor and star.
上述した従来の半導体集積回路のツェナーダイオードは
Ｐ型不純物層を絶縁拡散と同時忙形成し、Ｎ型不純物層
については、ＰＮＰトランジスタのベースコンタクト領
域と同時釦拡散によシ形成しているので、表面での濃度
が高く表面でブレークダウンが起こシ表面濃度によって
耐圧が決まってしまい、また表面から酸化ケイ素膜ある
いは窒化ケイ素膜へのホットエレクトロンの注入が大き
くツェナー耐圧がドリフトするという欠点がある。In the Zener diode of the conventional semiconductor integrated circuit described above, the P-type impurity layer is formed simultaneously with insulating diffusion, and the N-type impurity layer is formed simultaneously with the base contact region of the PNP transistor by button diffusion. The breakdown voltage is determined by the surface concentration due to the high concentration at the surface, and the breakdown voltage is determined by the surface concentration.Also, there is a drawback that the injection of hot electrons from the surface into the silicon oxide film or silicon nitride film is large, causing the Zener breakdown voltage to drift.
本発明の半導体集積回路の製造方法は、第１導電型半導
体層の表面から第２導電型不純物を導入してなる第２導
電型ウェルと前記第１導電型半導体層に設けられた第２
導電型コレクタ領域で側面及び底面を囲まれた第１導電
型ウェルに同時に第１導電型不純物を導入して、前記ｍ
ｌｌ導電ツウオル少なくとも選択的に設けられた前記第
２導電型コレクタ領域に達する第１導電型ベース領域及
び前記第２導電型ウェルに選択的に設けられた第１の第
１導電型不純物層を形成する工程と、前記第１導電型ベ
ース領域にベースコンタクト領域及び前記第１の第１導
電型不純物層の表面から前記第２導電型ウェルに達する
第２の第１導電型不純物層を設ける工程とにより、縦型
バイポーラトランジスタと前記第１．第２の不純物層及
び第２導電型ウェルからなる定電圧ダイオードを形成す
るというものである。A method for manufacturing a semiconductor integrated circuit according to the present invention includes a second conductivity type well formed by introducing a second conductivity type impurity from the surface of the first conductivity type semiconductor layer, and a second conductivity type well provided in the first conductivity type semiconductor layer.
A first conductivity type impurity is simultaneously introduced into a first conductivity type well whose side and bottom surfaces are surrounded by a conductivity type collector region, and the m
forming a first conductivity type impurity layer selectively provided in the first conductivity type base region and the second conductivity type well reaching at least the selectively provided second conductivity type collector region; and providing a base contact region in the first conductivity type base region and a second first conductivity type impurity layer reaching from the surface of the first first conductivity type impurity layer to the second conductivity type well. Accordingly, the vertical bipolar transistor and the first. A constant voltage diode including a second impurity layer and a second conductivity type well is formed.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ型半導体（ケイ素
）基板１にＮ型埋込層２、Ｐ型埋込層３を埋込んでＮ型
エピタキシャル層４を成長し九ウェーハにＰ型絶縁拡散
を行ない、絶縁分離のためのＰ型拡散領域５ａと同時に
ツェナーダイオード部のＰ型不純物層となるＰ型ウェル
５ｂを形成し、表面に酸化ケイ素膜６を形成する。First, as shown in FIG. 1(a), an N-type buried layer 2 and a P-type buried layer 3 are buried in a P-type semiconductor (silicon) substrate 1, and an N-type epitaxial layer 4 is grown. P-type insulation diffusion is performed to form a P-type diffusion region 5a for insulation isolation and a P-type well 5b which becomes a P-type impurity layer of a Zener diode portion at the same time, and a silicon oxide film 6 is formed on the surface.
次に、第１図（ｂ）に示すように、ホトレジスト膜をマ
スクにして酸化ケイ素膜６を選択的に除去し、ホトレジ
スト膜を除去した後に、Ｎ型のたとえばリンをイオン注
入で、縦型ＰＮＰ ）ランジスタのベース部となるＮ型
ベース領域７ａとツェナーダイオード部のＮ型不純物層
として第１のＮ型不純物層７ｂを同時に形成する。この
際、第１のＮ型不純物層７ｂはツェナーダイオード部の
Ｐ型不純物層となるＰ型ウェル５ｂの表面濃度を下げる
かＮ型に反転させるようにする。Next, as shown in FIG. 1(b), the silicon oxide film 6 is selectively removed using the photoresist film as a mask, and after removing the photoresist film, N-type, for example, phosphorus is ion-implanted to form a vertical structure. (PNP) An N-type base region 7a serving as the base portion of the transistor and a first N-type impurity layer 7b serving as the N-type impurity layer of the Zener diode portion are formed at the same time. At this time, the first N-type impurity layer 7b is designed to reduce the surface concentration of the P-type well 5b, which becomes the P-type impurity layer in the Zener diode portion, or to be inverted to N-type.
次忙、第１図（Ｃ）に示すように、Ｎ型ベース領域７ａ
、第１のＮ型不純物層７ｂ上に酸化ケイ素膜を形成し縦
型ＰＮＰ ）ランジスタのエミッタ部ヲ形成する部分の
酸化ケイ素膜６を取り除き、Ｐ型不純物たとえばポロン
を拡散又はイオン注入してＰ型不純物Ｍ８を形成し、そ
の上に酸化ケイ素膜を形成する。Next, as shown in FIG. 1(C), the N-type base region 7a
, a silicon oxide film is formed on the first N-type impurity layer 7b to form a vertical PNP).The silicon oxide film 6 is removed from the portion where the emitter part of the transistor is to be formed, and a P-type impurity such as poron is diffused or ion-implanted to form a vertical PNP. A type impurity M8 is formed, and a silicon oxide film is formed thereon.
この後、ツェナーダイオード部のＮ型不純物層ならびに
縦型ＰＮＰトランジスタのベースコンタクト部を形成す
るために酸化膜を選択的に除去し、Ｎ型のたとえばリン
を拡散し、第２のＮ型不純物層９ｂ及びベースコンタク
ト領域９ａを形成する。After this, the oxide film is selectively removed to form an N-type impurity layer in the Zener diode part and a base contact part of the vertical PNP transistor, and N-type, for example, phosphorus is diffused, and a second N-type impurity layer is formed. 9b and a base contact region 9a are formed.
この際、ツェナーダイオード部の不純物層は先に形成し
たＮ型不純物層の内側【入るよう拡散する。At this time, the impurity layer in the Zener diode portion is diffused into the previously formed N-type impurity layer.
最後に、第１図（ｄ）Ｋ示すように、この後、ウェーハ
を酸化して酸化ケイ素膜を形成し、電極引出し部の酸化
ケイ素膜を除去し、電極１０を形成する。Finally, as shown in FIG. 1(d)K, the wafer is then oxidized to form a silicon oxide film, and the silicon oxide film on the electrode extension portion is removed to form the electrode 10.
このようにして、ツェナーダイオードとＰＮＰトランジ
スタとを含む半導体集積回路が形成される。In this way, a semiconductor integrated circuit including a Zener diode and a PNP transistor is formed.
以上説明したように本発明は、第２導電型ウェルに低濃
度の第１の第１導電型不純物層を形成し、その内側に第
２の第１導電型不純物層を形成し、ツェナーダイオード
の接合付近の表面濃度を低下させることにより、表面で
のブレークダウンを抑え内部でブレークダウンを起こさ
せるので、ホットエレクトロンの酸化膜あるいは窒化ケ
イ素メ膜への注入を抑えることができ、動作の安定な半
導体集積回路を製造できる効果がある。As explained above, the present invention forms a low concentration first impurity layer of the first conductivity type in the second conductivity type well, forms a second impurity layer of the first conductivity type inside the first impurity layer, and forms a Zener diode. By lowering the surface concentration near the junction, breakdown at the surface is suppressed and breakdown occurs internally, which suppresses the injection of hot electrons into the oxide film or silicon nitride film, resulting in stable operation. This has the effect of making it possible to manufacture semiconductor integrated circuits.
チップの断面図、第２図は従来例を説明するための半導
体チップの断面図である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型埋
込層、３・・・・・・Ｐ型埋込層、４・・・・・・Ｎ型
エピタキシャル層、５ａ・・・・・・Ｐ型拡散領域、５
ｂ・・・・・・Ｐ型ウェル、６・・・・・・酸化ケイ素
膜、７ａ・・・・・・Ｎ型ベース領域、７ｂ・・・・・
・第１のＮ型不純物層、８・・・・・・Ｐ型不純物層、
９ａ・・・・・・ベースコンタクト領域、９ｂ・・・・
・・第２のＮ型不純物層、９Ｃ・・・・・・Ｎ型不純物
層、１０・・・・・・電極、１１・・・・・・Ｎ型ウェ
ル、１２・・・・・・窒化ケイ素膜。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional example. 1... P-type semiconductor substrate, 2... N-type buried layer, 3... P-type buried layer, 4... N-type epitaxial layer, 5a...P-type diffusion region, 5
b...P-type well, 6...Silicon oxide film, 7a...N-type base region, 7b...
・First N-type impurity layer, 8... P-type impurity layer,
9a...Base contact area, 9b...
...Second N-type impurity layer, 9C...N-type impurity layer, 10...Electrode, 11...N-type well, 12...Nitriding silicon membrane.
Claims (1)
してなる第２導電型ウェルと前記第１導電型半導体層に
設けられた第２導電型コレクタ領域で側面及び底面を囲
まれた第１導電型ウェルに同時に第１導電型不純物を導
入して、前記第１導電型ウェルに少なくとも選択的に設
けられた前記第２導電型コレクタ領域に達する第１導電
型ベース領域及び前記第２導電型ウェルに選択的に設け
られた第１の第１導電型不純物層を形成する工程と、前
記第１導電型ベース領域にベースコンタクト領域及び前
記第１の第１導電型不純物層の表面から前記第２導電型
ウェルに達する第２の第１導電型不純物層を設ける工程
とにより、縦型バイポーラトランジスタと前記第１、第
２の不純物層及び第２導電型ウェルからなる定電圧ダイ
オードを形成することを特徴とする半導体集積回路の製
造方法。A second conductivity type well formed by introducing a second conductivity type impurity from the surface of the first conductivity type semiconductor layer and a second conductivity type collector region provided in the first conductivity type semiconductor layer surround the side and bottom surfaces. A first conductivity type impurity is introduced into the first conductivity type well at the same time, and the first conductivity type base region and the second conductivity type impurity reach the second conductivity type collector region provided at least selectively in the first conductivity type well. forming a first impurity layer of the first conductivity type selectively provided in the conductivity type well; A step of providing a second first conductivity type impurity layer reaching the second conductivity type well forms a constant voltage diode including a vertical bipolar transistor, the first and second impurity layers, and the second conductivity type well. A method for manufacturing a semiconductor integrated circuit, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28815386A JPS63140561A (en) | 1986-12-02 | 1986-12-02 | Manufature of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28815386A JPS63140561A (en) | 1986-12-02 | 1986-12-02 | Manufature of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63140561A true JPS63140561A (en) | 1988-06-13 |
| JPH0582985B2 JPH0582985B2 (en) | 1993-11-24 |
Family
ID=17726489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28815386A Granted JPS63140561A (en) | 1986-12-02 | 1986-12-02 | Manufature of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140561A (en) |
-
1986
- 1986-12-02 JP JP28815386A patent/JPS63140561A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0582985B2 (en) | 1993-11-24 |
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