JPS63173357A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63173357A JPS63173357A JP667587A JP667587A JPS63173357A JP S63173357 A JPS63173357 A JP S63173357A JP 667587 A JP667587 A JP 667587A JP 667587 A JP667587 A JP 667587A JP S63173357 A JPS63173357 A JP S63173357A
- Authority
- JP
- Japan
- Prior art keywords
- buried layer
- oxide film
- type
- layer
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 12
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
r産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体基板
上に埋込層を形成する工程を含む半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION r Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of forming a buried layer on a semiconductor substrate.
バイポーラICでは、コレクタ直列抵抗を下げるため、
埋込層が設けられる。In bipolar ICs, in order to lower the collector series resistance,
A buried layer is provided.
第3図(a)〜(c)は従来の半導体装置の製造方法を
説明するための工程順に示した半導体チップの断面図で
ある。FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.
第3図(a>に示すように、P型のシリコン基板1の表
面に選択的に形成した酸化硅素膜1oをマスクとしてシ
リコン基板1の表面にN型の高濃度不純物を導入し、埋
込層4を形成する。As shown in FIG. 3 (a), N-type high-concentration impurities are introduced into the surface of the silicon substrate 1 using the silicon oxide film 1o selectively formed on the surface of the P-type silicon substrate 1 as a mask. Form layer 4.
次に、第3図(b)4こ示すように、酸化硅素膜10を
除去し、P型シリコン基板1の表面にN型の低濃度不純
物を含むエピタキシャル層5を形成する。Next, as shown in FIG. 3(b), the silicon oxide film 10 is removed, and an epitaxial layer 5 containing low concentration N-type impurities is formed on the surface of the P-type silicon substrate 1.
次に、第3図(c)に示すように、エピタキシャル層5
の表面にP型の高濃度不純物を選択的に導入してシリコ
ン基板1に達する分離領域6を形成し、シリコン基板]
および分離領域6で囲まれたエピタキシャル層5の表面
にP型ベース領域7、N型エミッタ領域8、N型コレク
タ・コンタクト領域9を形成して縦型NPN トランジ
スタを形成する。Next, as shown in FIG. 3(c), an epitaxial layer 5 is formed.
A high-concentration P-type impurity is selectively introduced into the surface of the silicon substrate to form an isolation region 6 that reaches the silicon substrate 1.
A P type base region 7, an N type emitter region 8, and an N type collector/contact region 9 are formed on the surface of the epitaxial layer 5 surrounded by the isolation region 6 to form a vertical NPN transistor.
上述した従来の半導体装置の製造方法は、シリコン基板
1と埋込層3の接する面がPN接合であるため、例えば
、第3図に示すNPN)ランジスタの場合、コレクタと
接地電位のシリコン基板1との間の接合容量が大きく、
トランジスタの高周波特性、特に信号の立ち上り特性を
悪化させるという問題点がある。In the conventional semiconductor device manufacturing method described above, since the contact surface between the silicon substrate 1 and the buried layer 3 is a PN junction, for example, in the case of an NPN transistor shown in FIG. The junction capacitance between
There is a problem in that the high frequency characteristics of the transistor, especially the signal rise characteristics, are deteriorated.
本発明の目的は、コレクタの寄生容量が少なく高周波特
性のすぐれた半導体装置の製造方法を提供することにあ
る。An object of the present invention is to provide a method for manufacturing a semiconductor device with less parasitic capacitance in the collector and excellent high frequency characteristics.
本発明の半導体製造方法は、−導電型の半導体基板を中
央に埋込層相当の厚さに残して全面に酸化膜を形成する
工程と、前記表面の酸化膜を選択エツチングして開孔部
を設け前記酸化膜をマスクとして前記半導体基板中に逆
導電型の不純物を導入して裏面の酸化膜に達する埋込層
を形成する工程と、前記表面の酸化膜を除去して前記半
導体基板表面に逆導電型のエピタキシャル層を形成する
工程とを含んで構成される。The semiconductor manufacturing method of the present invention includes a step of forming an oxide film on the entire surface of a conductive type semiconductor substrate with a thickness equivalent to a buried layer left in the center, and selectively etching the oxide film on the surface to form an opening. forming a buried layer that reaches the oxide film on the back surface by introducing impurities of opposite conductivity type into the semiconductor substrate using the oxide film as a mask; and forming an epitaxial layer of opposite conductivity type.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
第1図(a)に示ずように、P型のシリコン基板1を約
1000℃の高温スチームにより酸化し、非酸化部分が
埋込層に相当する厚さ5〜10μmになるよう酸化時間
を設定して酸化硅素膜2゜3を形成する。As shown in FIG. 1(a), a P-type silicon substrate 1 is oxidized with high-temperature steam at about 1000°C, and the oxidation time is increased so that the non-oxidized part becomes 5 to 10 μm thick, which corresponds to the buried layer. Then, a silicon oxide film 2.3 is formed.
次に、第1図(b)に示すように、酸化硅素膜2をリソ
グラフィ技術を用いてパターニングし形成された開孔部
を通してシリコン基板1の表面に高濃度N型不純物を導
入し、酸化硅素膜3に達する埋込層4を形成した後、酸
化硅素膜2を除去する。Next, as shown in FIG. 1(b), high concentration N-type impurities are introduced into the surface of the silicon substrate 1 through the openings formed by patterning the silicon oxide film 2 using lithography technology. After forming the buried layer 4 that reaches the film 3, the silicon oxide film 2 is removed.
次に、第1図(c)に示すように、低濃度N型のエピタ
キシャル層5を成長する。このとき埋込層4の高濃度N
型不純物がエピタキシャル層5中にも拡散し、埋込層4
の厚さが増加する。Next, as shown in FIG. 1(c), a lightly doped N-type epitaxial layer 5 is grown. At this time, the buried layer 4 has a high concentration of N
The type impurity also diffuses into the epitaxial layer 5, and the buried layer 4
The thickness increases.
次に、第1図(d)に示すように、エピタキシャル層5
の表面にP型の高濃度不純物を選択的に導入してシリコ
ン基板1に達する分離領域を形成し、シリコン基板1お
よび分離領域6で囲まれたエピタキシャル層5の表面に
P型ベース領域7、N型エミッタ領域8、N型コレクタ
・コンタクト領域9を形成して縦型NPN?−ランジス
タを形成する。Next, as shown in FIG. 1(d), an epitaxial layer 5 is formed.
A P-type high concentration impurity is selectively introduced into the surface of the epitaxial layer 5 to form an isolation region reaching the silicon substrate 1, and a P-type base region 7, An N-type emitter region 8 and an N-type collector contact region 9 are formed to form a vertical NPN? - form a transistor;
このように、埋込層4の底面に接する酸化硅素膜3をシ
リコン基板1の裏面に形成することで、シリコン基板1
と埋込層4との接合容量は大幅に減少させることができ
、従来の1/2以下とすることができる。In this way, by forming the silicon oxide film 3 in contact with the bottom surface of the buried layer 4 on the back surface of the silicon substrate 1, the silicon substrate 1
The junction capacitance between the capacitor and the buried layer 4 can be significantly reduced, and can be reduced to 1/2 or less of the conventional value.
第2図(a>、(b)は本発明の第2の実施例を説明す
るための工程順に示した半導体チップの=5−
断面図である。FIGS. 2A and 2B are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.
第2図(a)に示すように、第1の実施例で形成した埋
込層4の内側に埋込層4の不純物よりも拡散係数の大き
な高濃度P型の埋込層10を形成した後N型のエピタキ
シャル層5を形成する。As shown in FIG. 2(a), a highly doped P-type buried layer 10 having a larger diffusion coefficient than the impurity of the buried layer 4 was formed inside the buried layer 4 formed in the first embodiment. After that, an N-type epitaxial layer 5 is formed.
次に、第2図(b)に示すように、エピタキシャル層の
表面に埋込層10に達するP型コレクタ領域]1を形成
し、埋込層10とコレクタ領域11で囲まれたエピタキ
シャル層5の表面にN型ベース領域12、P型エミッタ
領域13を形成してフローティング状態の縦型PNP)
ランジスタを形成する。Next, as shown in FIG. 2(b), a P-type collector region 1 reaching the buried layer 10 is formed on the surface of the epitaxial layer, and an epitaxial layer 5 surrounded by the buried layer 10 and the collector region 11 is formed. An N-type base region 12 and a P-type emitter region 13 are formed on the surface of the vertical PNP in a floating state).
form a transistor.
以上説明したように、本発明は、半導体基板裏面に、埋
込層と接する酸化物層を形成することにより、埋込層と
基板間の接合容量を低減でき、トランジスタの高周波特
性を改善できる効果がある。As explained above, the present invention has the effect of reducing the junction capacitance between the buried layer and the substrate and improving the high frequency characteristics of the transistor by forming an oxide layer in contact with the buried layer on the back surface of the semiconductor substrate. There is.
第1図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図、第2図
(a)、(b)は本発明の第2の実施例を説明するため
の工程順に示した半導体チップの断面図、第3図(a)
〜(C)は従来の半導体装置の製造方法を説明するため
の工程順に示した半導体チップの断面図である。
1・・・シリコン基板、2,3・・・酸化硅素膜、4・
・・埋込層、5・・・エピタキシャル層、6・・・分離
領域、7・・ベース領域、8・・・エミッタ領域、9・
・・コレクタ・コンタクト領域、10・・・埋込層、1
1・・コレクタ領域、12・・ベース領域、13・・・
エミッタ領域。
一7=
とbつ
眞)
第1図
αり
暴3図FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. FIG. 3(a) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
-(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon substrate, 2, 3... Silicon oxide film, 4.
...Buried layer, 5.Epitaxial layer, 6.Isolation region, 7.Base region, 8.Emitter region, 9.
...Collector contact region, 10...Buried layer, 1
1...Collector area, 12...Base area, 13...
emitter area. 17 = Tob Tsushin) Figure 1 α Ribo Figure 3
Claims (1)
て全面に酸化膜を形成する工程と、前記表面の酸化膜を
選択エッチングして開孔部を設け前記酸化膜をマスクと
して前記半導体基板中に逆導電型の不純物を導入して裏
面の酸化膜に達する埋込層を形成する工程と、前記表面
の酸化膜を除去して前記半導体基板表面に逆導電型のエ
ピタキシャル層を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。A process of forming an oxide film on the entire surface of a semiconductor substrate of one conductivity type, leaving a thickness equivalent to a buried layer in the center, and selectively etching the oxide film on the surface to form an opening, using the oxide film as a mask. Introducing impurities of opposite conductivity type into the semiconductor substrate to form a buried layer reaching the oxide film on the back surface, and removing the oxide film on the front surface to form an epitaxial layer of opposite conductivity type on the surface of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667587A JPS63173357A (en) | 1987-01-13 | 1987-01-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667587A JPS63173357A (en) | 1987-01-13 | 1987-01-13 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63173357A true JPS63173357A (en) | 1988-07-16 |
Family
ID=11644943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP667587A Pending JPS63173357A (en) | 1987-01-13 | 1987-01-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63173357A (en) |
-
1987
- 1987-01-13 JP JP667587A patent/JPS63173357A/en active Pending
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