JPS5898956A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an integrated junction logic element of extremely small area in self-aligning manner by oxidizing a polycrystalline semiconductor layer in high pressure and low temperature oxidative atmosphere and forming an oxidized film having a thickness larger than the oxidized film formed on the other part thereon. CONSTITUTION:An oxidized film 6 which has a thickness more than five times the low density single crystal silicon substrate and is chemically good in quality is formed by oxidizing in high pressure and low temperature oxidative atmosphere on arsenic-or phosphorus-added polysilicon layers 5, 5'. An oxidized film 7 is formed on the single crystal substrate. The film 7 on the substrate is all etched, thereby allowing an oxidized film 6' to remain on the layers 5, 5'. A boron-added polysilicon layer 12 is grown on the overall surface. Further, an aluminum layer 12 is deposited thereon.

Description

[Detailed Description of the Invention] Alpha speaking language 1 and Katazo old--2 Pi. (, 48 children, hereinafter referred to as IL).

I”L is a horizontal PNP transistor as a charge injection element and a vertical reverse NPN transistor as a carrier amplification element.
The transistors are integrated, and the collector of the PNP) transistor and the space of the NPN) transistor are formed in common, making it excellent as a logic element that can be formed on the same substrate as a linear circuit.

However, in order to increase the speed of I"L, it is essential to reduce the size of the sensor, and various methods have been proposed for this reduction. Examples of these are shown in Fig. 1. This is a method of forming the collector region of an NPN transistor using a polysilicon layer containing impurities.
As shown in FIG. 1 (4), an isolation oxide film 2 is selectively formed on the Nm layer 1, an injector region 4' and a base region 4 are formed using the filled oxide film 3 as a mask, and impurities are added to form a collector region. A polysilicon layer 5 containing the silicon nitride is formed, and the polysilicon layer 5 is formed into a predetermined pattern shape using an oxide film 6 and a nitride Jl 17.

In this way, the nitride film 7 and the oxide a6 are required to etch the polysilicon layer 5 into a predetermined shape. Further, a nitride film 8 is required in order to avoid forming an oxide film on the field when selectively oxidizing the polysilicon layer 5ft.

However, when oxidized in this way, as shown in FIG. 1 (5), the oxide film thickness 9' near the interface between the polysilicon l15 and the single crystal silicon layer 4 becomes thinner, and when the AI electrode 11 is formed, There is a drawback that the collector region lO of fL and the base region 4 may be short-circuited, and the withstand voltage is lowered.

Furthermore, an alignment margin for selectively etching the nitride film 8 is required (FIG. 1(i)), which impedes miniaturization of the device. Note that 9 is an oxide film on the surface of the polysilicon layer 5.

The object of the present invention is to solve the drawbacks of the conventional method and to provide a method and structure for manufacturing an I'L that is simple and does not require an alignment margin.

The present invention takes advantage of the fact that an oxide film several times thicker than that on a single crystal semiconductor layer is formed on a polycrystalline semiconductor layer containing impurities when fermentation treatment is performed at high pressure and low temperature. The manufacturing method of the present invention will be explained in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the manufacturing method of the present invention.

First, as shown in Figure W&2 (1), using the selective oxide film 2 formed on the n-type substrate 1 and the field oxide film 3 on the substrate 1 as masks, the fL injector 4'' and the common base region 4 are bonded to a junction depth of 1μ. , formed with a layer resistance of 1 to Ω/gate.

Next, as in the second rotation), a polysilicon layer doped with N-type impurities, e.g., TTF arsenic or phosphorous, is added to
6Ω/portion and selectively etched using photoresist or the like to form the collector portions 5 and 51 of I”L.
Leave 0. After that, it is heated at a low temperature of about 600C and under high pressure (9
By oxidizing in an oxygen atmosphere (atmospheric pressure), the arsenic- or phosphorus-doped polysilicon layer 5,5t has a thickness that is more than 5 times that of a low-concentration single-crystal silicon substrate, and is electrically and chemically oxidized. A high quality oxide film 6 is formed.An oxide film 7 is also formed on the single crystal substrate.

When forming 6.7 on this oxidation 11, a polysilicon layer 5°5
A very shallow junction collector region can be formed by impurity diffusion from '. If necessary, further heat treatment may be performed to create the desired collector region 10,10'. Thereafter, by etching the field oxide film 7 on the single crystal silicon substrate, an oxide MII s is formed on the polysilicon layers 5, 5'' by the difference in thickness between the oxide films 6 and 7.
+ remains. In this state, if necessary, use injector 4.
+, Boron may be diffused into the base 4 to form a high concentration P shadow region having a layer resistance of about 1/2. Next, a polysilicon layer 12 with no additives or with boron added is formed on the entire surface with a thickness of 300 to 50%.
The polysilicon layer 8 may be grown to a thickness of 0A (O). If necessary, heat treatment may be performed to diffuse boron from the polysilicon layer 8 to form a high concentration P shadow region in the portion that will become the base contact (see Figure 2 (C).
)).

Next, 1iill of aluminum is vapor deposited on it to a thickness of 1 to 2 microns, and then a wiring pattern is formed by etching using a photoresist or the like as a mask (FIG. 2(d)).

The I'L formed as described above has the following characteristics. That is, the collector of I''L is 10°10'
No complicated process such as nitride film is required to form the nitride film, and the margin between the collector and the base can be made extremely small by using self-alignment. At this time, the collector-base breakdown voltage is significantly improved by using a high-pressure oxide layer. In addition, by placing the polysilicon layer 12 under the aluminum electrode 11, the injection efficiency can be increased without reducing the amount of impurities in the emitter of the horizontal PNP transistor as an injector. On the other hand, the aluminum electrode does not sink.

As explained above, according to the present invention, an extremely small area fL can be manufactured in a self-aligned manner without requiring a complicated manufacturing process, and the effect thereof on the high integration of semiconductor devices is significant.

[Brief explanation of the drawing]

FIGS. 1(al) and 1(b) are process cross-sectional views showing an example of a method for manufacturing I2L by a conventional method, and FIGS. 2(51) to (51) to (
d) is a process sectional view showing one embodiment of the present invention. 1 is an N-type substrate, 2 is an isolation oxide film, 3 is a field oxide film, 4 is a P-type base region, 4'...P-type injector region, 5 and 51 are polysilicon doped with impurity wax (As or P), 6 is a polysilicon oxide film, 7 is a nitride film on polysilicon, 8 is a field nitride film, 91 is a selective oxide film of polysilicon, 10 is a collector, 11 is an aluminum electrode, 12 is an impurity added (boron) or not. The added polysilicon is shown respectively. foil diagram

Claims (1)

[Claims] The semiconductor region is formed on the polycrystalline semiconductor layer by forming a polycrystalline semiconductor layer containing other conductive impurities on a part of the semiconductor region of one conductor, and oxidizing the polycrystalline semiconductor layer in a high-pressure, low-temperature oxidizing atmosphere. Another conductor tm<
forming a semiconductor region; removing the oxide film from the entire surface by at least the thickness of the oxide film formed on other parts of the semiconductor region; and forming a conductor on the exposed semiconductor region. A method for manufacturing a semiconductor device, comprising a step of forming a layer.