JPS622655A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the resistance in an outer base and to reduce the electrostatic capacity between a base and a collector, by using anisotropic etching, forming a hole, whose side surface is approximately vertical, in an outer base region, oxidizing the inner surface of the hole, depositing a semiconductor thereon, introducing high-concentration impurities, and forming the low-resistance outer base. CONSTITUTION:On a one-conducting type semiconductor layer 5, insulator layers 13 and 14 are formed. A hole 4 is formed in one-conducting type semiconductor layer 5 through the insulator layers 13 and 14 in an outer base region. Then an insulator layer 15 is selectively formed on the inner surface of said hole 4. Reverse conducting type impurities are introduced into an intrinsic base region surrounded by the hole 4, and an intrinsic base 6 is formed. A reverse conducting type semiconductor layer 16 is formed in the hole 4, and an outer base 7 is obtained. The insulator layers 13 and 14 are removed. One conducting type impurities are introduced in the intrinsic base 6 beneath the layers 13 and 14, and an emitter 8 is formed. Thus the very small emitter can be readily formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is an improvement that reduces the capacitance between the base and collector of a vertical bipolar transistor, lowers the resistance of the external base, and simplifies the method of forming the emitter.

Anisotropic etching is used to form an opening in the external base region with nearly vertical sides, the inner surface is oxidized, a semiconductor is deposited on top of the opening, and a semiconductor is heavily doped into the opening to achieve low resistance. In order to form the external base of , the area of the base-collector junction is made extremely small to reduce the base-collector capacitance, and at the same time, through the above steps,
An extremely small emitter can be easily formed by lowering the resistance of the external base and by utilizing the bird's beak phenomenon that occurs during the process of forming an insulating film on the external base.

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device. In particular, the invention relates to improvements that reduce the base-collector capacitance of vertical bipolar transistors, lower the external base resistance, and facilitate the formation of emitters with reduced dimensions.

(Prior Art) The structure of an example of a planar bipolar transistor according to the prior art is shown in FIG. , 6 is an intrinsic base, 7 is an external base connecting the intrinsic base 6 and the base electrode 11, and 8 is an emitter.

9 is a field insulating film, and 10 and 2 are an emitter electrode and a collector electrode, respectively.

The active region where the transistor operates is limited to the region near the emitter 8 (intrinsic base 6).

In other words, the external base 7 only has the function of connecting the intrinsic base 6 and the base electrode 11. Therefore, it is desirable to reduce the resistance of this external base by making the impurity concentration as high as possible.Also, a large capacitance is generated along the pn junction that forms the interface between the base and the collector, reducing the operating speed of the transistor. Therefore, it is desirable that the pn+ffi junction area between the base and collector be as small as possible.Furthermore, in order to improve the degree of integration and reduce the pn junction area between the base and collector, the base should be made as small as possible. However, when trying to increase the impurity concentration of the external base of a bipolar transistor with a structure as shown in FIG. It is not possible to increase the impurity concentration only in the extrinsic base because diffusion will extend to the collector region and the intrinsic base region, changing the entire layer structure. Furthermore, since it is necessary to provide a space between the collector electrode and the base electrode, it is difficult to extremely shorten the length of the external base, and there is a limit to reducing the area of the pn junction between the base and collector. .

Therefore, it is desired to develop a method for manufacturing a semiconductor device that can reduce the external base resistance, reduce the base-collector capacitance, and easily form an extremely small emitter. was.

[Means for solving problems]

The means taken by the present invention to eliminate the above-mentioned drawbacks is to form an insulator layer 13, 14 on the semiconductor layer 5 of one conductivity type,
In the external base region, an opening 4 is formed in the semiconductor layer 5 of one conductivity type through the insulating layer 13, 14, and an insulating layer 15 is selectively formed on the inner surface of the opening 4;
Impurities of the opposite conductivity type are introduced into the intrinsic base region surrounded by the opening 4 to form the intrinsic base 6, and a semiconductor layer 16 of the opposite conductivity type is formed in the opening 4 to form the extrinsic base 7.
This method of manufacturing a semiconductor device includes the steps of removing the insulator layers 13 and 14 and introducing impurities of one conductivity type into the underlying intrinsic base 6 to form an emitter 8.

[Function] The present invention, as shown in FIG. 1(a) and FIG. 1(b),
An insulating layer 15 is interposed between the external base 7 and the collector region 5 existing under the external base 7, and this region (insulating layer 1
The base-collector capacitance is reduced to a negligible level by eliminating the pn junction from the region where the external base 7 exists (the region where the insulating layer I5 exists). is used as a diffusion stopper to make it possible to introduce impurities to a high degree only into the external base region 7, and the surface layer of the external base region 7 is oxidized to form an insulating film 9. By utilizing the bird's beak generated during the oxidation process, the window method enables the formation of extremely small emitter regions without the need for additional processes.

(Example) A vertical bipolar transistor according to an example of the present invention will be further described below with reference to one drawing.

Refer to FIG. 2. An n+ layer is formed in a part of the p-type silicon substrate 1,
Let it be n+buried layer 2. Next, add 2 to 34 n-type layers.
The collector region 5 is formed by epitaxial growth to a thickness of m. Field oxide film 3 is formed by oxidizing areas other than the base formation region.
and on top of that, a pad 5102 with a thickness of about 300 mm
An insulating film consisting of the film 13 and a CVD Si3N4 film 14 having a thickness of about 0.2 μLm is formed.

An opening 4 having a depth of about 0.5 .mu.m is formed in the external base region by using a chlorine-based active ion etching method using a chlorine-based gas. Since this etching method is anisotropic, the etching is approximately perpendicular to the end face of the opening 4.

Refer to FIG. 3. Using the above insulating layers 13 and 14 as a mask, the inner surface of the opening 4 is oxidized to form a SiO2 film 1 with a thickness of about 5,000.
Forms 5al. At this time, the intrinsic base region becomes much shorter than the length of the insulator layer 13.14, and the base-collector contact area (pn junction area) becomes smaller.

Then, p-type impurity ions are implanted through the insulator layers 13 and 14 to form the intrinsic base 6.

As mentioned above, since the base-collector pn junction area is small, the base-collector capacitance is small.

S+02 film 15a with controlled etching
The insulator layer 15 is formed by reducing the thickness of the insulator to about 0.3 dilatation.

A non-doped polycrystalline silicon layer 1 is formed using the CVD method (see FIG. 5).
8 to a thickness of about 0.5 mm. A p-type impurity is ion-implanted at a high concentration and heat treatment is performed to convert the polycrystalline silicon layer 16 to a high-concentration P-type.

Using the CVD method (see Fig. 6), Si3 with a thickness of about 0.2 pLm was prepared.
After forming the N4 film 17, it is removed from areas other than the external base area, leaving it only on the external base area.
Polycrystalline silicon layer 1 is formed using 5i3N4 film 17 as a mask.
6 (a portion above the surface of the insulator layers 13 and 14) is oxidized.

Referring to FIG. 17, the polycrystalline silicon layer 16 in the oxidized region is dissolved and removed.
Next, the Si3N4 film 17 is dissolved and removed. As a result,
Polycrystalline silicon layer 16 will remain only in the extrinsic base region.

Next, the surface of the polycrystalline silicon layer I6 is oxidized to a thickness of about 0.1 gm to form an insulating film 18. The polycrystalline silicon layer 16 in its lower region is converted into an external base 7. At this time, the p-type impurity is transferred from the polycrystalline silicon layer 16 to the intrinsic base 6.
The high concentration P-type head region 6a is formed by diffusion into the interior. At the same time, the surface layer of the intrinsic base 6 is narrowed as shown due to the bird's beak.

Referring to FIG. 8, the insulator layers 13 and 14 are dissolved and removed, and an n-type impurity is introduced into the surface layer of the intrinsic base 6 to form an emitter 8.

Forming a polycrystalline silicon layer 18 with a thickness of 0.1 pm,
This is buttered so that it remains only on the emitter 8.

Refer to Figures 1(a) and 1(b). Electrode contact windows are formed in the base electrode forming area and the collector electrode forming area, and an aluminum film with a thickness of approximately 0.9mm is formed, and this is patterned. , emitter electrode 10
, a base electrode 11, and a collector electrode 12 are formed.

In the vertical bipolar transistor manufactured using the above process, an insulating layer is interposed between the lower surface of the external base and the upper surface of the collector region, and this insulating layer is used to form a contact between the intrinsic base and the collector. Since it protrudes into the intrinsic base region to reduce the area, the base-collector capacitance is reduced, and the above-mentioned insulating layer functions as a diffusion stopper in the process of forming the external base, so that the external The impurity concentration of the base is made sufficiently high and the resistance is made low.Furthermore, the area of the emitter is made extremely small due to the bird's beak generated in the process of forming an insulating film on the external base. Easy and sure.

(Effects of the Invention) As explained above, in the present invention, an anisotropic etching is used to form an opening whose side surfaces are generally vertical, the inner surface of the opening is oxidized, and a semiconductor is formed on the opening. By depositing and introducing impurities into this at a high concentration to form a low-resistance external base, the area of the base-collector junction can be made extremely small, reducing the base-collector capacitance, and at the same time, the above-mentioned This process lowers the resistance of the external base, while making use of the bird's beak phenomenon that occurs during the process of forming an insulating film on the external base to easily form an extremely small emitter. It is possible to provide a method for manufacturing a semiconductor device in which base resistance can be reduced, base-collector capacitance can be reduced, and an extremely small emitter can be easily formed.

[Brief explanation of drawings]

1(a) and 1(b) are a plan view and a cross-sectional view taken along line A-A of a vertical bipolar transistor manufactured using a method for manufacturing a semiconductor device according to an embodiment of the present invention. be. 2 to 8 are manufacturing process diagrams of a vertical bipolar transistor according to an embodiment of the present invention. FIG. 9 is a cross-sectional view of a brainer type bipolar transistor according to the prior art. 1...p-type silicon substrate, 2...n+ buried layer, 3-11@field insulating film, 4--opening, 5-1 fist collector, 6-tatami-intrinsic base, 61--high impurity Area, 7--external base,
8・・Emitter, 9・O・Insulating film, °10
・@11 emitter electrode, ゛11...base electrode, 1
2--Collector electrode, 13--S+02 film,
14e**SiN film, 15a * * * 5
in2 membrane, 15, . 18... Insulator layer, 18...
Polycrystalline silicon layer, 17... SiN film, 19
...Polycrystalline book wo Kiri Risome 8 1st (Q)l! I Cb) I! i 2nd flash n figure @3 figure L figure 3g4 figure futami figure 5WI F L eye lET figure 118 figure

Claims (1)

[Claims] An insulating layer (13, 14) on a semiconductor layer (5) of one conductivity type.
forming the insulating layer (13, 14) in the external base region;
an opening (4) penetrating through the semiconductor layer (5) of one conductivity type;
an insulating layer (15) is selectively formed on the inner surface of the opening (4), and an opposite conductivity type impurity is introduced into the intrinsic base region surrounded by the opening (4) to form an intrinsic base (6). ) is formed in the opening (4), a semiconductor layer (16) of opposite conductivity type is formed as an external base (7), and the insulator layer (13,
14) and introducing an impurity of one conductivity type into the underlying intrinsic base (6) to form an emitter (8).