JPS62141767A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the high frequency characteristics, the reliability and the yield of production of a transistor using a simple constitution by a method wherein the first isolation silicon oxide film is provided on the outer edge part of a collector region, a base lead out electrode is provided in the prescribed region of a field oxide film located on the circumference of a base region through the first isolation oxide film. CONSTITUTION:The first isolation insulating film 12 is formed on the outer edge part of one conductive type semiconductor layer 4 surrounded by an element insulating film 5, a low density the other conductive type diffusion layer 13c is formed on the prescribed region in the above-mentioned semiconductor layer 4, and a medium density the other conductive type diffusion layer 13a connected to the circumference of said layer 13c and a high density the other conductive type diffusion layer 13b connected to the circumference of the layer 13a are provided. Then, the other conductive type semiconductor film 15b, formed on the prescribed region on the element insulating film 5 through the above-mentioned first isolation insulating film 12 and connected to said high density other conductive diffusion layer 13b, the second isolation insulating film 18 formed on the surface of the film 15b, and a high density other conductive type diffusion layer 13c located on the inner edge part of the second isolation insulating film 18, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a high-speed, high-density bipolar semiconductor device structure and a method for manufacturing the same.

In order to realize high speed and high density in conventional bipolar type 2 transistors, it is necessary to miniaturize the pattern and reduce the junction capacitance. Therefore, studies have been made to miniaturize the base region and reduce the emitter-base junction capacitance by forming the base lead-out electrode with a polycrystalline silicon film (Poly-5i film). Japanese Patent No. 60-81862 proposes a structure of a fine bipolar type 2 transistor and a method of manufacturing the same using the self-line technology using the manufacturing method shown in FIG.

This transistor has a silicon oxide film (5i
n2) 33 and silicon nitride film (Si5Na film) 34
An insulating film consisting of P+ is provided around a predetermined base region.
By providing a base lead-out electrode made of a Po1y-8i film 36 on the insulating film 33, 34, the collector region 2 and the base lead-out electrode 36 are electrically separated.

In the above transistor manufacturing method, after buttering the p+ type Poly-5i film 35 that will serve as the base extraction electrode, the underlying 513N4 film 34 is etched away by an appropriate amount of side etching using itself as a mask. The film 33 is etched away to form a P+ type Po
The eaves portion of the 1y-8i film 35 is formed. After that, a Po1y-3i film 3 that will become a base contact is placed on this eave part.
6 is embedded and heat treated to form a P+ type Po1y-
Needle-shaped diffusion is performed using the 3i film 35 as a source, and the embedded P
An external base diffusion layer 37 is formed in the collector region 2 via the o1y-5i film 36. After that, the active base diffusion layer 3
B and emitter region 39 are sequentially formed. This provides a manufacturing method in which the base lead-out electrode, the base region, and the emitter region are formed using the same forming pattern.

Problems to be Solved by the Invention These conventional structures and manufacturing methods have the following problems.

(1) Collector region 32 and base extraction electrode 36
The separation of the thin SiO□ film 33 on the film 3 with high dielectric constant 5
Since it is composed of an insulating film made of the isN4 film 34, the parasitic capacitance between the collector base and the lead-out electrode is large, which deteriorates the high frequency characteristics of the transistor. Furthermore, since the surface of the base-collector junction is protected by the insulating film made of chemically incomplete 5i3NJ34, leakage current at the junction is large, reducing the reliability of the transistor.

) In the formation of the Poly-3i film 36 and the external base layer 37 that will serve as the base contact,
Since the length of the eaves of the -3i film 35 varies due to side etching of the Si3N4 film, it is difficult to control the width of the base contact to be constant.

In addition, since the P1 type diffusion using the P+ Po1y-3i film 35 as a source is performed via the Po1y-3i film 36 formed in the eaves, the concentration of the P+ type impurity (boron) in the external base layer 370 is controlled to be constant. It's also difficult. For these reasons, it is difficult to control the base resistance of transistors with good reproducibility and manufacture them with good yield.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the high frequency characteristics, reliability, and yield of a transistor with a simple configuration.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a transistor structure with a first layer on the outer edge of the semiconductor layer of the collector region surrounded by the field oxide film, which is in contact with the side surface of the base region. By providing an isolated silicon oxide film around the base region and providing a base lead-out electrode in a predetermined region on the field oxide film via the first isolation oxide film, the collector region and the base lead-out electrode are electrically connected. It is something that is separated.

In the above method for manufacturing a transistor, a laminated film is formed on a substrate having a semiconductor layer in the collector region, the lower and upper layers are anti-oxidation films, and the middle layer is an impurity-doped silicon film, and then selectively oxidized to form a layer on the collector region. A first impurity-doped silicon oxide film is formed around the impurity-doped silicon film. Thereafter, the upper layer anti-oxidation film and the first impurity-doped silicon oxide film are removed, and ions are implanted using the remaining impurity-doped silicon film as a mask to form a medium-concentration first external base diffusion layer.

After that, the impurity-doped silicon film is oxidized to form a second impurity-doped silicon oxide film, and the underlying oxidation prevention film is removed using this as a mask to select the doped polycrystalline silicon film that will become the base extraction electrode. Form. after that,
The second impurity doped recon oxide film is removed, and an impurity is diffused using the doped polycrystalline silicon film as a source by heat treatment in an oxidizing atmosphere. forming a second external space diffusion layer and simultaneously forming a second isolation silicon oxide film on the doped polycrystalline silicon film; Thereafter, the underlying oxidation prevention film is removed, and an active base diffusion layer and an emitter diffusion layer are sequentially formed. In this way, the isolation silicon oxide film, the base lead-out electrode-base region, and the emitter region are formed in a self-aligned manner using the same formation pattern.

Function: According to the structure of the transistor described above, the collector region and the base lead-out electrode are separated by the thick first isolation silicon oxide film that is in contact with the side surface of the base region. The parasitic capacitance between the collector paste lead electrodes becomes sufficiently small, and the high frequency characteristics of the transistor can be improved.

In addition, since the surface of the base-collector junction is protected by a chemically perfect first silicon oxide film, the leakage current of the junction is small and the junction is flat, so the reverse breakdown voltage does not decrease, so the transistor reliability can be improved.

According to the manufacturing method described above, the width of the base contact window is controlled to be constant depending on the amount of the first impurity-doped silicon oxide film. Further, since the external base layer is formed by ion implantation using the impurity-doped silicon film as a mask and by direct impurity diffusion using the doped polycrystalline silicon film as a source, the impurity concentration is controlled to be constant. For these reasons, the base resistance of the transistor can be controlled with good reproducibility, and the yield can also be improved.

Embodiment FIGS. 1A and 1B are a cross-sectional configuration diagram and a cross-sectional configuration diagram of essential parts showing an example of a semiconductor device according to the present invention. In the same figure B, 4 is an N-type silicon semiconductor layer in the collector region, 5 is a field oxide film for isolation between elements, 12 is a first isolation silicon oxide film between collector base extraction electrodes, and 13L is a P
+ type first extrinsic base diffusion layer, 13b is p++ type second extrinsic base diffusion layer, 13C is p type active pace diffusion layer, 1
5b is a base extraction electrode of P← type polycrystalline silicon film;
1B is a second isolation silicon oxide film between the emitter base extraction electrodes, 194 is a type 1 polycrystalline silicon emitter electrode, 20tL is an N+ type emitter diffusion layer, 21& is an emitter metal electrode, and 21G is a base metal electrode.

In such a configuration, the first isolation silicon oxide film 1
2 is formed so as to be connected to the field oxide film 6 from the side surface of the second external base layer 13b, so that the base extraction electrode 16b and the collector region 4 are electrically connected to each other by this first isolation silicon oxide film 12. is insulated. Since the first isolation silicon oxide film 12 can be formed thickly, the parasitic capacitance between the collector base and the lead-out electrodes can be sufficiently small. From this, the cutoff layer wavenumber (fa) of the transistor is improved, so
High frequency characteristics can be improved.

In addition, since the surface of the collector-base junction is protected by a chemically perfect first isolated silicon oxide film 12 formed by a thermal oxidation method, the interface between silicon oxide film and silicon oxide film is electrically stable. , and the junction leakage current becomes smaller. Since this first isolation silicon oxide film 12 is in contact with the side surfaces of the first and second external base layers 13a and 13b, the collector-base junction surface becomes a plane.
Reverse breakdown voltage does not decrease. For these reasons, the electrical characteristics of the collector-paste junction are improved, so the reliability of the transistor can be improved.

Furthermore, since the external base region is composed of the first and second external base layers 131L and 13b, the highly doped second external base layer 13b does not come into contact with the highly doped emitter diffusion layer 20&. and a low concentration active base layer 130 via a medium concentration first external base layer 13+L.
is connected to. As a result, the emitter-base junction capacitance (Cj,) can be made small, and the base resistance (rbb) can also be made small, and the high frequency characteristics of the transistor can be improved.

Next, a method for manufacturing a semiconductor device according to the present invention will be explained.

FIG. 2 is a cross-sectional process diagram showing an example in which the method for manufacturing a semiconductor device according to the present invention is applied to a method for manufacturing an NPN transistor.

In FIG. 2, a P-type semiconductor substrate (here, a silicon substrate, hereinafter referred to as a Si substrate) 1 is prepared using a well-known technique.
2% N+ type buried layer as collector embedding, P 10 type diffusion layer as channel stopper, H type semiconductor layer as collector (herein epitaxial layer, hereinafter referred to as shrimp layer) 4
are formed sequentially. After that, a field oxide film (hereinafter referred to as 5i02 film) 5 is applied as an element isolation by selective oxidation method.
After forming, a well-known technique is used to form an N+ decadal diffusion layer as a collector all. Thereafter, after forming a SiO2 film 7 as a base film on the Si substrate 1 by thermal oxidation method, c.
By the vn method, a silicon nitride film (hereinafter referred to as 5isN4 film) 8 as the first oxidation prevention film, a phosphorus (P) doped polycrystalline silicon film (hereinafter referred to as phosphorus doped Po1y-3i film) 9 as the impurity-doped silicon film, A 5j-5N4 film 1o is sequentially laminated as a second oxidation prevention film. Note that, in order to form the Po1y-8i film 9 (doped), a non-doped Po1y-8i film 9 is formed on the Si substrate 1 by the C''/D method.
After depositing the 1y-8i film, it is also possible to perform doping with a predetermined impurity, for example, by ion implantation.

Next, using a photoetch technique, a first Si 5N layer is deposited on the predetermined emitter and collector contact regions.
4 films 8&, 8b, phosphorous-doped Po1y-8i film 91L
, sb and a second 5i5N4 film are formed (see FIG. 2).

Next, using the first 5i5N4 film 81L as a mask, the phosphorus-doped Po1y-3i film 9 surrounded by the field 5i02 film and sandwiched between the shrimp layers is also oxidized from the surroundings, and the first phosphorus-doped 5i02 film 11N and 11b (hereinafter referred to as PSG film) are formed. At this time, the first
By controlling the oxidation pattern of the PSGSi film 8L, it is possible to leave the phosphorous-doped POIY-Si film 9a having a fine width on the emitter region (FIG. 2B).

Next, the second Si3N4 films 10a, 1Qb are etched by chemical dry etching, and the first PSG films 11a, 1Qb are etched.
1b is sequentially removed by etching with a dilute hydrofluoric acid solution. Thereafter, using the remaining phosphorus-doped Po1y-3i film 9a as a mask, ions of, for example, boron (B) are implanted into the shrimp layer 4 next to the first separated SiO2 film 12 into the P-type first external space diffusion layer 13iL. (Figure 2C).

Next, the phosphorous-doped Po1y-Si films 9a and 9b are thermally oxidized to form the first Si 5N 4 film 8ZL18b.
Second psc films 142L and 14b are formed thereon. At this time, the second PSG film 14a expands in volume, so the second PSG film 14a expands in volume.
The ends of the membrane pores 4 of the PSE membrane 1 extend onto the P+ type first external pace diffusion layer 13a. In other words, the second psG film 1
41L outer end 2 p + type first external base diffusion layer 13
A gap is created between the inner end of 2L (FIG. 2D) Next, using the second PSE films 14a and 14b as a mask,
The first 5i5N4 films 8a and 8b are removed by chemical dry etching, and the 5i02 film 7 is removed by etching with a hydrofluoric acid solution. At this time, the shrimp layer 4 around the second PSG film 142L is exposed, and a base contact region is formed as a self-line.

Next, a semiconductor film (herein, a polycrystalline silicon film, hereinafter referred to as a Poly-Si film) 1 is formed on the Si substrate 1 by the CVD method.
5 is laminated. After that, the second PS is formed by an etchback method using a coating film (here, a photoresist film)
Only the Po1y-8i film 16 on the GSi films 2L and 14b is selectively removed (FIG. 2E).

Next, a 5i5N4 film 16 is formed on a predetermined region of the Si substrate 1 using a well-known technique. After that, the 20th page
Only the SG film 14b is removed by etching with a dilute hydrofluoric acid solution. After that, using the Si3N4 film 16 as a mask, the Po1
The y-Si film 15 is selectively oxidized to form a Po1y-3i film 161L and a 5102 film 17 which will serve as a pace extraction electrode (FIG. 2F).

Note that the Po1y-3i film 15, which serves as a pace extraction electrode,
Other methods can also be used to form a. For example, if the Po1y-5i film 16 outside a predetermined area is etched away using a well-known photoetching technique, P
The o1y-3i film 162L can be selectively formed.

Next, the 5i5N4 film 16 is etched away using a well-known technique. Thereafter, boron (B) is selectively ion-implanted into the Poly-3i film 15a using, for example, photolithography, and then the second PSG film 14a is
Remove by etching with acid solution. Thereafter, when the Si substrate 1 is heat-treated in an oxidizing atmosphere, Po1y-3
The i film 15a becomes a P+ 10-type Po1y-Si film 15b,
Then, boron diffuses into the shrimp layer 4 in a solid phase as a source of the P+ ten-shaped Po1y-3i film 16b'i of the P+
Inside the first external base diffusion layer 13 &tc p ++
A ten-shaped second external base diffusion layer 13b is formed. At the same time, using the first 5i5N4 film 8a as a mask,
The surface of the P+ decade Po1y-5i film 15b is selectively oxidized,
A second isolation 5i02 film 18 is formed (FIG. 2G).

Next, the Si5N4 films 8a and 8b are removed by etching, boron ions are implanted through the underlying SiO2 film 7, and heat treatment is performed to form a P-type active base diffusion layer 130 in a self-lined manner. Thereafter, the 5i OJT is etched away, and the emitter Po1y-3i
N-shaped P which becomes the electrode and collector Po1y-8i electrode
o1y-8i films 192L and 19b are formed. Thereafter, heat treatment is performed to diffuse N-type impurities (in this case, H) using the N+ type Po1y-8i film 19 as a source.
A ten-shaped emitter diffusion layer 20& and an N-shaped collector contact diffusion layer 20b are formed. In this way, the P++ form 2nd
A structure in which the P-type active base diffusion layer 13C is connected to the P-type active base diffusion layer 13C via the P+ 10-shaped first external base diffusion layer 13& without contacting with the external base diffusion layer 13b&-iN+N-shaped patterned diffusion layer 202L can be formed by self-line. (Figure 2) 1)
.

Miter aluminum alloy electrode (hereinafter referred to as aluminum-silicon alloy, hereinafter referred to as M1-8i) 211L.

KL/RIp kl-3i electrode 21b1 base IJ-
8i electrode 21c is formed. In this way, H in this example
The PN type transistor is completed (Fig. 2).

In the transistor manufactured in this way, the base contact window connecting the p++ type Po1y-5i film 15b of the base extraction electrode and the p++ type external base layer 13b is
Since the periphery of the phosphorus-doped silicon film pattern 9a is formed using the PSG film 11&, which is oxidized, the width of the window is controlled to be constant depending on the amount of oxidation, and as a result, the contact resistance of the window is also controlled to be constant. In addition, the P-type first external base layer 13& and the P++-type second external base layer 13b connecting the p++-type external forming part base layer 16b with the active space layer 130 are formed of phosphorous-doped Po1y-3i.
By implanting boron ions using the film 9& as a mask, the latter is removed from the base contact window to the P-cube-shaped Poly-5i film 13.
Since they are formed by direct solid-phase diffusion using b as a poron source, the respective boron concentrations are controlled to be constant, and as a result, the diffusion resistance is also controlled to be constant. From the above,
The base resistance of the transistor can be controlled with good reproducibility, and the yield can also be improved.

And phosphorus dope for the same formation) Poly-8 film 9
By a, the first isolated SiO2 film 12, the P++ type Po1y-8i film 16b of the base extraction electrode, the p+ 10 type first external base layer 13&, the P++ type active base layer 13
b, second isolation 5102 membrane 18, P-type active base layer 13
The C and H 10-type emitter layers 20iL can be sequentially formed in a self-aligned manner and finely.

In particular, the P-type active base layer 130 and N
The 10-shaped emitter layer 20a can be formed with fine dimensions without depending on the design dimensions of the mask.

In this embodiment, the N+ type transmitter layer 202L was formed by solid phase diffusion from the N+ type Poly-8i film 194, but it could also be formed by other methods such as ion implantation of N type impurities. Further, although the method for manufacturing an NPN transistor has been described, it goes without saying that this effect can also be obtained using a method for manufacturing other semiconductor devices.

Effects of the Invention As described above, according to the present invention, it is possible to realize a high-speed, high-density bipolar semiconductor device that can improve the high frequency characteristics, reliability, and yield of transistors with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device of this embodiment, and FIG. 3 is a process diagram showing a conventional method for manufacturing a semiconductor device. It is. 4... N-type Si semiconductor layer, 6... Field 5i02 film, 12... First separation 510
2 membranes 13&...P 10-shaped first external paste layer, 1
3b...P++ type second external base 4s 130
...P type active heath layer, 16b...P
++ type Po1y-8i membrane, 18... second separation 5102 membrane, 19a... N ten type Po1y-8i
Membrane, 20 a...N+decade transmitter layer, 211
L... Emitter 1-Si electrode, 21C...
...Base person 4Si electrode. Name of agent: Patent attorney Toshio Nakao and one other person a)

Claims (4)

[Claims] (1) An element insulating film that separates the one conductivity type semiconductor layer formed on one main surface side of a substrate having the one conductivity type semiconductor layer, and an outer edge portion of the one conductivity type semiconductor layer surrounded by the element insulating film. a first isolation insulating film formed above, a low concentration diffusion layer of the other conductivity type formed in a predetermined region within the semiconductor layer of the one conductivity type, and a medium concentration diffusion layer of the other conductivity type connected to the periphery of the diffusion layer of the low concentration diffusion layer of the other conductivity type. a high concentration diffusion layer of the other conductivity type connected around the middle concentration diffusion layer of the other conductivity type; the other conductive type semiconductor film formed in a predetermined region on the element insulating film, the second isolation insulating film formed on the surface of the other conductive type semiconductor film, and the low concentration at the inner edge of the second isolation insulating film. A semiconductor device comprising a high concentration diffusion layer of one conductivity type formed on a diffusion layer of the other conductivity type. (2) On the other hand, an N-type silicon single crystal layer is used as the conductivity type semiconductor layer,
The semiconductor device according to claim 1, wherein a P-type polycrystalline silicon film is used as the conductive type semiconductor film, and a silicon oxide film is used as the element insulating film, the first isolation insulating film, and the second isolation insulating film. . (3) A step of selectively forming an element insulating film on one principal surface of a substrate having a semiconductor layer of one conductivity type, and doping a predetermined region of the semiconductor layer of one conductivity type with an anti-oxidation film as a lower layer and an upper layer and an impurity doped layer as a middle layer. forming a laminated film pattern made of a silicon film, selectively oxidizing the one conductivity type semiconductor layer using the oxidation prevention film as a mask to form a first isolation insulating film, and at the same time forming a first isolation insulating film; a step of oxidizing the surrounding area to form a first impurity-doped silicon oxide film; a step of sequentially removing the upper layer oxidation prevention film and the first impurity-doped silicon oxide film; and a step of sequentially removing the impurity-doped silicon oxide film. A step of implanting ions into a mask to form a medium concentration diffusion layer in the semiconductor layer of one conductivity type and a diffusion layer of the other conductivity type; and a step of oxidizing the impurity-doped silicon film to form a second impurity-doped silicon oxide film. a step of removing the underlying oxidation prevention film using the impurity silicon oxide film as a mask; and a step of selectively forming the other conductivity type semiconductor film on a predetermined region around the outer edge of the second impurity doped silicon oxide film. , said second
removing the impurity-doped silicon oxide film, and heat-treating the substrate in an oxidizing atmosphere to form a high concentration diffusion layer of the other conductivity type inside the medium concentration diffusion layer of the other conductivity type semiconductor film. forming a second isolation insulating film on the surface of the other conductive type semiconductor film using the lower oxidation prevention film as a mask; removing the lower oxidation prevention film; forming a low concentration diffusion layer of the other conductivity type connected to the medium concentration diffusion layer of the other conductivity type in the semiconductor layer of the one conductivity type at the inner edge of the isolation insulating film; 1. A method for manufacturing a semiconductor device, comprising the step of forming a one-concentration conductivity type diffusion layer. (4) The semiconductor device according to claim 3, wherein a phosphorus-doped polycrystalline silicon film is used as the impurity-doped silicon film, and a phosphorous-doped silicon oxide film is used as the first and second impurity-doped silicon oxide films. Production method.