JPS59188970A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance and the distribution capacitance of lead-out electrodes by improving the arrangement of said electrode from each semiconductor region by a method wherein the second semiconductor region of the reverse conductivity type is provided in the semiconductor region of the first conductivity type, and the third semiconductor region of the first conductivity type is provided in the second region. CONSTITUTION:An N type collector region 1 is formed in the Si substrate constituting a transistor for high frequency. Further, a P-base region 2 of the reverse conductivity to N type is formed, and then an N type emitter region 3 is formed in this region 2. The Si of a part of the emitter side surface junction 4 and the collector side one 5 is removed by etching by using a mask, thus forming a side surface junction removed groove 7. Besides, an oxide insulation film 8 is grown on the inner surface of the groove 7, and a base contact window 2b and an emitter contact window 3b are formed, respectively. A base lead-out electrode 2a and an emitter lead-out electrode 3a are extended on the insulation film 8, reducing the junction capacitance and the distribution capacitance of the electrodes, resulting in the improvement of the high frequency characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency semiconductor device whose parasitic capacitance is minimized.

Conventionally, in the design and manufacture of high-frequency transistors, it has been an important point to increase the continuous frequency (referred to as fT), which is a parameter that determines the gain in the high-frequency band τ. Therefore, conventionally, minute! The emitter-base junction capacitance and the base-collector junction capacitance were made as small as possible by using the short film technology, and the base width was narrowed by using the shallow junction formation technology.

That is, FIG. 1(a) is a plan view of a conventional high frequency transistor, and FIG. 1(b) is a sectional view taken along line AA in FIG. 1(a). In FIGS. 1A and 1B, 2a is a base electrode connected to base region 2 through base contact window 2b, and 3a is an emitter electrode connected to emitter region 3 through emitter contact window 3b. Further, 1 is a collector region of one conductivity type, for example, N type, and base region 2
is of a conductivity type opposite to that of the collector region, for example P type, and is provided in the collector region 1, and the emitter region 3 is of the same conductivity type as the collector region, for example N type, and is provided in the base region 2. . For these collector, base, and emitter regions 1 and 2.3, first, a base region 2 is formed by diffusing P-type impurities into the N-type collector layer 1 using the insulating film 6 on the surface as a mask. Next, an emitter region 3 is formed by diffusing N-type impurities.
The base-to-base junction (referred to as emitter junction) and the base-collector junction (referred to as collector junction) each have a bottom part and a side part, and the junction capacitance of the side part 4 of the emitter junction and the side part 5 of the collector junction is occupies 20 to 30 inches of the total junction capacitance including Further, the collector-to-collector capacitance between the emitter lead-out electrode 3a and the base lead-out electrode 2a for electrical connection with the outside has a capacitance comparable to the junction capacitance.

The object of the present invention is to reduce the junction capacitance and the distribution valley of the extraction electrode, which are inevitably attached to the structure as described above, and to
An object of the present invention is to provide a semiconductor device with improved high frequency characteristics.

The semiconductor device of the present invention has a second semiconductor region of an opposite conductivity type within a first semiconductor region of a negative conductivity type, and a third semiconductor region of one conductivity type within the second semiconductor region. , the third
and a portion of the side junction between the second semiconductor region and the first semiconductor region.
A groove is provided by removing the side junction between the first semiconductor region and the second semiconductor region, the inner surface of the groove is covered with an insulator, and then the third and second semiconductor regions are connected to the third and second semiconductor regions on the insulator. It has a configuration in which the extracted extraction electrodes are each extended.

Next, the present invention will be explained by examples.

FIG. 2(a) is a plan view of an embodiment of the present invention, and FIG. 2(b) is a plan view of an embodiment of the present invention.
is a sectional view taken along line A-A in FIG. In Figure 2,
- between a first semiconductor region (collector region) 1 of conductivity type, for example N conductivity type, and a second semiconductor region (base region) 2 of opposite conductivity type, for example P type, provided in collector region 1; A groove 7 is drilled along the lateral junction to remove this junction, and in particular, this groove 7 is used to remove an N-type emitter region (in case of multiple The inner surface of this groove 7 is cut out with an insulating material 8. The groove 7 is formed wide on the base region side so as to include the lateral joint between the groove 7 and the base region. Further, base extraction electrodes 2a and 3a connected through base and emitter contact windows 2b and 3b extend over the insulating film 8.

In such a high frequency transistor of the present invention.

Part of the base-emitter side junction and the base-collector side junction have been removed and replaced with an oxide film (or other insulating film).

Its capacitance is much smaller than the original junction capacitance.
There is. In addition, the base electrode 2 drawn out from the base region
a is #I! , and extends over the T-filled insulating film, the collector capacitance due to this extraction electrode is also significantly reduced compared to the conventional structure without a groove. Therefore, the cutoff frequency (f
r) is increased, and a high frequency transistor with improved high frequency characteristics can be obtained.

FIGS. 3 to 6 are a plan view (a) and a sectional view (b) of the person-A, respectively, in the order of steps for explaining the manufacturing process of a high-frequency transistor according to an embodiment of the present invention shown in FIG. It is. First, the base area 2 as shown in FIGS. 3(a) and 3(b). Worker area 3. As shown in FIGS. 4(a) and 4(b), a collector side surface junction 5 and an emitter side surface dζ are formed on a silicon substrate provided with a collector region l.
To remove portion 4 located close to the rectangular junction,
Except for this portion to be removed, the remaining portions are covered with a nitride film 9. Next, as shown in FIGS. 5(a) and 5(b), using the nitride film 9 as a mask, a portion of the oxide film and silicon of the collector side junction and the emitter side junction near the collector side junction are removed. , wet and dry etching to form grooves 7. Next, oxidation is performed using the nitride film 9 as a mask under a low-temperature oxidizing atmosphere in which the emitter junction and collector junction do not move from the initial setting conditions, and as shown in FIGS. 6(a) and (b), the groove 7 is An oxide insulating film 8 is grown on the inner surface. In this way, a portion of the collector side junction and the emitter side junction can be replaced with an insulating film having a low dielectric constant.

Normally, the junction of ultra-high frequency transistors is formed at a depth of about 0.5 μm from the silicon surface, so the depth of the groove 7 may be about 1 μm, and the depth of the trench 7 is approximately 1 μm. is extremely simple.

Next, from the state shown in FIGS. 6(a) and 6(b), the nitride film 9
The emitter is removed by solution or dry etching, and a contact window is opened for the electrodes in the emitter and base regions to form an emitter extending over the insulating film 8 as shown in FIGS. 2(a) and 2(b). and base extraction electrode 3
What is necessary is to form a and 28.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a conventional high frequency transistor.
Figure 2(b) is a sectional view taken along line A-A in Figure 2(a), and Figure 2(a)
U A plan view of one embodiment of the present invention, the same figure (b) is the same figure (a
), Figures 3(a) to 6(a) are
FIG. 6 is a plan view of the manufacturing process of an embodiment of the present invention shown in the figure, and a sectional view taken along the line A-A in FIG. 3(a) of FIG. 3(b) to FIG. DESCRIPTION OF SYMBOLS 1... N-type collector region, 2... P-type base region, 2a... Base extraction electrode, 2b
...Base contact window, 3...N-type emitter region, 3a...Emitter extraction electrode,
3b...Emitter contact window, 4...
・Emitter side bonding, 5... Collector side bonding, 6... Oxide film, 7... Side bonding groove removed, 8... Inner surface of removal groove Insulating film, 9...
...Nitride film. Figure 1 7--"'--] Sanskrit Figure 3 (b) Figure 5 Figure 6 1 Procedural amendment (formality) Commissioner of the Patent Office 1, Indication of case 1988 Special request No. 6406
No. 6 No. 2, Title of the invention: Semiconductor device 3, Relationship with the case of the person making the amendment Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: Tomoe Amendment Subject of the specification Columns for opaque and simple explanations Contents of amendment (1) Lines 11 to 14 of page F of the specification "Figure 3 (a) -
FIG. 6(1) is a sectional view taken along line A-A. ” is corrected as below. [FIG. 3(b)), FIG. 4(a), FIG. 5(, ), and FIG. 6(a) are plan views showing the substrate in the order of manufacturing steps of an embodiment of the present invention; Figure 3(b), Figure 4(b)
), Figure 5(b) and Figure 6(1)) are respectively
Figure (a), Figure 4 (a), Figure 5 (a) and Figure 6 (
It is a sectional view taken along the line A in a). ”

Claims (1)

[Claims] A second semiconductor region of an opposite conductivity type is provided within the first semiconductor region of one conductivity type, a third semiconductor region is further provided within the second semiconductor region, and the third and second semiconductor regions are provided within the first semiconductor region of the opposite conductivity type. A trench is provided by removing a portion of the lateral junction between the regions and the lateral junction between the second and first semiconductor regions, and the inner surface of the trench is covered with an insulator. A semiconductor device, wherein lead electrodes respectively connected to the second and third semiconductor regions extend above the semiconductor device.