JPS61124175A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61124175A JPS61124175A JP24674384A JP24674384A JPS61124175A JP S61124175 A JPS61124175 A JP S61124175A JP 24674384 A JP24674384 A JP 24674384A JP 24674384 A JP24674384 A JP 24674384A JP S61124175 A JPS61124175 A JP S61124175A
- Authority
- JP
- Japan
- Prior art keywords
- film
- base
- mask
- region
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 22
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 5
- 239000011241 protective layer Substances 0.000 claims 1
- 239000012808 vapor phase Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置および製造方法に係り、そのうち特
に、バイポーラ型半導体装置の新規な構造とその形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a manufacturing method, and more particularly to a novel structure of a bipolar semiconductor device and a method for forming the same.
最近におけるＩＣ，ＬＳＩなど半導体装置の発展は非常
に目覚ましいものがあるが、それらはすべて高集積化、
高密度化して高速動作する方向に技術的検討が進められ
ている。The recent development of semiconductor devices such as ICs and LSIs has been very remarkable, but they have all become highly integrated and
Technical studies are progressing toward higher density and faster operation.
且つ、ＩＣなどの半導体装置はバイポーラ型とＭＩＳ型
との２つのタイプの構造に大別されるが、前者のバイポ
ーラ型の方が同じディメンジョンではＭＩＳ型よりも高
速化が容易なことが知られている。In addition, semiconductor devices such as ICs can be roughly divided into two types of structures: bipolar type and MIS type, but it is known that the former bipolar type can be more easily increased in speed than the MIS type with the same dimensions. ing.
本発明はこのようなバイポーラ型ＩＣにおいて、−Ｎ高
速化するための構造と製造方法に関するものである。The present invention relates to a structure and manufacturing method for increasing -N speed in such a bipolar IC.
［従来の技術〕
第３図は従来の一例のバイポーラ型半導体装置の断面構
造図を示しており、１はｎ型コレクタ領域、２はｐ型ベ
ース領域、３はｎ＋＋エミッタ領域、４は二酸化シリコ
ン（ＳｉＯ２）膜からなるフィールド絶縁膜、５はベー
ス電極、６はエミッタ電極、７はコレクタ電極、８はｎ
＋型型埋階層ある。[Prior Art] FIG. 3 shows a cross-sectional structural diagram of an example of a conventional bipolar semiconductor device, in which 1 is an n-type collector region, 2 is a p-type base region, 3 is an n++ emitter region, and 4 is silicon dioxide. A field insulating film made of (SiO2) film, 5 is a base electrode, 6 is an emitter electrode, 7 is a collector electrode, 8 is an n
+ There is a type-type buried layer.
図のように、バイポーラ型半導体装置はコレクタとベー
スとがｐｎ接合し、ベースとエミッタとがｐｎ接合する
構造が基本となって、作成されている。As shown in the figure, a bipolar semiconductor device is basically manufactured with a structure in which a collector and a base are in a pn junction, and a base and an emitter are in a pn junction.
し発明が解決しようとする問題点］
しかし、接合（ジャンクション）は容量を発生し、その
接合容量が動作の高速化を器官する問題がある。Problems to be Solved by the Invention] However, there is a problem in that junctions generate capacitance, and the junction capacitance increases the speed of operation.
バイポーラ型半導体装置の高周波性能指数ば、Ｆ＝ｆ／
ｒ−ｃ
なる式で表され、Ｆは遮ｖ！ｎ周波数、ｒはベース抵抗
、Ｃはコレクタ容量であるが、この式から明らかなよう
に、特にコレクタ容量（コレクタ・ベース間の寄生容量
）は周波数特性、スイッチング特性に与える影響が大き
い。従って、コレクタ容量を減少するために、従前より
種々の工夫がなされているが、必ずしも十分ではない。The high frequency figure of merit of a bipolar semiconductor device is F=f/
It is expressed by the formula r−c, where F is the interruption v! n frequency, r is the base resistance, and C is the collector capacitance. As is clear from this equation, the collector capacitance (parasitic capacitance between the collector and the base) has a particularly large influence on the frequency characteristics and switching characteristics. Therefore, various efforts have been made to reduce the collector capacitance, but these are not always sufficient.
且つ、上記の式から、ベース抵抗ｒを小さくすると、周
波数特性、スイッチング特性が同様に改善されることが
明らかである。Furthermore, from the above equation, it is clear that by reducing the base resistance r, the frequency characteristics and switching characteristics are similarly improved.
更に、半導体装置の電極接続部、例えばベース領域とベ
ース電極との間にも接合容量が生じて、これも高速動作
に害を与えている。Further, junction capacitance also occurs between electrode connections of the semiconductor device, such as between a base region and a base electrode, which also impairs high-speed operation.
本発明はこれらの容量や抵抗を減少させて、動作を高速
化する構造の半導体装置とその製造方法を提案するもの
である。The present invention proposes a semiconductor device having a structure that reduces these capacitances and resistances to increase the speed of operation, and a method for manufacturing the same.
［問題点を解決するための手段〕
その問題は、エミッタ領域を含むベース領域が単結晶半
導体層に設けられ、該単結晶半導体層を取り囲んだベー
ス電極を有する多結晶半導体層からなるベース領域が設
けられ、該多結晶半導体層からなるベース領域と単結晶
半導体層からなるコレクタ領域との間に絶縁膜が介在す
る構造を具備している半導体装置によって達成される。[Means for solving the problem] The problem is that the base region including the emitter region is provided in a single crystal semiconductor layer, and the base region is made of a polycrystalline semiconductor layer having a base electrode surrounding the single crystal semiconductor layer. This is achieved by a semiconductor device having a structure in which an insulating film is interposed between a base region made of the polycrystalline semiconductor layer and a collector region made of the single crystal semiconductor layer.
且つ、その半導体装置は、エミッタ形成部を含むエミッ
タ形成部周囲領域に保護マスクを被覆し、該エミッタ形
成部周囲領域外の一導電型単結晶半導体基板をエツチン
グして、前記保護マスクの下面をもサイドエツチングす
る工程、次いで、該一導電型単結晶半導体基板の表面に
二酸化シリコン膜を形成した後、上面より耐弗酸性マス
クをスパッタして被覆する工程、次いで、該耐弗酸性マ
スクを保護膜として、前記保護マスクの下の単結晶半導
体基板側面部分に露出した二酸化シリコン膜を弗酸でエ
ツチング除去した後、前記耐弗酸性マスクを除去する工
程、次いで、多結晶半導体膜を気相成長して前記保護マ
スクまで積層し、更に、該多結晶半導体膜の表面を研磨
して平坦化する工程、次いで、保護マスクをマスクとし
て不純物を導入した後、前記保護マスクを除去し、耐酸
化性マスクを形成して、フィールド酸化膜を生成する工
程が含まれる製造方法によって作成される。In addition, in the semiconductor device, a region surrounding the emitter formation portion including the emitter formation portion is covered with a protective mask, and a single-crystal semiconductor substrate of one conductivity type outside the region surrounding the emitter formation portion is etched to remove the lower surface of the protective mask. Next, after forming a silicon dioxide film on the surface of the one conductivity type single crystal semiconductor substrate, a step of sputtering and covering the top surface with a hydrofluoric acid-resistant mask, and then protecting the hydrofluoric acid-resistant mask. After etching and removing the silicon dioxide film exposed on the side surface of the single crystal semiconductor substrate under the protective mask with hydrofluoric acid as a film, the process of removing the hydrofluoric acid-resistant mask is followed by vapor phase growth of a polycrystalline semiconductor film. Then, the surface of the polycrystalline semiconductor film is polished and planarized. Next, impurities are introduced using the protective mask as a mask, and then the protective mask is removed and oxidation-resistant It is produced by a manufacturing method that includes the steps of forming a mask and producing a field oxide film.
［作用］
即ち、本発明にかかるバイポーラ型半導体装置はコレク
タとベースとの間の広い面積部分に絶縁膜（Ｓｉ０２膜
）を介在させてコレクタ容量を減少させ、更に、ベース
に多結晶シリコン領域を設けて、ベース抵抗を減少させ
、且つ、ベース電極は多結晶シリコン領域で接続させて
、その接続容量を小さくする構造にする。[Function] That is, the bipolar semiconductor device according to the present invention reduces the collector capacitance by interposing an insulating film (Si02 film) in a wide area between the collector and the base, and further includes a polycrystalline silicon region in the base. The base electrode is connected to a polycrystalline silicon region to reduce the connection capacitance.
かくして、周波数特性、スイッチング特性が一層改善さ
れた半導体装置を得ることができる。In this way, a semiconductor device with further improved frequency characteristics and switching characteristics can be obtained.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかる半導体装置の断面構造図を示し
ており、１１はｎ型コレクタ領域、１２は単結晶半導体
層からなるｐ型ベース領域、１３は多結晶半導体層から
なるｐ型ベース領域で、上記のベース領域１２を取り囲
んで設けられている。１４はｎ＋型エミッタ領域、１５
は二酸化シリコン（ＳｉＯ２）膜からなるフィールド絶
縁膜、１６はコレクタとベースとの間に介在させている
５ｉ０２膜（絶縁膜）、。FIG. 1 shows a cross-sectional structural diagram of a semiconductor device according to the present invention, in which 11 is an n-type collector region, 12 is a p-type base region made of a single crystal semiconductor layer, and 13 is a p-type base made of a polycrystalline semiconductor layer. The base region 12 is provided surrounding the base region 12 described above. 14 is an n+ type emitter region, 15
16 is a field insulating film made of a silicon dioxide (SiO2) film, and 16 is a 5i02 film (insulating film) interposed between the collector and the base.
１７はベース電極、１８はエミッタ電極である。17 is a base electrode, and 18 is an emitter electrode.
このような構造にすれば、上記したようにコレクタ容量
、ベース抵抗および電極接続容量を少なくすることがで
きて、一層動作が高速化される。With such a structure, the collector capacitance, base resistance, and electrode connection capacitance can be reduced as described above, and the operation speed can be further increased.
次に、その形成方法を第２図ｆａ）〜（ｈ）に示す形成
工程順断面図によって説明する。Next, a method for forming the same will be explained with reference to sequential cross-sectional views of the forming steps shown in FIGS. 2fa) to 2(h).
まず、第２図（ａ）に示すように、ｎ型シリコン基板１
１の上のエミッタ形成領域とその周囲部分に、窒化シリ
コン（Ｓｉ２Ｎ４膜膜２１からなる保護マスクを形成す
る。この保護マスクは、化学気相成長（ＣＶＤ）法でＳ
ｉ３Ｎ４膜２１を被着し、パターンニングして形成され
る。First, as shown in FIG. 2(a), an n-type silicon substrate 1
A protective mask made of silicon nitride (Si2N4 film 21) is formed in the emitter formation region on the emitter formation region 1 and its surrounding area.
It is formed by depositing an i3N4 film 21 and patterning it.
次いで、第２図（１））に示すように、シリコン基板１
１をＣＦ４ガスを用いたドライエツチングによって膜厚
５０００人程度程度等方的なエツチングを行なう。そう
すると、図のようにＳｉ３Ｎ４膜２１の下面までサイド
エツチングされる。Next, as shown in FIG. 2 (1), the silicon substrate 1
1 is isotropically etched by dry etching using CF4 gas to a film thickness of about 5000 mm. Then, as shown in the figure, side etching is performed to the bottom surface of the Si3N4 film 21.
次いで、第２図（Ｃ）に示すように、高温高湿雰囲気中
で酸化して、露出したシリコン基板の表面に５ｉ０２膜
１６を生成する。Next, as shown in FIG. 2C, oxidation is performed in a high temperature and high humidity atmosphere to form a 5i02 film 16 on the exposed surface of the silicon substrate.
次いで、第２図（ｄｌに示すように、その上面から蒸着
法によってタングステン膜２２（耐弗酸性マスク）を被
着する。そうすると、蒸着法は方向性があるから、Ｓｉ
３Ｎ４膜２１の下面のサイドエツチングされた部分に生
成された５ｉ０２膜の部分には被覆されない。Next, as shown in FIG. 2 (dl), a tungsten film 22 (hydrofluoric acid-resistant mask) is deposited on the top surface by vapor deposition.Then, since vapor deposition is directional, Si
The portion of the 5i02 film formed on the side-etched portion of the lower surface of the 3N4 film 21 is not coated.
次いで、第２図（ｅ）に示すように、弗酸溶液によって
露出した５ｉ０２膜（Ｓｉａ Ｎ４膜２１の下面のシリ
コン基板側面部分）をエツチング除去した後、タングス
テン膜２２を王水でエツチング除去する。Next, as shown in FIG. 2(e), the exposed 5i02 film (side surface of the silicon substrate under the Sia N4 film 21) is etched away using a hydrofluoric acid solution, and then the tungsten film 22 is etched away using aqua regia. .
ここに、耐弗酸性マスクとしてタングステン膜２２を用
いたが、その他にモリブテン膜などを用いても良い。Although the tungsten film 22 is used here as a hydrofluoric acid-resistant mask, other materials such as a molybdenum film may also be used.
次いで、第２図（ｆｌに示すように、ＣＶＤ法によって
多結晶シリコン膜１３を被着して、Ｓｉ２Ｎ４膜２１を
含む凸状のシリコン基板１１の部分を埋没させた後、研
磨などにより平坦化し、Ｓｉ３Ｎ４膜２１を表出させる
。その後、Ｓｉ３Ｎ４膜２１をマスクにして外部ベース
となる多結晶シリコンに硼素をイオン注入する。Next, as shown in FIG. 2 (fl), a polycrystalline silicon film 13 is deposited by the CVD method to bury the convex portion of the silicon substrate 11 including the Si2N4 film 21, and is then flattened by polishing or the like. , the Si3N4 film 21 is exposed. Then, using the Si3N4 film 21 as a mask, boron ions are implanted into the polycrystalline silicon that will serve as an external base.
次いで、第２図（幻に示すように、Ｓｉ３ Ｎ４２１を
エツチング除去した後、再び５ｉ０２膜を介在させたＳ
ｉ３Ｎ４膜２３を被着してパターンニングし、半導体素
子形成領域上の全面をマスクして、高温高湿雰囲気中で
酸化処理して、５ｉ０２膜からなるフィールド酸化膜１
５を選択的に形成する。即ち、これは公知のＬＯＣＯ５
法と呼ばれるフィールド酸化膜の形成法である。Next, as shown in Figure 2 (phantom), after removing Si3N421 by etching, S
A field oxide film 1 made of a 5i02 film is formed by depositing and patterning an i3N4 film 23, masking the entire surface of the semiconductor element formation region, and performing oxidation treatment in a high temperature and high humidity atmosphere.
5 is selectively formed. That is, this is the known LOCO5
This is a method of forming a field oxide film called the method.
次いで、第２図ｔｈ）に示すように、５Ｌ３Ｎ４膜２３
をエツチング除去し、半導体素子形成領域上に新しい５
ｉ０２膜２４を形成して、更に、その上から硼素をイオ
ン注入し熱処理して、単結晶半導体層からなるｐ型ベー
ス領域１２を画定する。Next, as shown in FIG. 2th), the 5L3N4 film 23
is removed by etching, and a new 5 is formed on the semiconductor element forming area.
After forming the i02 film 24, boron ions are implanted thereon and heat treated to define the p-type base region 12 made of a single crystal semiconductor layer.
しかる後、公知の方法によって、エミッタ領域１４およ
びベース電極１７．エミッタ電極１Ｂを形成して、半導
体装置が完成される。Thereafter, emitter region 14 and base electrode 17 . The emitter electrode 1B is formed to complete the semiconductor device.
このような形成方法を採れば、上記の半導体装置の構造
を容易に作成することができる。If such a formation method is adopted, the structure of the semiconductor device described above can be easily created.
［発明の効果コ
以上の説明から明らかなように、本発明によればバイポ
ーラ型半導体装置が高速化されて、このような構造から
なるＩＣは著しく高性能化される効果がある。[Effects of the Invention] As is clear from the above description, the present invention has the effect of increasing the speed of a bipolar semiconductor device and significantly improving the performance of an IC having such a structure.
第１図は本発明にかかるバイポーラ型半導体装置の構造
断面図、
第２図ｆａｌ〜（ｈ）は本発明にかかる半導体装置の形
成工程順断面図、
第３図は従来のバイポーラ型半導体装置の構造断面図で
ある。
図において、
１．１１はｎ型コレクタ領域、
２はｎ型ベース領域、
３．１４はｎ＋型エミッタ領域、
４，１５はフィールド酸化膜、
５．１７はベース電極、 ６，１８はエミッタ電極、
１２は単結晶半導体層からなるベース領域、１３は多結
晶半導体層からなるベース領域、１６はベースとコレク
タ間に介在させたＳ Ｌ Ｏ２膜、２１はＳｉ３Ｎ４膜
（保護マスク）、
２２は耐弗酸性マスク、
２３は５ｉ０２１！ｉｉを介在させたＳｉ３Ｎ４膜、２
４は新しい５ｉ０２膜
を示している。
第１図
第２図FIG. 1 is a cross-sectional view of the structure of a bipolar semiconductor device according to the present invention, FIGS. FIG. In the figure, 1.11 is an n-type collector region, 2 is an n-type base region, 3.14 is an n+ type emitter region, 4 and 15 are field oxide films, 5.17 is a base electrode, 6 and 18 are emitter electrodes,
12 is a base region made of a single crystal semiconductor layer, 13 is a base region made of a polycrystalline semiconductor layer, 16 is an S L O2 film interposed between the base and collector, 21 is a Si3N4 film (protective mask), and 22 is a fluorocarbon film. Acid mask, 23 is 5i021! Si3N4 film with ii interposed, 2
4 shows the new 5i02 membrane. Figure 1 Figure 2
Claims (2)
に設けられ、該単結晶半導体層を取り囲んだベース電極
を有する多結晶半導体層からなるベース領域が設けられ
、該多結晶半導体層からなるベース領域と単結晶半導体
層からなるコレクタ領域との間に絶縁膜が介在する構造
を具備してなることを特徴とする半導体装置。(1) A base region including an emitter region is provided in a single crystal semiconductor layer, a base region made of a polycrystalline semiconductor layer having a base electrode surrounding the single crystal semiconductor layer is provided, and a base region made of the polycrystalline semiconductor layer is provided. 1. A semiconductor device comprising a structure in which an insulating film is interposed between the region and a collector region made of a single crystal semiconductor layer.
保護マスクを被覆し、該エミッタ形成部周囲領域外の一
導電型単結晶半導体基板をエッチングして、前記保護マ
スクの下面をもサイドエッチングする工程、次いで、該
一導電型単結晶半導体基板の表面に二酸化シリコン膜を
形成した後、上面より耐弗酸性マスクを蒸着して被覆す
る工程、次いで、該耐弗酸性マスクを保護膜として、前
記保護マスクの下の単結晶半導体基板側面部分に露出し
た二酸化シリコン膜を弗酸でエッチング除去した後、前
記耐弗酸性マスクを除去する工程、次いで、多結晶半導
体膜を気相成長して前記保護マスクまで積層し、更に、
該多結晶半導体膜の表面を平坦化する工程、次いで、前
記保護マスクをマスクとして不純物を導入した後、前記
保護マスクを除去し、耐酸化性マスクを形成して、フィ
ールド酸化膜を生成する工程が含まれてなることを特徴
とする半導体装置の製造方法。(2) Covering the area surrounding the emitter formation part including the emitter formation part with a protective mask, etching the single conductivity type single crystal semiconductor substrate outside the area surrounding the emitter formation part, and also side-etching the lower surface of the protection mask. Next, after forming a silicon dioxide film on the surface of the one-conductivity type single crystal semiconductor substrate, a step of depositing a hydrofluoric acid-resistant mask from the upper surface to cover the substrate, using the hydrofluoric acid-resistant mask as a protective film, After removing the silicon dioxide film exposed on the side surface of the single-crystal semiconductor substrate under the protective mask by etching with hydrofluoric acid, the hydrofluoric acid-resistant mask is removed, and then a polycrystalline semiconductor film is vapor-phase grown to remove the protective layer. Laminated up to the mask, and furthermore,
a step of flattening the surface of the polycrystalline semiconductor film, then a step of introducing impurities using the protective mask as a mask, then removing the protective mask and forming an oxidation-resistant mask to generate a field oxide film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24674384A JPS61124175A (en) | 1984-11-20 | 1984-11-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24674384A JPS61124175A (en) | 1984-11-20 | 1984-11-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61124175A true JPS61124175A (en) | 1986-06-11 |
Family
ID=17152988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24674384A Pending JPS61124175A (en) | 1984-11-20 | 1984-11-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61124175A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198689A (en) * | 1988-11-30 | 1993-03-30 | Fujitsu Limited | Heterojunction bipolar transistor |
-
1984
- 1984-11-20 JP JP24674384A patent/JPS61124175A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198689A (en) * | 1988-11-30 | 1993-03-30 | Fujitsu Limited | Heterojunction bipolar transistor |
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