JPH01187864A - Transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a high speed bipolar transistor by forming a collector region, an emitter region and an outer base region having larger thickness than that of an inner base in a self-alignment manner. CONSTITUTION:A base 8 is formed by epitaxially growing in a self-alignment manner on collectors 2, 3. In order to form an emitter 11 in a self-alignment manner with the collectors 2, 3, a collector-base junction and an emitter-base junction are formed in a self-alignment manner substantially in the same area on the single crystalline part of the base, and since an external base region is formed substantially all on an insulating film 7, and the junction capacity of the collector-base becomes only the part of an inner base 8, thereby reducing an operation delay due to a parasitic capacity. A base leading electrode 6 having a large thickness and a low resistance is formed at a short distance from the region 8 and the emitter 11 in a self-alignment manner, the resistance of the outer base is reduced, thereby decreasing the operation delay due to the parasitic resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor suitable for high-speed operation and a method for manufacturing the same.

[Conventional technology]

Regarding bipolar transistors, for example, the Institute of Electrical Information and Communication Engineers Technical Research Report Vol. 87Na61p, 53-p.
, 58.

In this known example, an internal base and a base extension layer are formed by epitaxial growth on a collector separated by an insulating film, but the internal base and base extension layer have the same thickness. Furthermore, the emitter is not self-aligned with the collector, but is formed by mask alignment.

[Problem that the invention seeks to solve]

When scaling down the device, the above-mentioned conventional technology has the following problem in that it hinders speeding up.

(1) Since the collector region and emitter region are not self-aligned, the junction capacitance between the collector and the external base cannot be reduced, resulting in a delay in operating speed.

(2) Since the base lead-out electrode on the insulating film has the same thickness as the internal base region and is small, the external base resistance is large, which causes a delay in the operating speed.

(3) Since the emitter-base junction area is much smaller than the base-collector junction area, the transistor characteristics in the reverse direction are not good.

An object of the present invention is to solve the above-mentioned problems of the prior art and realize a higher speed bipolar transistor.

[Means for solving problems]

The above object is achieved by forming in self-alignment the collector region, the emitter region and the external base region, which has a thickness greater than that of the internal base.

The characteristics of the process to realize this technology are as follows.

That is, first, a low-resistance layer is formed on the collector region via a first insulating film, and then a hole is filled in the low-resistance layer.Then, the first insulating film is removed in self-alignment with the sidewall of the hole. to expose the collector layer.

Next, by vapor phase epitaxial growth, molecular beam epitaxial growth, or solid phase epitaxial growth of the deposited amorphous Si, single-crystal Si is grown from the collector layer and polycrystalline p-type Si is grown from other parts at the same time, thereby forming the first insulating film. The inner base, the outer base, and their connecting parts are formed by forming the interface on top. Next, an insulating film is formed only on the side walls of the hole, and an emitter made of an n-type single crystal layer is formed in the P-type single crystal Si exposed at the bottom of the hole by diffusion from the ion-implanted polycrystalline Si film.

[Effect]

(1) If the above-mentioned suspension is adopted, a base is formed by self-aligned growth on the collector,
And the single crystal part of its base.

Since the emitter is formed in a self-aligned manner with the collector, the collector base junction and emitter base junction can be formed in a self-aligned manner and in approximately the same area, and almost all of the external base region is formed on the insulating film. Therefore, the junction capacitance of the collector base is limited to only the internal base portion, and operational delays due to parasitic capacitance can be reduced.

(2) If the above method is adopted, a thick, low-resistance base extraction electrode can be formed in a self-aligned manner with a thin internal base region and a short distance from the emitter, so the external base resistance becomes small, and the operation due to parasitic resistance The delay can be reduced.

(3) If the above means is employed, the emitter-base junction area is reduced to 2 base-collector junction areas, so the reverse transistor characteristics are improved.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. 1 is a p-type Si substrate, 2 is an n-type diffusion layer, and 3 is an n-type epitaxial layer. 2 and 3 form a collector. 4 is an element isolation insulating film, and 5 is an insulating film on the collector. 6 is p-type polycrystalline Si which is the base extraction electrode, 7 is
This is an insulating film formed thereon. , 8 is a p-type single crystal layer serving as a base formed by vapor phase epitaxial growth or planar phase growth of deposited amorphous Si.

9 is a 5iOz film, 10 is an insulating film, 11 is an n-type single crystal layer forming an emitter formed by diffusion from polycrystalline Si doped with n-type impurities, 13 is an n + type polycrystalline Si film,
14 is a 5iOz film, and 15 is an emitter, base, and collector electrode. According to this embodiment, there are the effects shown in the section of the above-mentioned operation.

FIG. 2 shows a second embodiment of the invention. The first example of this example
The difference from the embodiment is that 1 is used as the base extraction electrode.
The point is that metal silicide No. 6 was introduced. According to this embodiment, there is an effect that the external base resistance can be further reduced compared to the first embodiment.

FIG. 3 shows a third embodiment of the present invention. The first example of this example. The difference from the second embodiment is that the n-type single crystal layer of the emitter is grown by vapor phase epitaxial growth, branch line epitaxial growth, or deposited amorphous S as shown in 17.
This is a point formed by in-phase growth of i.

According to this embodiment, the first. Compared to the second embodiment, this embodiment has the effect that the parasitic capacitance of the emitter-collector junction can be reduced.

FIG. 5(g) shows a fourth embodiment of the present invention.

This embodiment differs from the first to third embodiments in that the upper pole of the base drawer is formed in self-alignment with the collector. According to this embodiment, compared to the first to third embodiments, the collector area can be made smaller and the junction capacitance between the collector substrates can be made smaller.

Next, the manufacturing method of the first embodiment of the present invention is shown in FIG.
This will be explained using a) to (h). In these figures, the collector extraction part is omitted.

First, an N medium diffusion layer 2 is formed on a P-type Si substrate 1, and then an N-type epitaxial layer is formed. After that, element isolation insulating film 4
A collector region separated by 1 is formed. Next, a 5iOz film 5 (thickness: 1,500 mm) is formed on the collector region, and an impurity layer of 8 degrees 10" to 10"/d (
1) P-type polycrystalline Si film 6 (thickness: 3000), 5iO
A Z film 7 (thickness: 3,000 layers) and a 5laN film 18 (thickness: 1,400 layers) are formed (FIG. 4(a)).

Next, a hole reaching the upper surface of the insulating film 5 is formed in the collector region by conventional photolithography and anisotropic dry etching (FIG. 4(b)).

Next, the well-known Chemical Vapor Depos
5iaNa film (thickness 2
000 people) was deposited and anisotropic dry etching was performed to leave the 5isN4 film 19 only on the side wall of the hole (Fig. 4(C)).
).

Next, the 5iaNa film 19 and the insulator film 5 are selectively and alternately etched little by little by wet etching or isotropic dry etching, and when the collector Si is exposed, the 5iaNi film 18.19 is etched using hot phosphoric acid. completely remove. As a result, an opening with an inclined edge is formed on the collector in the insulating film 5 at the bottom of the hole (see Fig. 4).
d)).

Next, the substrate temperature was 650°C in a reduced pressure epitaxial furnace.
, the reaction gas S 1zHs+ R2H4 is irradiated with light (wavelength 2
A p-type epitaxial single crystal s, i8 (thickness: 500 nm) with an impurity concentration of lXl0"'/- is applied to the upper collector opening, and a p-type polycrystalline Si20 is applied to the other parts. Another method is to grow amorphous Si with a p-type impurity concentration of I x 10"D/cd at room temperature in a vacuum higher than 10-δTorr.
The same structure can also be formed by depositing by vapor deposition, annealing it at 600°C for 15 hours in a NZ atmosphere, and performing solid phase growth of amorphous Si from the collector opening or from the P-type polycrystalline Si6. (Figure 4(e)).

Next, regular Chamj, cal Vapor Dep
5isNa film 21 by position (CVD method)
After depositing 500 people.

A photoresist 22 is spin-coated, and the photoresist is etched back by anisotropic dry etching until the 5iaN4 film 21 is exposed.

Next, the portions of the 5iaN+ film 21 and polycrystalline Si 20 not covered by the resist 22 are etched away by isotropic dry etching. Next, the resist 22 is removed (FIG. 4(f)).

Next, annealing was performed for 70 minutes in an I atmosphere of 4 atm at SOO℃, and the polycrystalline 8
1 is oxidized to form a 5iOz film 23 with a thickness of 1000. Next, the S 1sN4 film 21 is removed by etching with hot phosphoric acid, and annealed for 30 minutes in an 820 atmosphere at 800'C and 4 atm. 24 is formed. Next, a 500 nm thick 5iaNa film is deposited by a conventional CVD method and removed by anisotropic dry etching, leaving only the side wall portion 10 of the hole. Next, the bottom of the hole is removed by anisotropic dry etching. selectively remove the SiO2 film (FIG. 4(g)).

Next, 1000 layers of polycrystalline Si were deposited by the usual CVD method, and annealed for 30 seconds at 1050°C by an instantaneous annealing method such as the 0-order infrared lamp annealing method in which As was ion-implanted to form an n-type monolayer. 6. To form the crystal layer 11, p-doped polycrystalline Si is deposited by the usual CVD method, and the polycrystalline Si film other than the upper part of the hole is removed by photolithography and dry etching (see FIG. 4). h)).

Next, Si is deposited on the polycrystalline Si film 13 by the usual CVD method.
G film 14 film type 4 0th order polycrystalline Si,6.

13, and SiO2 on the collector extraction diffusion layer part
The membrane is opened by photolithography and dry etching, and electrodes are formed thereon (FIG. 1).

This concludes the explanation of the manufacturing method of the first embodiment of the present invention.

In Fig. 4(n), p-type polycrystalline S with a thickness of 3000
Instead of forming the J film 6, a p-type polycrystalline Si film with a thickness of 2,000 layers is formed, and 1,000 layers of metal such as W, Mo, etc. are deposited thereon by vapor deposition or CVR method, and sintering is performed by heating. In some cases, metal silicide and p-type polycrystalline product S
A second embodiment of the present invention is manufactured by forming a two-layer film of i.

In FIG. 4(h), instead of forming an emitter by diffusion from the ion-implanted polycrystalline Si film,
``P concentration is 1 at room temperature at a vacuum higher than δTorr.
By depositing an amorphous Si film of xio"■-3 by 3000 people and annealing it for 15 hours at 600°C in a NZ atmosphere, the amorphous Si is grown in solid phase using the single crystal Si in the opening as a seed. The third embodiment of the present invention is manufactured by forming an emitter of n-type single crystal Si by vapor phase epitaxial growth.Instead of forming a single crystal Sj as an emitter, by plasma CVD method, Needless to say, an amorphous Si:H film or a film deposited on microcrystalline Si may be used.

Next, FIG. 5 (
This will be explained using a) to (g).

First, an N medium diffusion layer 2 is formed on a p-type Si substrate 1, and then an N-type epitaxial layer 3 is formed. Next, a 5ift film 4 (thickness: 1,000 yen) is formed on the epitaxial layer by thermal oxidation, and then a conventional CV r) method 1c and 4J Si
3Nt film 5 (thickness 1000) −, 5i02 film 6 (
7,000 people thick). Next, by photolithography and dry etching, S1. Ox film 6yS
The xaNa film 5, 5iOz film 4 is selectively etched away. Next, using the three-layer film left in the form of islands as a mask, wet etching and dry etching were carried out.
Etch away the epitaxial layer. Next, a Si◯2 film 29 (91,000 mm thick) is formed by thermal oxidation (FIG. 5(a)).

Next, 4J Si aNarItX by normal CVD method.
30 was deposited and anisotropic dry etching was performed to leave only the side walls of the step. Next, a field oxide film 31 with a thickness of 4,000 wafers is formed by thermal oxidation (FIG. 5(b)).

Next, polycrystalline Sin! is produced using the usual CVD method. 1iCJ'l
- 7,000 people) (Figure 5(c)).

Next, the polycrystalline Si film above the one step difference is selectively removed by etching, and then the SiOx film 2 is removed by wet etching.
8 is removed by etching (FIG. 5(d)).

Next, by thermal oxidation, the exposed portion of the polycrystalline 5i32 was
An SxOx film 33 having a thickness of 0.000 nm is then formed, and then the exposed portions of the 5isNa film 27 and the S, 1aNa film 29 are etched away using hot phosphoric acid (FIG. 5(e)).

Next, a 5iaN4 film 34 is deposited by the usual CVD method and anisotropically etched to leave the SjaN4 film only on the sidewalls of the step (FIG. 5(f)).

Next, (d) of FIG. 4 shown in the case of the first embodiment of the present invention.
) to (h), a fourth embodiment of the present invention shown in FIG. 5(g) is manufactured.

〔Effect of the invention〕

According to the present invention, since the junction between the external base and the collector becomes smaller, the capacitance between the base and the collector can be reduced to about 50% compared to the conventional technology with the same emitter size. Also, compared to the conventional technology, the external base region has a larger film thickness.

Furthermore, since it is formed in self-alignment with the emitter, the base resistance can be reduced to about 50%.

The minimum gate delay time of the ECL ring oscillator constructed using the bipolar transistor according to the present invention can be reduced to approximately 2/3 compared to the same emitter size according to the prior art.

According to the present invention, the fT, □ of the reverse direction operation of the transistor can be doubled compared to the conventional case where the base thickness is the same.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of a bipolar transistor according to a first embodiment of the present invention. FIGS. 2 and 3 are longitudinal cross-sectional views showing other embodiments of the present invention. FIG. 4 is a process diagram for explaining the manufacturing process of the first embodiment of the present invention. FIG. 5 is a process diagram for explaining the manufacturing process of still another embodiment of the present invention. 1...p-type Si substrate, 2...n-type east crystal Si, 3
... n-type Si epitaxial layer, 4. '5,7,9
゜10.14...Insulator film, 6...P medium polycrystalline S
i, 8...p-type single crystal Si, 11.17...n-type single crystal Si, 13-n+ type polycrystalline Si, 15...electrode, 16...metal silicide, 1.8, 19, 21...
・5iaN4TL screen, 20...p-type polycrystalline Si film, 2
2...Photoresist, 23,2:4...5iOz film, 26°29.31.33...Si,Oz film, 27
, 30° 34...Si3N4 film, 28-8 ioz
tl! 4.32-Polycrystalline Si film.

Claims (1)

[Claims] 1. An n-type buried layer formed on one main surface of a p-type Si substrate and an n-type buried layer formed on one main surface of a p-type Si substrate.
In a bipolar transistor having an insulating film having an opening on the upper surface of a collector layer formed of type epitaxial layers and electrically isolated from each other by an insulating film, the area above the opening is the same as the opening area or the opening is located above the opening. It has a p-type single-crystal Si layer overlapping on the insulating film further outside the outer periphery, and is thicker than the p-type single-crystal Si layer and is made of a material other than single-crystal Si, and is in contact with the p-type single-crystal Si layer region. It has a base extraction electrode located at a certain distance, and the p
The base lead-out electrode and the emitter are electrically isolated by an insulating film formed on the side wall of the step formed by the difference in thickness between the type single crystal Si layer and the base lead-out electrode. Characteristic bipolar transistor. 2. The n-type buried layer and the n-type buried layer formed on one main surface of the p-type Si substrate
A step of sequentially forming a first insulating film, a first conductor, and a second insulating film on a collector region made of a type epitaxial layer and electrically isolated from each other by an insulating film, and by photolithography and etching. A step of forming a recess reaching the upper surface of the collector layer in the collector region, and p-type single crystal Si is formed on the n-type epitaxial layer by vapor phase epitaxial growth, molecular beam epitaxial growth, or solid phase growth after amorphous Si deposition. a step of forming a p-type polycrystalline Si layer in a portion away from the n-type epitaxial layer; a step of selectively removing the p-type polycrystalline Si layer other than the inside of the recess; 1. A method of manufacturing a bipolar transistor, comprising the steps of: forming an insulating film on the bottom of the recess; and forming an n-type emitter layer in an opening at the bottom of the recess. 3. In the step of forming a recess in the three-layer film consisting of the first insulating film, the first conductor, and the second insulating film on the collector region, the first insulating film is formed by photolithography and anisotropic etching. forming a vertical hole reaching the top surface of the insulating film, then forming a third insulator on the side wall of the hole, and then forming a tapered opening in the first insulating film at the bottom of the hole;
3. The method of manufacturing a bipolar transistor according to claim 2, further comprising the step of selectively removing the third insulator.