JPS60117664A - Bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To produce the titled semiconductor device subject to high degree of integration and high speed operation making separation between elements and leading out electrode etc. entirely feasible utilizing a self alignment system by a method wherein a well is formed on a semiconductor substrate to produce an insulating film for separating elements, the first and the second interlayer insulating films. CONSTITUTION:A well 23 is formed in a field insulating film 22 and a silicon semiconductor substrate 21 and after forming another insulating film 24 for separating elements on the well 23 and then leaving the peripheral part of the well 23 only, a buried layer leading out conductive film 25, an n<++> type buried layer 26 are formed by etching process. Firstly an SiO2 film 29, the first Si3N4 interlayer insulating film 30A are formed and after removing a part of the buried layer leading out conductive film 25 on the bottom of the well 23 by etching process, an n type silicon semiconductor layer 31, a base leading out conductive film 32 and a p<+> type base region 33 are formed. Secondly another insulting SiO2 film 34, the second Si3N4 interlayer insulating film 35 and the other SiO2 film 36 are formed. Finally an emitter electrode 37E, a collector electrode 37C and a base electrode 37B are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a bipolar semiconductor device in which most of the main parts can be formed by applying a self-alignment method and which can be highly integrated.

Prior Art and Problems Generally, a bipolar semiconductor device as shown in FIG. 1 is known.

In the figure, 1 is an n-type silicon semiconductor substrate, 2 is an n-type buried layer, 3 is an epitaxially grown p-type silicon semiconductor layer, 4 is an insulating film made of silicon dioxide (SiO□), and 5 is a p-type base region. , 6 is an n++ type emitter region, an n+ type collector contact region, 8 is a p type isolation region, 9 is a collector electrode, 10 is a base electrode, 11
indicate emitter electrodes, respectively.

In such a bipolar semiconductor device, the collector contact region 7 or the element isolation region 8 is usually formed by impurity diffusion, and by the time it reaches the silicon semiconductor substrate 1, it has spread considerably in the lateral direction. It is necessary to allow a large margin for the area, and the pn between the element isolation region 8 and the silicon semiconductor layer 3
The junction capacitance also becomes large.

Furthermore, in order to form an electrode, it is necessary to form an electrode contact window in the insulating film 4 on the space region 5 or the emitter region 6, so the area of the region 5 or 6 must be large to some extent, and the emitter base This imposes restrictions on reducing the area of the bond.

FIG. 2 is a cross-sectional side view of a main part of a conventional bipolar semiconductor device having a configuration different from that shown in FIG. 1.

In the figure, a 12-ban or p-type silicon semiconductor substrate,
13 is an epitaxially grown n+ type silicon semiconductor layer, 1
4 is an epitaxially grown n-type silicon semiconductor layer, 15 is a p++ base region, 16 is an n++ emitter region, and 17 is an inter-element isolation film made of magnesia spinel (MgO.Al2O2).

To manufacture this conventional bipolar semiconductor device, a well is formed in the semiconductor substrate 12, an inter-element isolation film 17 made of magnesia spinel is formed on the wall surface of the well, and the inter-element isolation film 17 is made of magnesia spinel. An epitaxially grown n+ type silicon semiconductor layer 13 and an epitaxially grown n type silicon semiconductor layer 14 are deposited in the enclosed well, and a p++ base region 15 and an n+ type emitter region 1 are formed by diffusion into the epitaxially grown n type silicon semiconductor layer 14.
6 forming process is adopted. Therefore, similar to the bipolar semiconductor device described with reference to FIG. 1, there are restrictions on reducing the area of the emitter-base junction.

As described above, conventional bipolar semiconductor devices have many factors that hinder high integration and high speed.

Purpose of the Invention The present invention is capable of self-containing isolation between elements, electrode extraction, etc.
Provided is a semiconductor device that can be formed using an alignment method and can be highly integrated and run at high speed.

Structure of the Invention In the bipolar semiconductor device of the present invention, a single-current type semi-dedicated convex plate in which a well is formed, an insulating film for isolation between elements formed on the side periphery of the well, and a bottom portion of the well. The above-
a buried layer of an opposite conductivity type formed on a conductive semiconductor substrate; a conductive film extending from the buried layer connected to the periphery of the buried layer of the opposite conductivity type and drawn out through the insulating film for isolation between elements; a first interlayer insulating film covering the film; a semiconductor layer of an opposite conductivity type whose side periphery is surrounded by the first interlayer insulator in the well and formed adjacent to the buried layer of the opposite conductivity type; a base region of conductivity type formed on the surface of the semiconductor layer of opposite conductivity type; a base region extraction conductive film connected to the periphery of the conductivity type base region and drawn out through the first glabellar insulating crotch; A configuration comprising a second glabellar insulating film covering the film, and an emitter region of opposite conductivity type whose side periphery is surrounded by the second interlayer insulating film in the well and formed on the surface of the -conductivity type base region. Therefore, the self-alignment method 1~ can be applied to most of the areas near the wells where detailed buttering is required, and the areas that need to be buttered using a mask are naturally processed. Since it is not a part that requires extremely fine detail, it is a powerful technology for achieving high integration.

Embodiment of the Invention FIGS. 3 to 11 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention, and explanations will be given below with reference to these figures. .

See Figure 3 ■ Thermal oxidation method Acid or chemical vapor deposition method (CVD method: Chem
ical vapor deposition method) to deposit SjO□ on the surface of the p-type silicon semiconductor substrate 21.
The thickness of the field insulating film 22 is, for example, 3000 mm.
form to the extent of (a person).

Refer to Fig. 4. The field insulating film 22 and the silicon semiconductor substrate 21 are etched by applying photolithography technology and plasma etching technology or wet etching technology to, for example, a width of 6 [μITI] and a depth of 2 [μm].
] A well 23 is formed.

By applying the CVD method, an inter-element isolation insulating film 24 made of SiO□ is formed to a thickness of, for example, about 5000 (layers).

Refer to FIG. 5. 2) Applying a lithography ion etching method (RIE method), the insulating film 24 for isolation between elements is etched. Note that trifluoromethane (CHF3) is used as the etchant when etching SiO□ by the RIE method, and the same applies to subsequent steps.

At this time, the etching thickness is 5000 mm, so that the element isolation insulating film 24 on the field insulating film 22 and the element isolation insulating film 24 at the bottom of the well 23 are removed. However, the upper part of the element isolation insulating film 24 on the side periphery of the well 23 is slightly etched, and most of the rest remains.

By applying the CVD method, a buried layer extraction conductive film 25 made of polycrystalline silicon is formed to a thickness of, for example, about 5000 [layers].

Applying the ion implantation method, the acceleration energy: for example, 50 (K
Arsenic (As) ions are implanted under conditions of, for example, lXl01b(cn-'').

In a nitrogen (N2) atmosphere, temperature: e.g. 1000 [℃]
, time: For example, heat treatment is performed under the conditions of 1 [hour], and
=A mold buried layer 26 is formed, and the conductive film 25 made of polycrystalline silicon is made conductive.

Here, the buried layer of polycrystalline silicon is extracted from the conductive film 2.
5 is an insulating film 2 for element isolation except for the bottom surface of the well 23.
4, the impurity diffusion into the silicon semiconductor 7iHff121 does not spread in the lateral direction.

Refer to FIG. 6. The steps from this step to a part of step (2) are for removing only the portion of the buried layer extraction conductive film 25 located at the bottom of the well 23.

First, by applying the CVD method, silicon nitride (
A Si3N4) film 27 is formed to a thickness of, for example, about 1000 [people].

A resist film 28 is formed by applying a resist using a spin coating method.

Refer to FIG. 7. Applying the RIE method, etching is performed from the surface of the resist film 28, and a part of the resist film 28 and S ii
When a portion of the N4 film 27 is removed and the surface of the buried layer extraction electrode film 25 is exposed, etching is stopped. still,
02 was used as the etchant when etching the resist by the tE method, and CF was used as the etchant for Si and N, (95 (,%)) + 0□ (5 [%])
A mixed gas is used, and the same applies to the following steps.

As a result, the Si3N4 film 27 remains on the side periphery and bottom surface of the well 23.

The resist film 28 remaining in the well 23 is dissolved and removed, and the remaining Si3N film 27 is exposed.

Using the remaining 5i3Na film 27 as a mask, thermal oxidation is applied to the surface of the partially exposed buried layer extraction conductive film 25 to a thickness of, for example, about 3°00 [person].
An in2 film 29 is formed.

Applying the CVD method, a 5t3N film 3o is formed to a thickness of, for example, 10
00 (people).

This Si3N4 film 30 will be changed to the Si3N4 film 2 in a later process.
This is formed in order to protect the buried layer extraction conductive film 25 made of polycrystalline silicon from being exposed at the abutting portion between the Sing film 29 and the Sing film 29 .

Refer to FIG. 8. ② RIE method is applied to etch the Si, N, and film 30.

At this time, the etching thickness is approximately 1,000 mm, so that the surface of the SiO2 film 29 outside the well 23 is etched, and the 5t3N4 film 30 is etched around the side of the well 23.
However, at the bottom of the well 23, a portion of the buried layer-extracting conductive film 25 made of polycrystalline silicon is exposed.

Here, the remaining Si3N4 film 30 and the underlying Si3N4 film 27 are collectively represented by 30A, and will be referred to as a first interlayer insulating film.

By applying a wet etching method, a portion of the buried layer extraction conductive film 25 located at the bottom of the well 23 is etched, thereby exposing the silicon semiconductor substrate 21.

By applying a vapor phase epitaxial growth method, the n-type silicon semiconductor layer 31 is grown to a thickness of, for example, about 2 [μm].

Refer to FIG. 9. By applying the CVD method, a base drawing conductive film 32 made of polycrystalline silicon is grown to a thickness of, for example, about 5000 [layers].

By applying an ion implantation method, boron (B) ions are implanted, and then heat treatment is performed to form the p'-type hepatic region 33 and to make the base lead-out conductive film 32 conductive.

The base-extracting conductive film 32 is patterned by applying photolithography technology. In this patterning, for example, the left end in the figure is cut off, but this is to prevent it from colliding with the collector electrode, and such a part does not require great precision.

Refer to Figure 10 ■ This process is for removing only the portion of the base lead-out conductive film 32 that is located at the bottom of the well 23, and is basically the same as described in the previous paragraph ■. The process is exactly the same.

First, by applying the CVD method, a Si, N film, which will become a part of the second interlayer insulating film, is formed to a thickness of about 1.00 mm.

Applying a spin coating method, a resist is applied to form a resist film.

Applying the RIE method, etching is performed from the surface of the resist film to remove a part of the resist film and a part of the Si and N4 films that will become part of the second glabellar insulating film, and form a base drawing conductive film. Etching is stopped when a portion of the surface of 32 is selectively exposed.

As a result, Si, which becomes a part of the second interlayer insulating film,
The N4 film remains on the side periphery and bottom of the well 23.

The resist film remaining in the well 23 is dissolved and removed to form a portion of the remaining second interlayer insulating film.
Expose the i3N4 film.

A thermal oxidation method is applied using the remaining Si3N4 film serving as the second interlayer insulating film as a mask, and a thickness of, for example, 3
000 (person) SiO□ film 34 film type 4.

A CVD method is applied to form a Si3N film, which also becomes a part of the second interlayer insulating film, to a thickness of, for example, about 1000 [layers].

This Si3N4 film is composed of Si and N, which will become a part of the second eyebrow insulating film formed first in a later step.

This is formed to protect the base lead-out conductive film 32 made of polycrystalline silicon from being exposed in the area where the film and the SiO□ film 34 meet.

The RIE method is applied to etch the Si and N4 films.

At this time, the etching thickness is approximately 1,000 mm, so that the SiO□ film 2 is etched outside the well 23.
The surfaces of the wells 9 and 34 are covered with a Si, N film that will become a part of the second interlayer insulating film formed later on the side periphery of the well 23, and the drawn conductive film made of polycrystalline silicon is on the bottom of the well 23. 32 are each exposed.

Here, Si3N remains on the side periphery of the well.

The double layer of films will be collectively referred to as second interlayer insulation 11H5.

By applying a wet etching method, the surface of the p'' type base region 33 is exposed by etching the portion of the base-extracting conductive film 32 located on the bottom surface of the well 23.

By applying the CVD method, the p+ type base region i! 1
A total of 36 SiO□ films 36 are formed to form an insulating film a between i33 and an emitter region to be formed next.

Applying the RIE method, all 36 of the SiO□ films 36 are etched.

Due to this etching, the sin outside the well 23 is
, the surfaces of the films 29 and 34 are coated with Si on the side periphery of the well 23.
The surface of the p" type base region 33 is exposed on the bottom surface of the well 23, and the surface of the p" type base region 33 is exposed on the bottom surface of the well 23.

Patterning of S f Oz 8m29 and 34 is performed to form a collector electrode contact window and a base electrode contact window.

By applying the CVD method, the thickness, for example, 3000 ~
A polycrystalline silicon film of about 400° is grown.

Applying photolithography technology, the polycrystalline silicon film is patterned to form an emitter electrode 37E, a collector electrode 37c, and a base electrode 37B.

Refer to FIG. 11 (2) Applying the ion implantation method, As ions are implanted into the emitter electrode 37E and the collector electrode 37C, and B ions are implanted into the base electrode 37B, followed by heat treatment.

As a result, each electrode is rendered conductive, and an n'-type emitter region 38 is formed within the p'-type base region 33.

After this, standard techniques are applied to complete the process by forming metal electrodes, wiring, protective films, etc.

Effects of the Invention In the bipolar semiconductor device of the present invention, a semiconductor substrate of one conductivity type in which a well is formed, an insulating film for isolation between elements formed on the side periphery of the well, and the -
a buried layer of opposite conductivity type formed on a conductivity type semiconductor substrate; a buried layer extraction conductive film connected to the periphery of the opposite conductivity type buried layer and drawn out through the top of the element isolation insulator 11; and the buried layer extraction conductive layer. a first interlayer insulating film covering the film; a semiconductor layer of an opposite conductivity type whose side periphery is surrounded by the first interlayer insulator in the well and formed adjacent to the buried layer of the opposite conductivity type; A base region of conductivity type formed on the surface of the opposite conductivity type semiconductor layer; a base-extracting conductive film connected to the periphery of the conductivity-type base region and extended over the first interlayer insulating film; and the base-extracting conductive film. a second interlayer insulating film covering the well, and an opposite electric shock type emitter region whose side periphery is surrounded by the second interlayer insulating film in the well and formed on the surface of the - conductivity type base region. Since all elements such as isolation between elements and electrode extensions can be formed using a self-alignment method, it can be made significantly smaller than those manufactured using conventional technology, and is extremely advantageous for increasing density. be. Further, since element isolation can be achieved only with a thin insulating film, and element isolation does not depend on pn junctions, no junction capacitance occurs.

[Brief explanation of the drawing]

1 and 2 are cross-sectional side views of main parts of a bipolar semiconductor device according to the prior art, and FIGS. 3 to 1I are main parts of a semiconductor device at important process points for explaining an embodiment of the present invention. FIG. In the figure, 21 is a p-type silicon semiconductor substrate, 22 is a field insulating film, 23 is a well, 24 is an insulating film for isolation between elements, 25 is a buried layer extraction conductive film, 26 is an n'' type buried layer, and 27 is a Si.N4 film, 28 is a resist film, 29 is a SiO□ film, 30 is a Si3N4 film, 30A is a first interlayer insulating film, 31 is an n-type silicon semiconductor layer, 32 is a base drawing conductive film, 33
34 is a p4 type base region, 34 is a Si0g film, 35 is a second interlayer insulating film, 36 is a Sin film, 37B is an emitter electrode, 3'7C is a collector electrode, 37B is a base electrode, 38
is an n4'' type emitter region. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 3 Fig. 5 3 Fig. 6 Fig. 8 Fig. 7 Fig. 8 Fig. 9

Claims (1)

[Claims] a semiconductor substrate of one conductivity type in which a well is formed, an insulating film for isolation between elements formed on the side periphery of the well, and a buried layer of the opposite conductivity type formed in the -conductivity type semiconductor substrate at the bottom of the well; A buried layer drawing-out electric shock 1 model connected to the periphery of the buried layer of the opposite conductivity type and drawn out through the inter-element isolation insulating film, a first glabella insulating film covering the buried layer drawing-out conductive film, and a side periphery of the a thick body layer of opposite conductivity type surrounded by the first interlayer insulating film in the well and provided adjacent to the buried layer of opposite conductivity type; base area and the -
a base lead-out conductive film connected to the periphery of the conductive type base region and drawn out via the first glabellar insulating film; a second glabellar insulating film covering the base lead-out conductive film; 2. A bipolar semiconductor device comprising: an emitter region of an opposite conductivity type surrounded by a glabellar insulating film and formed on the surface of the base region of the − conductivity type.