JPS587862A - Bipolar transistor structure and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an extrinsic structure made by a double self-alignment process in which the base is self-aligned to an oxide window and the emitter is self-aligned to this base.
The present invention relates to an oxidized insulated bipolar transistor structure with a small polysilicon connected to the base contact area.

U.S. Pat. No. 4,157,269 discloses a method of manufacturing bipolar transistors using a single self-alignment process in which the emitter is self-aligned to the ancillary base contact. The polysilicon contacts connected to the ancillary base regions defined by the relative alignment of the two mask levels are much larger than the polysilicon contacts obtained by the present invention.

US Pat. No. 5,598,555 shows a fairly large base contact area gold-biased transistor structure and is relevant to the present invention in that the base contact includes an insulating layer thereon. The base contact is aluminum and the insulating layer is a thin film of aluminum oxide grown on the aluminum layer, which keeps the aluminum stable.

The present invention provides an improved bipolar transistor structure and an improved dual self-aligning manufacturing method for making such a structure.

FIG. 1 is a cross-sectional view of an embodiment of a bipolar transistor structure in accordance with the principles of the present invention.

The structure of FIG. 1, made by the described dual self-aligned manufacturing method, includes a recessed oxide insulating region 12 in a semiconductor substrate 10. A layer 14 of insulating material, such as silicon dioxide, extends over the edge of the recessed oxide insulating region 12 toward the center of the device area and includes a window opening for the emitter region. Insulating layer 14 extends to the edges of collateral base 16.

A layer of conductive contact material such as p+ polysilicon
'.18 is placed over the insulating layer 14 and extends vertically downwardly to extend over the edges of this insulating layer and contact the ancillary base 16. In practice, the ancillary base 16 is formed by driving donor impurities from the polysilicon layer 18, so that the polysilicon layer 18 need only consist of an electrically conductive material, which is distributed throughout this layer 1B. Rather than being doped with , it only needs to be doped in the region 52kp+ above the ancillary base region. A second insulating layer 20, such as a combination of silicon dioxide 20-1 and aluminum dioxide 20-2, is overlaid and extends over the inner edge of the polysilicon layer or base contact layer 18 and defines the emitter region thereof. Substrate 1 so as to insulate it from the paste contact layer.
Extends perpendicularly downward to the surface of 0. Alternatively, layer 20 may consist entirely of one suitable insulating material.

The remaining elements of the bipolar device include an emitter 22, an intrinsic base 24, an n-epi luminescent collector 2n+ subcollector 28, and an emitter contact 5Qfc consisting of, for example, n+ polysilicon.

It can be seen that the base contact area is a very small area, less than 1 micron in size, and is located between insulating layer 14 and insulating layer 20, which insulates space contact layer 18 from emitter contact 50. The reduced area of ancillary base 16 reduces parasitic capacitance and results in faster operation and higher packing density for integrated circuits. or,
As a result of the fabrication method described below, the ancillary base is self-aligned to the vertical edges of the oxide insulating layer 14, and the emitter is self-aligned to this ancillary base.

The method for making the bipolar device shown in Figure 1 is 1.
Figure 2-1, Figure 2-2, Figure 2-6, Figure 2-4, Figure 2
This is shown in Figure-5 and Figure 2-6.

The key feature of this method is to first use an oxidation step to define a self-aligning rim of conductive material that acts as a base contact, and then to provide an oxide-insulated emitter. By using this conductive rim.

More specifically, in FIG. 2-1, an insulating layer 14 (i.e., silicon dioxide) is deposited on a silicon substrate 10, which substrate has a recessed oxide insulating region 12, e.
It has a pi lumin collector 2 and an n+ sub collector 28, which are placed on this substrate by conventional techniques. Conductive materials (Sunawa+, Chi, P Polysilicon, Polycide
A base contact layer 18 of metal or refractory metal) is deposited on top of the insulating layer 14, and a second insulating layer 2° is deposited on top of this base contact 18. Insulating layer 20 must have the properties of being a good reactive ion etch (RIE) mask for polysilicon and a good mask for silicon oxidation. Aluminum oxide (At203) or silicon dioxide (Si
O2) is a suitable material for the insulating layer 2°. However, other materials or combinations of materials can also be used.

Next, holes or windows are etched into the insulating layer 2o (i.e. using H3po4 with respect to At203) and into the base contact layer 18 and then a portion of the insulating layer 14 is etched using a reactive ion etching process. to be etched. Next, insulating layer 1
The remainder of 4 is etched by a chemically reactive etching process so that a portion of this insulating layer 14 is undercut to provide the structure shown in FIG. 2-1. Chemically reactive etching to provide an undercut is optional and the structure may be made without such an undercut.

A p+ deposit 9 layer 52 is then deposited over the structure of FIG. 2-1 as shown in FIG. 2-2.

Due to the conformal nature of the deposition, the polysilicon layer '52 also deposits in the undercut areas. That is, this polysilicon layer forms a protective bridge connecting the first base contact layer 18 to the substrate 10.

The polysilicon layer '52 removes the polysilicon from the exposed horizontal surfaces and removes the polysilicon from the aluminum dioxide layer 20-2.
is etched using a reactive ion etching process to partially remove the polysilicon from the sidewalls of the base contact layer 18, leaving a vertical connection bridge from the base contact layer 18 to the substrate 10 as shown in Figures 2-3. .

In the next step, the exposed silicon substrate 1° and some residual polysilicon on the polysilicon 32 and the sidewalls of the aluminum dioxide layer 20-2 are removed to form a layer 54 as shown in FIG. 2-4. oxidized to During this step, impurities, such as boron, are driven from the remaining p+ polysilicon sidewall residue of polysilicon layer 32 into substrate 10, thereby creating an additional base region as shown in FIGS. 2-4. 16 is formed. If necessary, additional tempering treatments can be applied to drive the boron deeper.

Additional silicon dioxide 56 is chemically vapor deposited over the structure to thicken the oxide layer 54, as shown in FIGS. 2-5.

The horizontal portions of silicon dioxide layers 34 and 36 are removed by a directional reactive ion etching process, leaving silicon dioxide sidewalls 20-1 on the sidewalls of polysilicon layer 52. That is, this process leaves the emitter region of the substrate 10 exposed.

It is important to note that the polysilicon base contact 52 and ancillary base 16 are self-aligned to the window formed by the silicon dioxide sidewall 20-1.

The window acts as an aperture for the emitter and thus the emitter is self-aligned with the ancillary base 16 as shown in FIGS. 2-6.

The remaining steps in the device fabrication method consist of conventional steps. Substantive base 24 is formed by diffusing or implanting boron through the window formed by oxide sidewall 20-1, and n+ emitter 22 is implanted (ie, arsenic).

Next, an n+ polysilicon emitter contact 30 is formed by depositing, masking, and etching a layer of arsenic-doped polysilicon to form the structure shown in FIG. Alternatively, emitter contact 30 can also be formed using metallization techniques. It is recognized in the art that the base may be implanted before the emitter is formed, or the emitter may be implanted before the base is formed.

The manufacturing method described above with respect to FIGS. 2-1, 2-2, 2-5, 2-4, 2-5, and 2-6 and the manufacturing method formed by this manufacturing method. The structure in Figure 1 is npn
Provide mold equipment. However, using materials of opposite conductivity, a pnp type device having a p+ doped emitter, an n+ doped concomitant space, and a p type collector can be provided following the same manufacturing process.

A unique bipolar transistor device has been described having a structure in which a layer of insulating material extends over the device substrate to a collateral base around the emitter region. A very small area conductive base contact is provided to the ancillary base and a protective sidewall of insulating material is placed over the base contact to space it from the emitter contact. This unique structure can be made by a manufacturing method that incorporates a dual self-alignment technique.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing a bipolar transistor structure according to the principle of this explanation, Fig. 2-1, Fig. 2-2, Fig. 2-5, Fig. 2-4, Fig. 2-5. and FIGS. 2-6 are cross-sectional views illustrating a bipolar transistor structure at selected steps of the dual self-aligned manufacturing method according to the present invention. 10... Board, 26... Collector, 2B...
・Sub-collector, 12... Oxide insulation region, 16.
...incidental base, 24...substantive base, 14
．． 20... Insulating layer, 18... Polysilicon layer,
22...Emitter, 30...Emitter contact. Applicant International Business Machines Corporation Representative Patent Attorney Yamamoto
Jinro (1 other person)

Claims (1)

Claims: A bipolar transistor structure comprising a substrate of a semiconductor material, comprising a region of electrically insulating material recessed into the substrate and surrounding a central device region of the substrate; a transistor subcollector region disposed within the substrate in the enclosed central device region; and a first electrically insulating material disposed over a surface of the substrate and a recess in the electrically insulating material region. a transistor base in the substrate in the central device region above the sub-collector region, the transistor base having an aperture above the central device region; an additional base region extending below the edges of the first insulating layer and surrounding the central substantially base region; having a predetermined thickness and overlying the first insulating layer;
A layer of electrically conductive material extending downwardly along the edges and sidewalls of the aperture of the first insulating layer and contacting the ancillary base region of the substrate to form a base contact region. a layer of conductive material having a thickness substantially equal to the width of the contact region and extending downwardly along edges and sidewalls of the layer of conductive material and extending downwardly along the edges and sidewalls of the layer of conductive material; a second layer of insulating material in contact with the surface, overlying the substrate and in the central device region above the substantially base region and within the sidewalls of the second insulating layer; an emitter electrically isolated from the base contact region by sidewalls of an insulating layer; and an emitter overlying the emitter and electrically insulated from the layer of conductive base contact material by sidewalls of the second insulating layer. A bipolar transistor structure consisting of an emitter contact of a conductive material, and