JPS61220463A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a bipolar transistor, whose characteristics are determined by only an intrinsic base, by noting the fact that the performance is deteriorated by the extension of a graft base for taking out a base electrode into collector and emitter regions, and limiting the graft base by an insulator. CONSTITUTION:An N<+> type sub-collector region 2 is diffused and formed in the surface layer part of a P-type Si substrate 1. An N<-> type active collector layer 3 is epitaxially grown on the region 2. The outside of the layer 3 is surrounded by an insulator 8. The layer 3 is divided by the same insulator 8. One is used for the active region of a transistor, and the other is used for a collector taking out region. A P-type base region 4, which is larger than the area of the layer 3 is provided on the layer 3 in the active region. A graft base region 6 and an outer base 7, which is linked to the region 6, are formed on the insulator 8 around the region 4. An N<+> type emitter region 5 having the same area as the region 3 is formed on the region 5 and surrounded by an insulator film 9. Thus contact of the graft base 6 and the regions 3 and 5 is positively prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a bipolar transistor and a method for manufacturing the same, and more particularly to a minute bipolar transistor for integrated circuits having high-speed operation performance and a method for manufacturing the same. .

[Background of the invention]

In order to reduce the parasitic capacitance of bipolar transistors for LSI and enable high-speed operation,
As shown in Japanese Patent No. 6961, there is a known method of burying an insulator in the parasitic region between the base and the N'' buried layer for the collector.However, in the conventional method, the active collector in the epitaxial region No consideration was given to problems such as deterioration of the withstand voltage between the pace and the collector, reduction of operating speed, current gain, etc. due to the formation of a diffusion layer for taking out the pace electrode around the layer.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar transistor that eliminates the above drawbacks and has improved performance such as high speed and high breakdown voltage, and a method for manufacturing the same.

[Summary of the invention]

In order to achieve the above object, the present invention focuses on the fact that performance deterioration occurs when a diffusion layer (graft paste) for taking out a pace electrode extends into the collector or emitter region. By limiting this, a bipolar transistor whose characteristics are determined only by the intrinsic pace is constructed.

[Embodiments of the invention]

The present invention will be explained below using examples.

FIG. 1 schematically shows the cross-sectional structure of a bipolar transistor showing an embodiment of the present invention. This structure consists of an N buried layer 2 as a sub-collector formed on a P-type 3i substrate 1, and an N buried layer 2 formed on an epitaxial growth layer.
- It basically consists of an active collector layer 3, a base layer 4, and an emitter layer 5. The widths of the emitter layer 5 and the active collector layer 30 are approximately equal to ti, and the width of the base layer 4 is even larger. The pace is also connected to the external base 7 via a graft pace 6t'' provided around the pace.

(Various low resistance wiring materials such as polycrystalline 8i+W8i snow can be used for the external space.) An insulating film 8.9 is provided around the active collector 3 and emitter 5 to reduce parasitic capacitance. (It is preferable to use 5jOs for the insulating film.) In this structure, in particular, the insulating film is made so that the thickness of the graft paste 6 approaches the thickness of the paste 4, and contact between the graft paste and the emitter and collector is avoided. The feature is that it is provided. This has caused problems in the past, such as deterioration of junction breakdown voltage due to contact between graft paste and emitter or N0 buried layer, and degradation of characteristics around the original transistor due to graft paste protruding into the active collector layer. It is possible to eliminate the drawbacks such as the formation of bad (thick base layer) parasitic transistors that reduce current gain and operation speed. That is, the present structure is a one-dimensional vertical NPN transistor determined by the emitter dimension, and is a bipolar transistor suitable for high-speed operation, in which parasitic capacitance and parasitic transistors have been eliminated.

In this embodiment, an NPN transistor has been described, but the same applies to a PNP transistor.

Furthermore, it is also possible to remove the junction formed between the N9 buried layer of the subcollector and the substrate by inserting an insulating film.

Next, a manufacturing method for realizing the above structure will be described.

FIG. 2 is a process diagram showing the manufacturing method of this example. P-type Si substrate 1, N9 buried layer 2 and N-epitaxial layer 1
A pattern consisting of a thin pad 5iottx, S is Na 12 as an oxidation-resistant film, and 5i (h film 13) is formed on the substrate on which S 1sNt 12 is formed, and the S 1sNt 12 is side-etched to form a pattern as shown in FIG. 2 (1). Obtain the cross-sectional structure shown in .

For side etching of 871N4, wet etching using a phosphoric acid solution or plasma etching using 7 Leon gas can be used.

Subsequently, a wall 8iCh14 is formed by thermal oxidation as shown in FIG. Here, S i f:l! is exposed before thermal oxidation. <If etched, a flat wall 8i0114 can be obtained. In addition, this wall 8! The region surrounded by Os is the region that will later become an emitter, and the bottom of the wall 8102 is preferably at the same depth as the depth at which the emitter is formed.

Next, use 8i0s13 as a mask to create a wall of SiO snow.
14. The epitaxial layer 10'i is anisotropically etched using a reactive sputter etching method using Freon gas, etc.
The shape shown in Figure 2 (8) is obtained. Subsequently, after depositing SjsNA, the sidewall 8jsNa15 shown in FIG. Form. Furthermore, after the exposed Si surface is isotropically etched and lightly oxidized to form an 8i0 layer 16 that determines the depth of the graft base, the second sidewall 81sNa is deposited by 513N4 deposition and anisotropically etched. form 17.

Embedded SiO*18t- is formed by thermal oxidation, and the side wall 8j
Removal of sN4 exposes the side surface 19 forming the graft base, as shown in FIG. 2(5).

Next, by depositing and planarizing polycrystalline Si,
As shown in FIG. 2(6), a structure is completed in which the base electrode is taken out using polycrystalline f3 i 20. Here, the graft base 21 is formed by diffusion of B from the polycrystalline f3i, and the intrinsic base 22 and emitter 23 are formed from the surface by B%A! ! It is formed by K such as ion implantation or diffusion.

In the bipolar transistor obtained as described above, the graft base region is controlled with high precision by the wall 5iCh 14 and the buried SiO 18, and problems such as breakdown voltage deterioration do not occur when the electrode is taken out from the side wall. Therefore, according to the above manufacturing method, a miniature bipolar transistor with excellent high-speed performance etc. can be realized with high precision.

In addition, in the above process, when forming the embedded 8iCh thickly, it is preferable to use the following manufacturing method in order to prevent crystal defects from occurring due to stress during oxidation.

In Figure 3, a thick buried oxide film is provided using 5iOt24 formed by deposition.
6 is thin. In addition, in FIG. 4, the second SisN4 side wall 17
The embedded SiO
A thick 8f (h) is prevented from being formed at the end of the 25. By thinning the thermal oxide film formed under the graft base region as shown above, crystal defects can be suppressed. It is also effective to prevent defects by providing a thin 5fOs layer 26 as shown in FIG. 4 so that the silicon and silicon do not come into contact with each other.

〔Effect of the invention〕

As described above, according to the present invention, the graft base region can be processed with high precision, and the graft base does not extend over the emitter region or collector region, so that the breakdown voltage between the base, emitter, and collector can be improved. In addition, graft
Since the parasitic transistor formed by the base can be eliminated, a transistor with high speed operation and excellent current gain can be obtained.

Since small-area bipolar transistors can be formed with high precision, large-scale integrated circuits can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the cross-sectional structure of a bipolar transistor of the present invention, and FIGS. 2, 3, and 4 are process diagrams showing the manufacturing method of the present invention. 1...Si substrate, 2...N4'' buried layer, 3.10
...active collector layer, 4.22...intrinsic base layer,
5゜23... Emitter layer, 6.21... Graft.
Base, 9.14...Wall SiO Tomi, 8,18,
24゜茗 2 Figure 2

Claims (1)

[Scope of Claims] 1. An emitter region of a second conductivity, a base region of a first conductivity type, and a second conductivity type formed sequentially from the surface side in an epitaxial region provided on a semiconductor substrate of a first conductivity type. In a bipolar transistor having a collector region, a first conductivity graft base region surrounding the base region and an insulating layer surrounding the emitter and collector regions extending inward from the graft base region are provided. A bipolar transistor characterized by 2. A method for manufacturing a bipolar transistor, characterized in that an oxide film surrounding an emitter region is provided in a region formed by side etching an oxidation-resistant film patterned on a semiconductor substrate. 3. After forming an island-like region having a substantially perpendicular sidewall on the semiconductor substrate, the sidewall of the island-like region is coated with an oxidation-resistant film, and the semiconductor substrate below the sidewall is lightly etched to form a graft. - A method for manufacturing a bipolar transistor characterized by forming a buried oxide film under a region where a base is to be formed.