JPH03185838A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve surface flatness by patterning a semiconductor film so as to leave the domain ranging from an emitter forming region to a collector leading-out region, patterning a semiconductor film together with an insulating film formed on the whole surface so as to be isolated on the insulating film, and forming an emitter leading-out electrode and a collector leading-out electrode. CONSTITUTION:A semiconductor film 8, which is formed on the whole surface of an aperture 54 and an insulating film 7 and contains first conductivity type impurities, is so patterned that the domain ranging from an emitter forming part to a collector leading-out region 32 is left. As a result, only the semiconductor film 8 is etched and eliminated by the effect of selection ratio of the semiconductor film 8 and the insulating film 7. After that, a second insulating film 10 is stuck, and the semiconductor film 8 is again patterned together with the second insulating film 10 so as to be isolated on the insulating film 7,. thereby forming an emitter leading-out electrode 36 and a collector leading-out electrode 35 of the semiconductor film 8. Hence the surface containing a field insulating layer 6 between the emitter leading-out electrode 36 and the collector leading-out electrode 35 is free of level-difference and flat.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices, particularly high performance bipolar transistors.

[Summary of the invention]

The present invention provides a method for manufacturing a high-performance bipolar transistor, in which a collector extraction region of a first conductivity type is formed on the outside partitioned by a field isolation 8i layer, and a semiconductor region of a second conductivity type is formed on the inside. An insulating film having an opening at a position corresponding to the collector extraction region and the emitter formation part of the semiconductor region is formed, a semiconductor film containing a first conductivity type impurity is formed thereon, and this semiconductor film is connected from the emitter formation part to the collector formation part. By patterning so as to leave a range covering the extraction region, and then patterning the semiconductor film together with the insulating film formed on the entire surface so as to separate the semiconductor film at the insulation crotch to form an emitter extraction electrode and a collector extraction electrode, It is designed to improve surface flatness and achieve high reliability and high yield.

The present invention also provides a method for manufacturing a high-performance bipolar transistor, in which a collector lead-out region of a first conductivity type is formed on the outside separated by a field insulating layer, and a semiconductor region of a second conductivity type is formed on the inside. An insulating film having openings at positions corresponding to the collector extraction region and the emitter formation portion of the semiconductor region is formed, a semiconductor film containing impurities of the first conductivity type is formed thereon, and this semiconductor film is placed over the field insulating film. By patterning the semiconductor film so as to separate it from the field insulating layer to form a collector lead-out electrode, and further patterning the semiconductor film along with the insulating film formed on the entire surface so that a portion remains on the field insulating layer to form an emitter lead-out electrode. , the surface flatness has been improved to achieve high reliability and high yield.

[Conventional technology]

Conventionally, in a bipolar transistor, a base extraction electrode and an emitter extraction electrode are formed of a polycrystalline silicon film, and a base region and an emitter N region are formed in a self-aligned manner by impurity diffusion from the polycrystalline silicon film for emitter extraction. Ultrafast bipolar transistors have been proposed.

FIG. 8 shows an example of a method for manufacturing this ultra-high speed bipolar transistor. As shown in FIG. 8A, a collector buried region (2) of a second conductivity type, that is, an n-type, and a P-type channel stop region (3) are formed on the main surface of a silicon substrate (1) of a first conductivity type, for example, a p-type. After forming the n-type epitaxial M(4)
grow. A high concentration n-type collector extraction region (5) reaching the collector buried region (2) is formed, and the regions (4^) where the collector extraction region (5) and the base region and emitter region are to be formed are then selected. A field insulating layer (6) is formed by oxidation. Next, a thin insulating film, for example, a 5if2 film (7), is formed on the entire surface, and after opening a portion corresponding to the region (4A), CVD (chemical vapor deposition) is performed.
A first polycrystalline silicon film (8) that will become a base extraction electrode is formed by a method, and this polycrystalline silicon film (8) is doped with boron as a p-type impurity. Thereafter, the polycrystalline silicon film 8) is patterned through the first resist mask (9) having a pattern corresponding to the external shape of the base lead-out electrode.

Next, p3 polycrystalline silicon Jl! is patterned as shown in FIG. 8B. After a SiOg film (10) is deposited on the entire surface including (8) by CVD, a second resist mask (11) is formed. Then, through this resist mask (11), a Si0g film (10) is deposited on a portion corresponding to the active region where the intrinsic base region and emitter region are to be formed.
and p゛polycrystalline silicon l! (8) is selectively etched away to form an opening (13), and P'polycrystalline silicon I! (8) Base extraction electrode (1
2) Form.

Next, as shown in FIG. 8C, p-type impurity boron is ion-implanted through this opening (13) to connect the external base region to be formed later on the surface of the region (4A) and the intrinsic base region. A link base area (14) is formed.

Next, after depositing a SiO□ film by CVD method, 9
The film is densified by CVD 5 inches by heat treatment at about 00°C. During this heat treatment, a part of the external base region (16) is formed by boron diffusion from the base lead-out electrode (12) of the P1 polycrystalline silicon film. After that, the base extraction electrode (1) is etched back and faces the opening (13).
2) A sidewall (15) made of 5iO7 is formed on the inner wall of the sample.

Next, as shown in Figure 8, a second polycrystalline silicon film (18), which will eventually become an emitter extraction electrode, is formed in the opening (17) regulated by the sidewall (15) by the CVD method. A p-type impurity (e.g., B or BFz) is ion-implanted into the crystalline silicon film (18) and annealed to form a p-type intrinsic base region (19) in the active region, and then an n-type impurity (e.g., arsenic) is ion-implanted. Then, the polycrystalline silicon film (18) is ion-implanted with p-type impurities and n-type impurities, and then annealed at the same time to form an n-shaped emitter region (20). and an n-carved ξ ivy region (20). During the annealing process during the base and emitter formation, at the same time boron is diffused from the base lead-out electrode (12) of p゛゛crystalline silicon, and finally the external base region (16) is formed. is formed.In addition,
The intrinsic base region (19) has a higher impurity concentration than the link base region (14). After that, a contact hole is formed and a base electrode (21
), a collector electrode (22) and an emitter electrode (23) are formed. In this way, an ultra-high speed npn bipolar transistor (24) is constructed.

[Problem to be solved by the invention]

Incidentally, in a semiconductor integrated circuit, it is possible to realize a high-performance pnp bipolar transistor as shown in FIG. 9 by using the method for manufacturing the ultra-high speed npn bipolar transistor (24) described above. That is, as shown in FIG. 9A, after a p-type channel stop region (3) is formed on the -main surface of a p-type silicon substrate (1), an n-type epitaxial layer (4) is grown. A field insulating layer (6) is formed by selective oxidation except for the region (4B) where the collector extraction region, base region and emitter region are to be formed. Next, after forming a thin insulating film, that is, a Si0g film (7) on the entire surface, a resist mask <33> is formed to cover the region (4B), and boron ions as a p-type impurity are ion-implanted to take out the p-type collector. A region (32) is formed. This P-type current extraction region (32) is formed simultaneously with the substrate potential extraction region on the npn bipolar transistor side.

Next, as shown in FIG. 9B, after opening the Si0g film (7) in the part corresponding to the emitter formation part and the collector extraction region (32) of the region (4B), the first
A polycrystalline silicon film (8) is formed, and this polycrystalline silicon film (8) is doped with boron as a p-type impurity.

Then, a resist mask (34) is selectively formed on the P polycrystalline silicon film 8) in the portion corresponding to the region (4B) and the collector extraction region (32).

Next, as shown in FIG. 9C, this resist mask (3
4) The P polycrystalline silicon film 8) is patterned so as to be separated at the position of the field insulating layer (6) through the collector extraction region (32), the emitter formation part, and the base extraction region formation part. A p'polycrystalline silicon film 8) is left on the region. P on the collector extraction area (32)
1. The polycrystalline silicon film becomes the collector lead-out electrode (35). After that, the entire surface is coated with a Sin film (10
), a resist mask (11) having an opening in a portion corresponding to the base extraction region is formed.

Next, as shown in Figure 9, selective etching is performed using RIE (reactive ion etching) through a resist mask (11) to form a window hole through which the base extraction region formation portion faces. At this time, a portion of the p+ polycrystalline silicon peritoneum 8) is also selectively removed to form the final emitter extraction electrode (36).

Thereafter, a Si0g film (37) is deposited by CVD (see Figure 1C) and annealed, a sidewall (15) is formed by RIE, and then a second polycrystalline silicon film (18) is formed. Adhesive formation. And npn
) Simultaneously with the formation of the transistor emitter, an n° base extraction region (38) is formed by impurity diffusion from the second polycrystalline silicon film, that is, the n° polycrystalline silicon removed film 18). Also p
++ A p carved ξ ivy region (39) is formed by impurity diffusion from the emitter extraction electrode (36) of crystalline silicon.

Next, the n9 polycrystalline silicon film (18) is patterned to form the base lead-out electrode (40).
After forming the emitter extraction electrode (18) of the pn transistor at the same time), a contact hole is formed and an emitter electrode (41), a base electrode (42) and a collector electrode (43) are formed using metal (for example, AI). In this way, together with the npn bipolar transistor (24), a high performance pnp transistor (44) is constructed.

However, in the steps from FIG. 9C to FIG. 9 described above, a stepped portion (46) is generated. That is, as shown in the enlarged view of FIG.
FIG. 10A (same process as FIG. 9C)), in order to expose the base extraction region forming part, first 5
By selectively etching the iOJ layer (10) and then selectively etching the polycrystalline silicon film (8) (usually this etching is done just before over-etching), the field insulating layer (6) is etched as shown in FIG. 10B. A part of the SiO□ is etched to form a recess (47).
A sidewall (10a) made of the film (10) and a sidewall (8a) made of polycrystalline silicon JfI (8) are formed. Furthermore, as shown in FIG. 10C, a SiO2 film (37) is formed, and the sidewall (1) shown in FIG.
5) RI on the SiO2 film (37) to form
When E is applied, the sidewall (
10a) and (8a), a 5i02 film (37
) sidewalls (37a) overlap, resulting in 5
A stepped portion (46) is formed by the ioJ#, polycrystalline silicon residue (48), a partial recess (47) of the field insulating layer (6), and the like. Therefore, in the subsequent AZ process, A
t remains on this stepped portion (46), causing a short circuit between the electrodes, or AI, residue (48), etc. peeling off and causing dust, reducing reliability and adversely affecting manufacturing yield. There was a possibility.

In view of the above-mentioned points, the present invention provides a method for manufacturing a semiconductor device, that is, a high-performance bipolar transistor, which can be manufactured with high reliability and high yield.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes a field insulating layer (
A collector extraction region (32) of the first conductivity type is formed on the outside partitioned by 6), and a collector extraction region (32) of the second conductivity type is formed on the inside thereof. Step of forming a first insulating film (7) having openings (54) and (53) at positions corresponding to the emitter formation portion of the semiconductor region (4B), openings (54>(53) and insulating film (7) A step of forming a semiconductor film (8) containing impurities of the first conductivity type on the entire surface of the semiconductor film (8) containing impurities of the first conductivity type is coated with butter so as to leave a region extending from the emitter formation region to the collector extraction region. a step of forming a second insulating film (10) on the entire surface including the semiconductor film (8); The straw ivy extraction electrode (36) is separated on the insulating film (7) of No.
) and a step of forming a collector lead-out electrode (35).

In another method for manufacturing a semiconductor device according to the present invention, a collector extraction region (32) of the first conductivity type is formed on the outside partitioned by the field insulating layer (6), and a semiconductor region (4B) of the second conductivity type is formed on the inside. ), forming an insulating film 0) having openings (54) and (53) at positions corresponding to the emitter formation portion of the collector extraction region (32) and the semiconductor region (32>), on the substrate surface on which the opening ( 54) A step of forming a semiconductor film (8) containing impurities of the first conductivity type on the entire surface of (53) and the insulating film (7). 6) A step of forming a collector lead-out electrode (35) by patterning the top so as to separate the second insulating film (
10), the first conductivity type impurity-containing semiconductor film (8) is patterned together with the second insulating film (10) so that a portion (8x) remains on the field insulation N (6). This includes a step of forming an emitter extraction electrode (36).

[Effect]

In the first invention described above, the opening (54) (53)
The semiconductor film (8) containing impurities of the first conductivity type formed on the entire surface of the insulating film (7) is first patterned so that a region extending from the emitter formation part to the collector extraction region (32) remains. Only the semiconductor film (8) is etched away with the selectivity between the film (8) and the underlying first insulating film (7). After that, a second insulating film (10) is deposited, and the second insulating film (10) and the semiconductor film (8) are patterned again so as to be separated on the insulating film (7) to form a semiconductor film. (8), the surface including the field insulating layer (6) between the emitter extraction electrode (36) and the collector extraction electrode (35) has a step. There will be no flat surface. That is, as shown in Figure 10, no recesses (47) or residues (48) in the field insulating layer (6) are formed, and the level difference on the surface is reduced as a whole. Therefore, from now on, the base extraction area (38) will be shaped and the metal electrode (61) (
62) Even when (63) is formed, there is no metal residue on the emitter lead-out electrode (36) and collector lead-out electrode (35) that could cause a short circuit between the electrodes, or peeling of metal or residue, etc. High-performance semiconductor devices can be manufactured with high yield.

In the second invention described above, the opening (54) (53)
and a semiconductor film (8) containing impurities of the first conductivity type formed over the entire surface of the first insulating film (7).
) to form the collector lead-out electrode (35), and then deposit the second insulating film (10) to form the semiconductor film (8) together with the second insulating film (10). ,
Since the emitter extraction electrode (36) is formed by patterning so that a portion (8x) remains on the field insulating layer (6), a recess (8x) is formed in a part of the field insulating layer (6) as shown in Figure 10. 47) is left in the form or remains (48)
will not occur.

Therefore, when the base extraction area (38) is shaped and the metal electrodes (61), (62, and Therefore, high-performance semiconductor devices can be manufactured with high yield.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows an example of the present invention, which is applied to the manufacture of a semiconductor integrated circuit having a high-performance pnp bipolar transistor and an ultra-high-speed npn bipolar transistor.

In the figure, parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals, and redundant explanation will be omitted.

In this example, as shown in FIG.
A) and a P-type channel stop region (3) corresponding to the substrate potential extraction electrode forming portion (IC).

N-type collector buried region (2) 9 N-shaded region (4A) (n p n ) formed by an epitaxial layer separated by a field insulating layer (6) formed by selective oxidation (for transistor)
, an n-type collector extraction region (5), an n-shaded region (4B) (for p n p ) transistor by an epitaxial layer), a p-type collector extraction region (32), and a p-type substrate potential extraction region (51). Then, an insulating film such as a thin SiOg film (7) is formed on the entire surface. The p-type collector extraction region (32) is simultaneously connected to the substrate potential extraction region (51) via a resist mask (50) with a thin 5iOt
This is achieved by ion implantation of, for example, poron (B+) from above the membrane (7). The n-type collector extraction region (5) is also formed by ion implantation of, for example, arsenic (As'') onto the thin SiO□ film (7).

Next, as shown in FIG. 1B, a thin S i Ot l1l
For (7), n shadow area (4A
), emitter formation part and P-type collector extraction area of n shadow area (4B) in formation part (IB), formation part (IC)
Openings (52), (53), (54),
After forming (55), a first polycrystalline silicon film (8) is formed over the entire surface by the CVD method, and boron ions as a p-type impurity are implanted into this polycrystalline silicon film (8).

Next, as shown in FIG. 1C, a p1 polycrystalline silicon film (8) is left in a region extending from the emitter formation region to the p-type collector extraction region in the formation region (IB) through the resist mask (9). Pattern it like this.

At the same time, in the forming section (1^), the polycrystalline silicon film 8) is patterned into the external shape of the base extraction electrode through a resist mask.

Next, as shown in the first diagram, a polycrystalline silicon film 8 is formed.
) After depositing and forming a film (10) of Sin on the entire surface including
to give form to.

Next, as shown in FIG. 1E, the 5iOz film (10) and the p+ polycrystalline silicon removed film 8) are applied to the collector extraction region (3) through the resist mask (11) in the forming area (1B).
2) and the n-shaded area (4B) by selectively etching it by, for example, the RIE method so as to separate it on the insulating film (7), and forming a straw ivy extraction electrode (3) by forming a polycrystalline silicon film 8).
6) and the collector lead-out electrode (35>). In this case, the portion of the polycrystalline silicon film 8) extending from a part of the field insulating layer (6) to the base lead-out region formation portion is removed by etching. . At the same time, in the formation area (IA), SjO□JP! of the portion corresponding to the active area where the intrinsic base region and emitter region are to be formed is formed through the resist mask (11). (10) and p'polycrystalline silicon film 8) are selectively etched away using the RIE method to remove the opening (13).
), and a base extraction electrode (60) made of p-crystalline silicon is formed. Furthermore, in the formation part (1C), an extraction electrode (65) made of P゛゛crystalline silicon
form. RIE is performed on the verge of overetching. Here, in the formation part (IB), the Stow film (1
During selective etching of 0〉 and p゛polycrystalline silicon film formation 8), P゛polycrystalline silicon peritoneum 8) has n shadow region (4B
) and the insulating film (7) between the P-type collector extraction region (32)
), the underlying insulating film (7), especially a part of the field insulation M (6), is not removed by etching as in the conventional method, and the entire insulating film (7) is kept flat. dripping

Next, the formation part (IB) side is covered with a resist mask (56>), and on the formation part (1A) side, boron (B+) as a P-type impurity is ion-implanted through the opening (13) to form a p-type link base region ( 14).

Next, as shown in FIG. 1F, a Sin film is deposited by the CVD method, heat treated to densify, and etched back to expose the p3 polycrystalline silicon film in the formation areas (IB) and (IA). A sidewall (15) by Sing is installed on the side of the building. Densify heat treatment reduces p°
The formation part (I) is formed by boron diffusion from the polycrystalline silicon film (8).
In B>, a part of the emitter region (39) is formed, and in the forming part (IA), a part of the external base region (16) is formed. Then, by light etching, the 5iOt film (7), which is thin in terms of self-alignment, is selectively etched away to expose the base extraction region forming part on the forming part (IB) side. Also, the emitter formation portion is exposed on the formation portion (l^) side.

Then, a second polycrystalline silicon film (18) is applied over the entire surface by CVD.
The second polycrystalline silicon film (1
8>, a p-type impurity such as boron (Bo) is ion-implanted and annealed to form a p-type intrinsic base region (19) in the active region.

Next, as shown in FIG. 1G, an n-type impurity such as arsenic (^s + ) is ion-implanted into the second polycrystalline silicon film (19) and annealed to form an n-type impurity in the formation portion (IB). A base extraction region (38) is formed, and an n-type emitter region (20) is formed in the formation portion (IA).

Next, as shown in FIG. 1H, a resist mask (58) is applied.
The n゛ polycrystalline silicon film (19) is patterned to form a base lead-out electrode (40) made of n++ crystal silicon in the formation part (IB), and the emitter lead-out electrode made of n゛゛ crystal silicon is formed in the formation part (14). electrode(
59〉.

Next, a contact hole is formed, and a metal (e.g. AZ) ivy electrode (61
), the base electrode (62), and the collector electrode (63) are shaped like t.
In the forming part (IA), an emitter electrode (23), a base electrode (21), and a collector electrode (24) made of metal are formed.
A substrate potential extraction electrode (64) made of metal is formed in the forming portion (IC).

In this way, as shown in FIG.
8) is obtained.

According to this manufacturing method, especially in the high-performance pnp bipolar transistor (67), the polycrystalline silicon film (8) is formed in the step shown in FIG. After patterning, in the next step of the first drawing, the field insulating layer (6) is etched by RIE of the SiO□ film (7) and polycrystalline silicon II (8) on the base extraction region forming part, and selectively etched to the extent of over-etching. Etching is performed without forming any steps, and flatness is maintained. Moreover, unlike the tenth diagram, a residue (48) is not formed between the emitter forming portion and the collector extraction region. This improves the flatness in this region and reduces the level difference on the surface as a whole. Therefore, there is no remaining metal that can cause short circuits between electrodes when metal electrodes are formed, and metal,
Since no dust is generated due to peeling off of the residue, the semiconductor integrated circuit (68) can be manufactured with high reliability and high yield.

FIG. 2 shows another example of the fourth invention, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals and redundant explanation will be omitted.

In this example, after going through the steps shown in FIGS. 2A and B (same steps as those in FIGS. 1A and B described above), as shown in FIG. 2C, the forming portion ( 1B), the p+ polycrystalline silicon film (8) is formed into a field insulating layer (6).
) pattern to separate on top. At this time, the P polycrystalline silicon film (8
) is patterned so that the portion overlapping with the field insulating layer (6) becomes longer. By this patterning, a polycrystalline silicon film (8) is formed on the p-type collector extraction region (32).
A collector lead-out electrode (35) is formed. At the same time, in the forming portion (1^), the p'polycrystalline silicon film (8) is patterned into the external shape of the base lead-out electrode through the resist mask (9) as in the case of FIG. 1C.

Next, as shown in the second diagram, a p+ polycrystalline silicon film (
After forming a SiO □ film (10) on the entire surface including 8) by CVD method, on and on the collector extraction electrode (35) in the forming part (IB).
A resist mask (11) is patterned to cover the end of the P polycrystalline silicon film (8) separated from the p-polycrystalline silicon film (8) and to cover the portion corresponding to the emitter extraction electrode except for the base extraction region forming part. form.

Next, as shown in FIG. 2E, this resist mask (1
1) The Si0g film (10), the p0 polycrystalline silicon film (8), and the underlying thin Si0g film (7) are selectively etched away using R and IE to expose the base extraction region formation part, and An emitter extraction electrode (36) is formed using a polycrystalline silicon film. With this selective etching, the emitter lead electrode (36) and the collector lead electrode (
A polycrystalline silicon film (8x) remains partially independent on the field insulating layer (6) between 35 and 35.

At the same time, in the formation area (IA), Si0 is exposed through the resist mask (11) in a portion corresponding to the active area, similar to FIG. 1E.
The G film (10) and the P'polycrystalline silicon film (8) are selectively etched away to form an opening (13).

Here, in the formation part (IB), the field insulating layer (6) is patterned so that a part of the P2 polycrystalline silicon film (8x) remains independently on the field insulating layer (6).
) is not locally etched, and no residue is generated due to the P polycrystalline silicon film or the 5i (H film).

In FIG. 2E, a resist mask (56) is used to form the formation area (
P-type impurity boron (
Bo) is ion-implanted into the p-type link base region (1
4) is formed.

After that, see Figure 2 F~! As shown in Figure 1 above,
Through the same steps as above, a semiconductor integrated circuit (70) having a high-performance pnp bipolar transistor (69) and an ultra-high speed npn bipolar transistor (24) is obtained.

According to this manufacturing method, especially in a high-performance pnp bipolar transistor (69), as shown in FIG. By patterning the polycrystalline silicon film (8x) so that the part becomes long, and then patterning it in the second patterning so that a part of the polycrystalline silicon film (8x) remains on the field insulating layer (6), the surface level difference is reduced. eased. At the same time, residues (48) caused by the polycrystalline silicon film and the 5i (h film) are not formed between the emitter formation portion and the collector extraction region as shown in Figure 10.

Therefore, during the subsequent formation of metal electrodes, there is no metal residue or peeling off of the metal or residue, which causes short circuits between the electrodes, and this type of semiconductor integrated circuit (70) can be manufactured with high reliability and high yield. I can do it.

Next, element isolation (
In a bipolar transistor with so-called acos isolation, a high-performance bipolar transistor can be realized by adopting a so-called pedestal structure in which the collector region immediately below the emitter region is a high concentration region and the other collector regions are lower concentration regions. That is, taking the above-mentioned npn bipolar transistor as an example, the fourth
As shown in the figure, only 10" directly below the emitter region (20)
By configuring the collector region (83) so that the n shadow region (81) is on the order of Ca1-' and the other n shadow region (82) has a low concentration on the order of 10"cuI-", the collector junction capacitance lc is , c can be reduced, and the base area (
The Kirk effect (19) is suppressed and a high-speed, low power consumption bipolar transistor is realized. In the figure, (1) is P
(6) is a field insulating layer formed by selective oxidation, (2) is a collector buried region, (5) is a collector extraction region, (16) is an external base region, and (31) is a channel stop region.

However, as shown in Figure 4, the pedestal structure is
When trying to realize this with an OGOS isolation layer, the thickness of the n-epitaxial layer constituting the n-shadow region (82) increases in order to reduce the collector junction capacitance Cjc, and the bottom of the field insulating layer (6) and the collector buried region become thicker. (2)
A gap (84) is created between the external base region (16
) and p-type substrate (1) (i.e. parasitic pnp transistor)
The withstand voltage BVIISG becomes lower. For this reason, n fiI
There is a limit to the thickness of the n-epitaxial layer constituting the region (82), and the effect of the pedestal structure cannot be sufficiently obtained. Here, the idea of the pedestal structure is that the emitter region (20
) By making the n-type epitaxial layer constituting the low-concentration collector region (82) other than directly below thick and low-concentration, the depletion layer is expanded toward the n-type epitaxial layer side and the collector junction capacitance Cj c is reduced, and the emitter By increasing the concentration of the collector region (81) only directly under the region (20), Cj
This is to suppress the increase in c and prevent the Kirk effect.

In view of this point, FIG. 3 shows an embodiment of a high-performance bipolar transistor in which the withstand voltage Bv0° is improved and a pedestal structure is made possible. In this example, the present invention is applied to an npn bipolar transistor, and parts corresponding to those in FIG. 4 are designated by the same reference numerals.

In this example, a collector buried region (2) and a p-type channel stop region (3) are formed on a p-type silicon substrate (1).
For example, a relatively thick n-type epitaxial layer (4) with an impurity concentration on the order of IQIsc11 is formed through the N-type collector extraction region (5) and P-type external base region separated by a field insulating layer (6) formed by selective oxidation. (16), a p-type intrinsic base region (19), and an n-type emitter region (20) are formed, and in the epitaxial layer (4) directly under the emitter region (20), an impurity concentration of, for example, n A shadow region (81) is formed to form a low concentration n shadow region (82) by the epitaxial layer and a higher concentration n shadow region (82).
81) to form an n-type collector region (83),
Furthermore, an n
A shaped high concentration region (84) is formed and configured.

This n-type high concentration region (84) can be formed by the following method. For example, after forming a collector buried region (2) doped with antimony (Sb), an arsenic (^S) doped region is formed around the collector buried region (2), and then epitaxial N (4) is formed.

Since AsO has a larger autodoping and diffusion coefficient than sb, an n-type high concentration region (84) can be automatically formed in the epitaxial layer (4).

Alternatively, after forming the field insulating layer (6) by selective oxidation, the n-type high concentration region (84) can be formed by high-energy ion implantation (for example, phosphorus ion implantation).

Or p-type silicon substrate (1) in recess LOCOS
After selectively etching, an n-type impurity is ion-implanted into the part where the n-type high concentration region is to be formed, and then a field insulating layer (6) is formed by selective oxidation to form the n-type high concentration region ( 84) can be formed simultaneously.

According to the above-described npn bipolar transistor (85), by having the pedestal structure, the collector junction capacitance IC4° can be reduced, and the Kirk effect of the base region (19) can be reduced, and the field insulation N (6) can be reduced. The breakdown voltage B between the external base region (16) and the p-type silicon substrate (1) is increased by providing the n highest concentration region (84) between the bottom side of the collector buried region (2) and the collector buried region (2).
Vsso can be made smaller. Therefore, a high-performance bipolar transistor with high speed and low power consumption can be realized.

In the configuration shown in FIG. 3, if the pedestal structure is not used, that is, if the n-shaded region (81) is not formed, the collector junction capacitance Cjc is further reduced, resulting in a bipolar transistor with low power consumption. Therefore, in circuits used with large currents, a bipolar transistor with a pedestal structure (85) is used, and in circuits used with low currents, the n-shaded region (81
) By using a bipolar transistor with a structure (not a pedestal structure), higher performance LS can be achieved.
I is obtained.

The bipolar transistor shown in FIG. 3 above can be applied to the ultra-high speed bipolar transistor (24) shown in FIG. 1 described above and a normal bipolar transistor.

On the other hand, in order to improve the integration density of elements in LSIs and the like, element isolation technology has shifted from selective oxidation (LOGO5) isolation to trench isolation.

The current mainstream trench isolation technology is to bury polycrystalline silicon (94) all at once in a trench (92) formed in a silicon substrate (91) via an inner wall oxide film (93), as shown in Figure 6. trench (so-called Po1y 5i-filled
Trench).

However, in the case of this technology, in the step of oxidizing the surface of the polycrystalline silicon (94) embedded in the groove (92), the particle bird's beak (9) of the oxide film (95) is formed.
Crystal defects (96) are likely to occur due to the stress caused by 5a). Therefore, as shown in Fig. 7, there is a method of refilling the polycrystalline silicon (94) with SiO□ (97) by CVD without oxidizing the surface. In this process, the surface (94a) of the polycrystalline silicon (94) is oxidized, so stress is applied due to volumetric expansion, which tends to cause crystal defects as in the case described above.

FIG. 5 shows an embodiment of a method for manufacturing a semiconductor device that improves this point, that is, a method for forming a trench M9M region.

In this example, as shown in FIG. 5A, a silicon substrate (
A groove (92) is formed on the main surface of the groove (91) by, for example, RIE, and an oxide film (SiO□) (93) is formed on the inner wall of the groove (92).
After shaping, polycrystalline silicon (
94).

Next, as shown in FIG. 5B, polycrystalline silicon (94)
At the same time, the polycrystalline silicon (94) in the trench (92) is removed to a required depth to form a recess (98).

Next, as shown in FIG. 5C, an oxidation-resistant film, for example, 5iN111 (99) and a SiOg film (100) are deposited on the inside of the recess (98) by CVD, and then SiO□ The film (100) and the SiN film (99) are etched back to fill the groove (92) with polycrystalline silicon (94), as shown in Figure 5, and an oxidation-resistant SiN film is placed on top of the polycrystalline silicon (94). (99) via 5iOzBU (100
) is obtained. A trench isolation region (111) is obtained.

According to this trench isolation region (111), the groove (92
) is coated with an oxidation-resistant SiN film (99), which prevents the surface of the polycrystalline silicon (94) from being oxidized in the subsequent oxidation process. . Therefore, the stress applied to the silicon substrate (91) is reduced, the occurrence of crystal defects can be suppressed, and the transistor characteristics can be improved.

〔Effect of the invention〕

According to the first aspect of the present invention, in a method for manufacturing a high-performance bipolar transistor, a collector lead-out region of a first conductivity type is formed on the outside partitioned by a field insulating layer, and a collector lead-out region of a first conductivity type is formed on the inside.
An insulating film having openings at positions corresponding to the collector extraction region and the emitter formation region is formed on the surface of the substrate on which the conductive type semiconductor region is formed, and a semiconductor film containing the first conductive type is formed on the insulating film. , patterning the semiconductor film so as to leave a region extending from the emitter formation region to the collector extraction region;
Next, the semiconductor film is patterned so as to be separated on the insulating film together with the insulating film formed on the entire surface to form an emitter lead-out electrode and a collector lead-out electrode using the semiconductor film, thereby making it possible to improve the surface flatness. ,
Even in the subsequent formation of metal electrodes, there is no metal residue or peeling, and this type of highly reliable high-performance bipolar transistor can be manufactured at a high yield.

Further, according to the second aspect of the present invention, in manufacturing a high-performance bipolar transistor, a collector extraction region of the first conductivity type is formed on the outside partitioned by the field insulating layer, and a semiconductor region of the second conductivity type is formed on the inside. On the formed substrate surface,
An insulating film having an opening at a position corresponding to the collector extraction region and the emitter formation part of the semiconductor region is formed, a semiconductor film containing a first conductivity type impurity is formed on the insulating film, and this semiconductor film is separated on the field insulating layer. By patterning the semiconductor film to form a collector electrode, and then patterning the semiconductor film so that a portion of it remains on the field insulating layer together with the insulating film formed on the entire surface, the emitter lead-out electrode can be formed. can improve the degree of
Even in the subsequent formation of metal electrodes, there is no metal residue, peeling, etc., and this type of highly reliable, high performance bipolar transistor can be manufactured at a high yield.

Therefore, in particular, an ultra-high-speed bipolar transistor in which the base extraction electrode and the emitter extraction electrode are formed of a polycrystalline silicon film, and the base region and emitter region are formed in a self-aligned manner by impurity diffusion from the polycrystalline silicon film for emitter extraction. This manufacturing method is suitable for use in manufacturing high-performance bipolar transistors of a conductivity type opposite to this ultra-high-speed bipolar transistor.

[Brief explanation of drawings]

FIG. 1 A-1 is a manufacturing process diagram showing an example of a method for manufacturing a semiconductor integrated circuit according to the present invention, FIG. 2 A-1 is a manufacturing process diagram showing another example of a method for manufacturing a semiconductor integrated circuit according to the present invention, FIG. 3 is a sectional view showing an example of a bipolar transistor with a pedestal structure, FIG. 4 is a sectional view showing a comparative example of a pedestal structure, and FIGS. 6 and 7 are cross-sectional views showing comparative examples of trench isolation regions, respectively, FIGS. 8A-D are process diagrams showing a method for manufacturing an ultra-high-speed npn bipolar transistor used to explain the present invention, and FIGS. 9A-E is a high performance pnp which serves to explain the present invention.
FIGS. 10A to 10D, which are process diagrams showing a method for manufacturing a bipolar transistor, are cross-sectional views showing the step order in an enlarged manner. (1) is a p-type silicon substrate, (6) is a field insulating layer, (7) is a thin insulating film, (8) is a p-polycrystalline silicon film, (10) is a 5i02 film, (32) is a collector extraction area , (35) is a base extraction electrode, (36) is an emitter extraction electrode, and (39) is an emitter region. Agent Hidemori Matsukuma @ Figure 4, Figure 4, Figure 1, Figure 8, Amendment of process drawing procedure, 1. Display of the case Flat-bottomed patent application No. 325291 No. 325291 2 Name of the invention Method for manufacturing a semiconductor device 3 Person making the amendment Relationship with the case

Claims (1)

[Scope of Claims] 1. A collector extraction region of the first conductivity type is formed on the outside partitioned by the field insulating layer, and a semiconductor region of the second conductivity type is formed on the inside surface of the base body; and a step of forming a first insulating film having an opening at a position corresponding to the emitter formation portion of the semiconductor region, a step of forming a semiconductor film containing a first conductivity type impurity over the opening and the entire surface of the insulating film. patterning the semiconductor film containing impurities of the first conductivity type so as to leave a region extending from the emitter formation region to the collector extraction region;
forming an insulating film, patterning the first conductivity type impurity-containing semiconductor film together with the second insulating film so as to separate them on the first insulating film, and forming an emitter lead-out electrode and a collector lead-out electrode. A method for manufacturing a semiconductor device, which includes a step of forming a semiconductor device. 2. A collector extraction region of the first conductivity type is formed on the outside partitioned by the field insulating layer, and a semiconductor region of the second conductivity type is formed on the inside. a step of forming an insulating film having an opening at a position corresponding to the formation portion; a step of forming a semiconductor film containing impurities of a first conductivity type over the opening and the entire surface of the insulating film; a semiconductor film containing impurities of the first conductivity type; a step of forming a collector lead-out electrode by patterning them separately on the field insulating layer;
forming an insulating film, and patterning the first conductivity type impurity-containing semiconductor film together with the second insulating film so as to partially remain on the field insulating layer to form an emitter extraction electrode. Manufacturing method of the device.