JP2002208597A - Bipolar transistor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely control the spacing sizes between field oxide films of bipolar transistors and control the doping profile at the collector in an independent process. SOLUTION: The bipolar transistor has an element isolating oxide film 3 region on the surface of a silicon wafer 1 having a first conductivity type buried region 2, a through-hole 3a formed into the isolating oxide film 3 and a collector region 4 buried in the through-hole 3a, adjacent to the buried region 2. Since the collector region 4 is buried in the hole 3a of the previously formed oxide film 3, no bird beak appears at the boundary between the oxide film 3 region and an intrinsic transistor region and the spacing size between the field oxide films 3 is precisely controllable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a bipolar transistor and a method of manufacturing the same, and more particularly to a bipolar transistor whose operating frequency is effective in a GHz band.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device including a bipolar transistor as shown in FIG. 15, the structure of an element isolation region of the bipolar transistor is formed on the surface of a silicon wafer 47 on which a buried region of the first conductivity type is formed. In order to surround the intrinsic transistor section 46, LOCOS (Lo
The separation is performed by an element isolation oxide film (field oxide film) 41 formed by a process of cal oxidation of silicon (SiC), and impurities forming the second conductivity type are surrounded so as to surround the buried region 48 of the first conductivity type. The separation by the channel stop region 49 formed by ion implantation has been used in combination. The intrinsic transistor section 46
Collector region 43, base region 44, emitter region 45
It is composed of

[0003]

The conventional structure as described above has the following problems. 1) The intrinsic transistor portion 46 is formed between the field oxide films 41, 41 formed by the LOCOS process. In the LOCOS process, the boundary between the field oxide film 41 and the intrinsic transistor portion 46 is As shown in FIG. 15, a bird's beak 42 occurs, and the region of the field oxide film 41 becomes wider than the pattern size of LOCOS. As a result, the field oxide films 41, 4
In other words, it is difficult to control the interval of 1, that is, the dimension of the intrinsic transistor portion 46, it is difficult to miniaturize the transistor, and it is difficult to increase the speed of the transistor. 2) In the field oxidation step during the LOCOS process, typically, a high temperature such as 1000 ° C. and several hours
A long-time process is required, during which doping ions in the buried region 48 rise greatly into the epitaxial film in the collector region 43, making it difficult to control the doping profile on the collector side and suppressing variations in transistor characteristics. was difficult. 3) To mitigate the effects of the bird's beak 42,
Since the channel stop region 49 is provided around the transistor, a relatively large distance must be provided between the transistor and an adjacent transistor, which has been an obstacle to high integration in an integrated circuit. The present invention solves such a conventional drawback, and allows the dimension of the interval between the field oxide films to be finely controlled.
The collector side doping profile can be controlled by an independent process without being affected by the field oxidation step in the LOCOS process. Therefore, it is a bipolar device which can be operated at high speed with little variation in characteristics and also capable of ultra-high integration. It is an object to provide a transistor.

[0004]

In order to solve the above-mentioned problems, a bipolar transistor according to the present invention has a planar type bipolar transistor having an inter-element isolation oxide film region on the surface of a silicon wafer having a buried region of a first conductivity type. A transistor, wherein a through-hole is formed in the inter-element isolation oxide film on the buried region of the first conductivity type, and a collector region in contact with the buried region of the first conductivity type is buried in the through-hole. It is characterized by the following. According to the bipolar transistor having such a structure, the bird's beak does not occur at the boundary between the oxide film region and the intrinsic transistor portion region because the collector region is buried in the hole of the inter-element isolation oxide film formed in advance. In addition, the distance between the field oxide films can be finely controlled. Further, the collector doping concentration of the collector region can be accurately controlled because it is not affected by the field oxidation step during the LOCOS process. Therefore, the speed of the bipolar transistor can be increased, and the variation in characteristics can be suppressed. Further, since there is no spread of bird's beak, there is no need to form a channel stop region, and the distance between adjacent elements can be reduced accordingly to achieve high integration and reduce the number of steps.

By making the thickness of the central part of the collector region smaller than the thickness of the inter-element isolation oxide film, the collector traveling time of carriers can be shortened, and at the same time, the inter-element isolation oxide film is made thicker. Since the value of the parasitic capacitance using the element isolation oxide film as a dielectric can be reduced, the speed of the transistor can be increased. In addition, since the thickness of the collector region at a portion in contact with the side wall of the through-hole of the inter-element isolation oxide film is substantially equal to the thickness of the inter-element isolation oxide film, the intrinsic collector portion and the inter-element isolation oxide film are separated. The step at the contact portion of the film is eliminated, the junction with the base region formed thereon is improved, and the characteristics of the transistor are improved.

Further, by changing the doping profile in the epitaxial film in the collector region from the side of the buried region so as to decrease, the collector doping concentration at the collector-base junction decreases, and the collector-base concentration decreases. Since the parasitic capacitance at the junction is reduced and the Kirk effect can be suppressed, a high-speed transistor can be realized.

The portion of the collector region in contact with the through hole of the inter-element isolation oxide film is polycrystallized, and when an intrinsic base and an intrinsic emitter are formed immediately above the polycrystallized portion, the polycrystalline portion is regenerated. Leakage current flows due to coupling. In order to suppress this phenomenon, when the inner diameter D of the through hole is Db, the inner diameter of the emitter-base junction formed above the collector region is Tc, and the thickness of the central portion of the collector region is Tc,
It is desirable to set the range represented by the following equation 1 D> Db + 2 × Tc (equation 1). By doing so, the intrinsic transistor region can be formed avoiding the polycrystalline portion.

Further, the base region of the bipolar transistor of the present invention can be formed by an ion implantation method or an epitaxial film growth method. Therefore, it is possible to use a conventional silicon or a SiGe epitaxial film or a SiGeC epitaxial film which is a material for forming a heterojunction with silicon as a base, and it is possible to form a higher-speed bipolar transistor by band engineering. Becomes

In the method of manufacturing a bipolar transistor according to the present invention, a silicon wafer having a buried region of a first conductivity type is thermally oxidized to form an oxide film on a surface of the silicon wafer. A predetermined area on the mold buried area is removed by etching to form a through hole,
A silicon epitaxial film of the first conductivity type is grown on the surface of the buried region of the first conductivity type exposed to the through hole or on the surface of the inter-element isolation oxide film, and the buried region of the first conductivity type is grown by an etch-back process. The silicon epitaxial film is removed from the inter-element isolation oxide film while leaving the silicon epitaxial film, and then the silicon epitaxial film left in the through hole is used as a collector region. is there. According to such a method for manufacturing a bipolar transistor, the hole of the oxide film precisely controlled by lithography determines the width of the collector region of the bipolar transistor.
A bird's beak generated in the OCOS process can be eliminated to enable fine dimensional control, and a high-speed transistor can be formed. In addition, since excessive heat treatment is not performed after the formation of the silicon epitaxial film in the collector region, the dopant distribution of the collector epitaxial film becomes the collector dopant distribution of the transistor as it is. Therefore, the collector concentration is accurately determined only by the dopant distribution at the time of forming the epitaxial film, and the variation in transistor characteristics can be suppressed. Furthermore, since the collector epitaxial film is surrounded by an oxide film without a bird's beak and is isolated from an adjacent element, a channel stop for element isolation is not required, and the distance between adjacent elements can be reduced accordingly. Therefore, high integration is possible. In addition, a channel stop process is not required, and an oxide film forming process for separating elements is not performed.
Since it is simpler than the OCOS process, the number of steps can be greatly reduced, and the LT of the steps can be reduced.

The etching for forming a through hole in the inter-element isolation oxide film includes a step of removing 70 to 95% of the thickness of the oxide film by dry etching, and a step of removing the remaining oxide film by wet etching. Since the first conductive type buried region surface is not damaged by plasma due to dry etching, a subsequent collector epitaxial film can be formed satisfactorily. It is desirable that the thickness of the oxide film removed by dry etching be 80 to 90% in order to more accurately form the diameter of the through hole.

If the thickness of the first conductivity type silicon epitaxial film is not more than the thickness of the inter-element isolation oxide film, a photoresist is formed at the center of the collector region during the etch back process of the silicon epitaxial film. Remains, and the surface of the collector region is not exposed to plasma damage due to dry etching in the etch-back process, so that good crystallinity can be maintained.

According to another method of manufacturing a bipolar transistor of the present invention, a silicon wafer having a buried region of a first conductivity type is thermally oxidized to form an oxide film on the surface of the silicon wafer. A predetermined region on the buried region of one conductivity type is removed by etching to form a through hole, and non-doped silicon is formed on the surface of the buried region of the first conductivity type or the surface of the isolation oxide film exposed to the through hole. An epitaxial film is grown, and the silicon epitaxial film on the inter-element isolation oxide film is removed by an etch-back process while leaving the silicon epitaxial film on the buried region of the first conductivity type. The silicon epitaxial film in the hole is doped with the first conductivity type, and the silicon epitaxial film is It is to be characterized in that none the Kuta area. According to the manufacturing method of such a bipolar transistor, since the hole of the oxide film precisely controlled by lithography determines the width of the collector region of the bipolar transistor, it is possible to eliminate the bird's beak generated in the LOCOS process and to perform fine dimensional control. Thus, a high-speed transistor can be formed. In the dopant profile of the collector region, the dopant distribution of the ion implantation becomes the collector dopant distribution of the transistor as it is. Therefore, the collector concentration is accurately determined only by the dopant distribution at the time of forming the epitaxial film, and the variation in transistor characteristics can be suppressed. Furthermore, since the collector epitaxial film is surrounded by an oxide film without a bird's beak and is isolated from an adjacent element, a channel stop for element isolation is not required, and the distance between adjacent elements can be reduced accordingly. Because you can
High integration is possible. Further, since a channel stop process is not required, and an oxide film forming process for element isolation is simpler than a LOCOS process, the number of steps can be greatly reduced and the LT of the steps can be reduced.

The etching for forming a through hole in the inter-element isolation oxide film includes a step of removing 70 to 95% of the thickness of the oxide film by dry etching, and a step of removing the remaining oxide film by wet etching. Since the first conductive type buried region surface is not damaged by plasma due to dry etching, a subsequent collector epitaxial film can be formed satisfactorily. It is desirable that the thickness of the oxide film removed by dry etching be 80 to 90% in order to more accurately form the diameter of the through hole.

If the film thickness of the silicon epitaxial film of the first conductivity type is less than the film thickness of the inter-element isolation oxide film, a photo-etching process of the silicon epitaxial film causes a photo-resist to be formed at the center of the collector region. The resist remains, and the surface of the collector region is not exposed to plasma damage due to dry etching in the etch-back process, so that good crystallinity can be maintained.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention. In FIG. 1, 1 is n
Is a p-type silicon substrate on which a buried sub-collector region 2 is formed.
A collector region 4 doped with phosphorus of 00 ° to 5000 °, a collector electrode region 5 doped with phosphorus at a high concentration, a through hole 3a having a width of 1 to several μm, and a through hole 3b.
Is provided. Typically, oxide film 3 has a thickness of 6000 to 8000
It is desirable to make the thickness as thick as possible. Si1-xGex (0.03 <X) serving as a base region is formed above a part of the collector region 4 and the element isolation oxide film 3.
<0.5) The film 6 is formed to a thickness of 100 to 500
The i1-xGex (0.03 <X <0.5) film 6 is doped with about 5 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ of boron. The SiGe film 6 is monocrystalline in the upper part 6 a of the collector region 4 and polycrystalline in the upper part 6 b of the inter-element isolation oxide film 3. A phosphorus-doped (about 1 × 10 ²⁰ cm ⁻³ ) polysilicon emitter electrode 8 is formed over the SiGe single crystal film in the upper part 6 a of the collector region 4 via the contact window 7 a of the interlayer insulating film 7. Further, a collector extraction region 9 of polysilicon of the first conductivity type is also formed above the highly doped collector electrode region 5 through a contact window of the first interlayer insulating film 7. Further, contact windows 10a, 10b, and 10c of a second interlayer insulating film 10 are formed on the upper portion 6b of the SiGe polycrystalline film 6 above the isolation oxide film 3, the upper portion of the emitter polysilicon electrode 8, and the upper portion of the collector extraction region 9. Metallizations 11, 12, and 13 are provided via these.

FIG. 2 is a sectional view of a principal part of the bipolar transistor shown in FIG. 1. In FIG. 2, the n-type buried subcollector region 2 has a sheet resistance of 20 to 30 Ω / □.
About 1 × 10 ¹⁶ to 1 in the collector region 4.
× is 10 ¹⁸ cm ^-3 doping, the collector electrode region 5 is doped with a high concentration of phosphorus is 1 × 10 ¹⁸ cm ^-3 or more. The film thickness of the isolation oxide film 3 is 6000 to 800.
Although it is about 0 °, the contact portion 25 between the through hole 3a and the collector region 4 is inclined, and the surface of the thick element isolation oxide film 3 and the surface of the relatively thin collector region 4 are smoothly connected. Inter-element isolation oxide films 3 having different thicknesses
And the collector region 4 does not have a steep step. The doping profile in the epitaxial film at the center of the collector region 4 is changed so that the doping concentration decreases from approximately 1 × 10 ²⁰ cm ^{−3 to} approximately 1 × 10 ¹⁶ cm ⁻³ as the distance from the buried region 2 increases. It is. By doing so, the parasitic capacitance at the collector-base junction is reduced, and the Kirk effect can be suppressed. The diameter of the through hole 3a of the element isolation oxide film 3 is about 1 to several μm, and the contact window 7a of the interlayer insulating film 7 is formed.
Is formed to have a diameter of about 0.3 to 1 μm. When the inner diameter of the through hole 3a is D, the inner diameter of the emitter-base junction is Db, and the thickness of the central part of the collector region 4 is Tc, the following equation (1) is obtained. Are in a relationship that satisfies D> Db + 2 × Tc (1) As a result, the intrinsic base and the intrinsic emitter are
The collector region 4 is formed immediately above the single crystallized region avoiding the polycrystallized portion of the collector region 4 which is in contact with a.

Next, a first embodiment of the method of manufacturing the bipolar transistor shown in FIG. 1 will be described with reference to FIGS.
This will be described in detail with reference to FIG. 3 to 11 are process cross-sectional views illustrating a method for manufacturing a bipolar transistor according to the present invention. First, as shown in FIG. 3, As ions or Sb ions are ion-implanted only in the element region of the p-type silicon substrate 1, and a heat treatment for activation is performed to form a buried sub-collector region 2. Thereafter, it is thermally oxidized at about 1000 ° C. to form an element isolation oxide film 3. The oxide film 3 is preferably thicker, but typically, has a thickness of 6 mm.
It has a thickness of 000 to 8000.

Next, the photoresist 20 is patterned so that the through holes 3a and 3b for forming the collector formation region 4 and the collector extraction electrode portion 5 are opened, and the oxide film 3 is formed by anisotropic etching by dry etching. 95
%, Leaving a thin oxide film 21 as shown in FIG. Subsequently, the remaining thin oxide film 21 is removed by a wet etchant (for example, a buffered hydrofluoric acid aqueous solution) to form a through hole 3a for forming the collector region 4 and a collector extraction region 5 as shown in FIG. A through hole 3b is formed. The through-hole 3a of this collector region is approximately 1 to
It is formed to several μm. By doing so, the surface of the buried sub-collector region 2 at the bottom of the through-hole forming the collector region is not exposed to plasma by dry etching and is finally removed by wet etching. No damage is taken. Therefore, the subsequent collector epitaxial film can be formed without defect. Further, if the thickness of the oxide film 3 to be removed is about 80 to 90%, the variation of the through holes 3a can be reduced.

Next, the photoresist 20 is removed and, after appropriate cleaning, as shown in FIG.
^{16 ~1} × 10 ¹⁸ cm ^-3 doped epitaxial silicon film 22 to a thickness of 3000Å~5000Å formed on the entire surface of the substrate. Thereafter, a photoresist 23 is applied on the epitaxial silicon film 22 so that the steps of the oxide film 3 are reduced on the surface of the photoresist 23.

Next, as shown in FIG. 7, under the condition that the selectivity between the photoresist 23 and the epitaxial silicon film 22 is almost 1 or the etching rate of the epitaxial silicon film 22 is slightly high, the epitaxial silicon film 22 on the oxide film 3 is formed. Dry etching is performed until all are etched. Thus, a structure in which the silicon epitaxial film 22 is buried in the holes 3a of the oxide film 3 is completed. At this time, the photoresist 24 still remains on the surface of the collector region 4, and the surface of the collector region 4 is not exposed to plasma by dry etching, so that processing can be performed without plasma damage. it can.

Next, when the photoresist 24 is peeled off, the surface of the collector region 4 is separated from the boundary 25 between the oxide film 3 and the collector region 4 as shown in FIG.
And has a slightly inclined shape toward the center of the oxide film 3 and acts to fill the thickness difference between the oxide film 3 and the collector region 4. In this way, the oxide film 3 to be thickened and an appropriate film thickness in design are required, and the film thickness is typically 3000 to 5000
While realizing the collector region 4 as thin as Å, processing can be performed without generating a steep step. Subsequently, the photoresist is patterned so as to open the window 3b in the portion of the collector extraction region 5, phosphorus is ion-implanted into the collector extraction region 5, and heat treatment is performed to lower the resistance of the collector extraction electrode portion 5 and at the same time. To compensate for ohmic contact with metal.

Next, boron serving as a base region is 5 ×
Si 1-x doped about 10 ^{18 to} 5 × 10 ¹⁹ cm ^-3
The Gex (0.03 <X <0.5) film 6 is
Epitaxially grow to a thickness of 00 °. Then, Si1-
The xGex film 6 is patterned and etched as shown in FIG. 9 so that the SiGe film 6 remains only in the collector region 4 of the oxide film 3 and the upper portion around the collector region 4.

Next, as shown in FIG. 10, after a first interlayer insulating film 7 is formed to a thickness of about 3000 °, a collector region 4 is formed.
A window 7a having a width of 1 μm or less is opened at an upper portion, and a window 7b is opened at an upper portion of the collector extraction region 5. Then, phosphorus dope (1
(Approximately × 10 ²⁰ cm ⁻³ ) A polysilicon film is formed, and an emitter electrode 8 and a collector electrode 9 are formed by patterning and etching. Subsequently, phosphorus is diffused from the emitter electrode 8 to the SiGe film 6 by heat treatment to form an intrinsic emitter region.

Finally, the SiG layer on the emitter electrode 8, the collector electrode 9, and the element isolation oxide film 3
On top of the e film 6, a second interlayer insulating film 10
An N / AlSi / TiN laminated metal film is formed and patterned to form a collector 11, a base 12, and an emitter 13, thereby completing the transistor shown in FIG.

In the bipolar transistor thus manufactured, the collector region 4 is formed so as to be buried in the hole 3a of the inter-element isolation oxide film 3 formed in advance, so that the boundary between the oxide film region and the intrinsic transistor portion region is formed. Bird's beak does not occur, and the width dimension of the collector region 4 can be precisely and finely controlled to the same precision as the patterning dimension of the oxide film 3. Therefore, the speed of the bipolar transistor can be increased, and the variation in characteristics can be suppressed. In addition, after the collector epitaxial film 22 is formed, a high-temperature and long-time heat treatment such as field oxidation is not applied to the collector epitaxial film 22, so that the dopant concentration controlled by the collector epitaxial film 22 can be maintained to the end, A bipolar transistor as designed can be obtained. Further, since the collector film thickness is the same as the thickness of the collector epitaxial film 22 at the time of film formation, an optimal design in consideration of the Kirk effect and the withstand voltage can be realized. Therefore, it is possible to obtain a transistor having excellent high-frequency characteristics with a current cutoff frequency and a maximum oscillation frequency well exceeding 30 GHz. Furthermore, since the channel stop region, which has been conventionally required, is not required, the distance between adjacent elements is almost eliminated, high integration can be realized, and the number of steps can be reduced.

Next, a second embodiment of the method for manufacturing the bipolar transistor shown in FIG. 1 will be described with reference to FIG.
This will be described in detail with reference to FIGS. FIG. 12 to FIG.
FIG. 2 is a cross-sectional view of a main part step for explaining the manufacturing method of the bipolar transistor of the present invention. The difference between the manufacturing method of the second embodiment and the manufacturing method of the first embodiment resides in the collector portion, and therefore, the same portions as those of the first embodiment will be described using the same reference numerals. Omitted. First, the silicon substrate 1 is processed to the state shown in FIG. 5 by using the same process as in the first embodiment, and the through hole 3 a for forming the collector region 4 in the element isolation oxide film 3 and the collector extraction region 5 are formed. Is formed.

Next, the photoresist 20 is removed, and after appropriate cleaning, an intrinsic epitaxial silicon film 30 is formed on the entire surface of the substrate as shown in FIG. Thereafter, a photoresist 23 is applied on the upper part of the epitaxial silicon film 30 so that the step of the oxide film 3 is reduced on the surface of the photoresist 23.

Next, as shown in FIG. 13, under the condition that the selectivity between the photoresist 23 and the epitaxial silicon film 30 is almost 1 or the etching rate of the epitaxial silicon film 30 is slightly high, the epitaxial silicon film 30 Dry etching is performed until all are etched. Then, the holes 3 in the oxide film 3 are formed.
A structure in which a silicon epitaxial film is embedded in a and 3b is completed. At this time, the photoresist 24 still remains on the surface of the collector region 31, and the surface of the collector region 31 is not exposed to plasma by dry etching, so that processing can be performed without plasma damage. it can.

Next, when the photoresist 24 is peeled off, the boundary 25 between the oxide film 3 and the collector region 4 becomes slightly inclined toward the center of the collector region 31, as shown in FIG. And the collector region 31 is filled. Subsequently, the collector region 31
The photoresist is patterned so that a window is opened in the area of, and phosphorus is ion-implanted. In this ion implantation, the concentration near the interface between the buried subcollector region 2 of the collector region 31 and the buried subcollector region surface concentration (about 5
About × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ ), and the surface concentration of the collector region 31 is 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ^16.
This is performed under such a condition that the concentration becomes about cm ⁻³ and the phosphorus concentration of the collector region 31 decreases from the back side toward the surface side.

Next, the photoresist is patterned so as to open a window in the collector extraction region 5, and phosphorus ions are implanted. Subsequently, by performing a heat treatment at a temperature condition that is sufficient for activating the ion-implanted atoms but suppresses the diffusion of the dopant as much as possible, typically at 900 ° C. for about 1 minute, the collector region 31 has A collector having a doping profile inclined toward the surface is formed. In the collector extraction region 5, the resistance of the collector extraction electrode portion is reduced, and at the same time, the ohmic contact with the metal is compensated. Subsequently, the same bipolar transistor as that shown in FIG. 11 is completed by using the same process as that shown in FIGS. 9 to 11 of the first embodiment.

In the bipolar transistor manufactured in this way, a variation in characteristics is small, and a transistor excellent in high-frequency characteristics having a current cutoff frequency and a maximum oscillation frequency well exceeding 30 GHz can be obtained. Further, high integration can be realized and the process can be shortened.

In the practical example described above, the base region of the bipolar transistor is formed by using the SiGe epitaxial film. However, the base region can be formed by an epitaxial film growing method or an ion implantation method. Therefore,
Conventional silicon or a SiGe epitaxial film or a material that forms a heterojunction with silicon is used as a base.
It is also possible to use a GeC epitaxial film,
Band engineering makes it possible to form faster bipolar transistors.

[0033]

The bipolar transistor according to the present invention is a planar type bipolar transistor having an element isolation oxide film on the surface of a silicon wafer having a first conductivity type buried region formed therein, wherein the first conductivity type buried region is provided. A through-hole is formed in the inter-element isolation oxide film, and a collector region in contact with the buried region of the first conductivity type is buried in the through-hole. According to the bipolar transistor having such a structure, since the collector region is buried in the hole of the inter-element isolation oxide film formed in advance, there is no bird's beak at the boundary between the oxide film region and the intrinsic transistor portion region, and the field oxidation The distance between the films can be finely controlled. Also, since the collector doping concentration of the collector region is not affected by the field oxidation step during the LOCOS process,
Can be precisely controlled. Therefore, the speed of the bipolar transistor can be increased, and the variation in characteristics can be suppressed. Further, since there is no need to provide a channel stop region, the distance between adjacent elements can be reduced by that much, high integration can be achieved, and the number of steps can be reduced.

According to the method of manufacturing a bipolar transistor of the present invention, a silicon wafer having a buried region of the first conductivity type is thermally oxidized to form an oxide film on the surface of the silicon wafer. A predetermined area on the mold buried area is removed by etching to form a through hole,
A silicon epitaxial film of the first conductivity type is grown on the surface of the buried region of the first conductivity type exposed to the through hole or on the surface of the inter-element isolation oxide film, and the buried region of the first conductivity type is grown by an etch-back process. The silicon epitaxial film is removed from the inter-element isolation oxide film while leaving the silicon epitaxial film, and then the silicon epitaxial film left in the through hole is used as a collector region. is there. According to the manufacturing method of such a bipolar transistor, since the hole of the oxide film precisely controlled by lithography determines the width of the collector region of the bipolar transistor, it is possible to finely control the size and form a high-speed transistor. it can. Further, since excessive heat treatment is not performed after the formation of the silicon epitaxial film in the collector region, the dopant concentration of the collector is accurately determined only by the dopant distribution at the time of forming the epitaxial film, and the variation in transistor characteristics can be suppressed. Furthermore, since the collector epitaxial film is separated by an element isolation film without bird's beak, a channel stop process is not required, and high integration can be achieved. Furthermore, since a channel stop process is not required and an oxide film forming process for element isolation is simpler than a LOCOS process, the number of steps can be greatly reduced, and the LT of the step can be shortened.

In another method of manufacturing a bipolar transistor according to the present invention, a silicon wafer having a buried region of the first conductivity type is thermally oxidized to form an oxide film on the surface of the silicon wafer. A predetermined region on the buried region of one conductivity type is removed by etching to form a through hole, and non-doped silicon is formed on the surface of the buried region of the first conductivity type exposed on the through hole to the surface of the inter-element isolation oxide film. An epitaxial film is grown, and the silicon epitaxial film on the inter-element isolation oxide film is removed by an etch-back process while leaving the silicon epitaxial film on the buried region of the first conductivity type. Doping the silicon epitaxial film in the hole to a first conductivity type to form the silicon epitaxial film into a collector; It is characterized in that it is an area. According to the manufacturing method of such a bipolar transistor, since the hole of the oxide film precisely controlled by lithography determines the width of the collector region of the bipolar transistor, it is possible to finely control the size and form a high-speed transistor. it can. In the dopant profile of the collector region, the dopant distribution of the ion implantation becomes the collector dopant distribution of the transistor as it is. Therefore, the collector concentration is accurately determined only by the dopant distribution at the time of forming the epitaxial film, and the variation in transistor characteristics can be suppressed. Furthermore, since the collector epitaxial film is separated by an element separation film without bird's beak, channel stop is not required, and the distance between adjacent elements can be reduced by that amount, enabling high integration. Become. Further, a channel stop process is not required, and an oxide film forming process for element isolation is simpler than a LOCOS process, so that the number of steps can be greatly reduced and the LT of the step can be shortened.

[Brief description of the drawings]

FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of the bipolar transistor shown in FIG.

FIG. 3 is a first step sectional view for describing the first embodiment of the method for manufacturing the bipolar transistor shown in FIG.

FIG. 4 is a second process sectional view following FIG. 3;

FIG. 5 is a third process sectional view following FIG. 4;

FIG. 6 is a fourth process sectional view following FIG. 5;

FIG. 7 is a fifth process sectional view following FIG. 6;

FIG. 8 is a sixth process sectional view following FIG. 7;

FIG. 9 is a seventh process sectional view following FIG. 8;

FIG. 10 is an eighth process sectional view following FIG. 9;

FIG. 11 is a ninth process sectional view following FIG. 10;

FIG. 12 is a first step sectional view for describing the second embodiment of the method for manufacturing the bipolar transistor shown in FIG.

FIG. 13 is a second process sectional view following FIG. 12;

FIG. 14 is a third process sectional view following FIG. 13;

FIG. 15 is a sectional view of a conventional bipolar transistor.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 buried sub-collector region 3 interlayer isolation oxide film 3a, 3b hole 4 collector region 5 collector electrode region 6 SiGe epitaxial film 6a SiGe single crystal film 6b SiGe polycrystalline film 7, 10 interlayer insulating film 7a, 7b hole 8 emitter Electrode 9 Collector electrode 10a, 10b, 10c Hole 11, 12, 13 Metal

Claims (11)

[Claims] 1. A planar bipolar transistor having a device isolation oxide film region on a surface of a silicon wafer on which a first conductivity type buried region is formed, wherein the device isolation oxide region on the first conductivity type buried region is provided. A bipolar transistor, wherein a through-hole is formed in an oxide film, and a collector region in contact with the buried region of the first conductivity type is buried in the through-hole. A thickness of a central portion of the collector region is smaller than a thickness of the device isolation oxide film, and a thickness of a portion of the collector region in contact with a side wall of the through hole of the device isolation oxide film is reduced. 2. The bipolar transistor according to claim 1, wherein the thickness of the isolation oxide film is substantially equal to the thickness of the isolation oxide film. 3. The bipolar transistor according to claim 1, wherein the distribution of impurities forming the first conductivity type in the collector region in the depth direction gradually decreases as the distance from the buried region side increases. 4. The through hole inner diameter D of the collector region.
Is the inner diameter of the emitter-base junction formed above the collector region, and the thickness of the central portion of the collector region is Tc.
2. The bipolar transistor according to claim 1, wherein the following formula is satisfied: D> Db + 2 × Tc (Equation 1) 5. The method according to claim 1, wherein the base region in contact with the collector region is silicon or silicon germanium (SiGe).
Or silicon germanium carbide (SiGeC)
2. The bipolar transistor according to claim 1, comprising: 6. A silicon wafer having a buried region of the first conductivity type formed thereon is thermally oxidized to form an oxide film on the surface of the silicon wafer, and a predetermined portion of the oxide film on the buried region of the first conductivity type is formed. The region is removed by etching to form a through hole, and a first conductivity type silicon epitaxial film is grown on the surface of the first conductivity type buried region exposed on the through hole or the surface of the inter-element isolation oxide film, Removing the silicon epitaxial film on the inter-element isolation oxide film while leaving the silicon epitaxial film on the first conductivity type buried region by a back process, and then removing the silicon epitaxial film remaining in the through hole As a collector region. 7. Etching for forming a through hole in said inter-element isolation oxide film is carried out by reducing the thickness of said oxide film to 70 to 95%.
7. The method for manufacturing a bipolar transistor according to claim 6, comprising a step of removing the remaining oxide film by wet etching and a step of removing the remaining oxide film by wet etching. 8. The method of manufacturing a bipolar transistor according to claim 6, wherein said silicon epitaxial film is formed to a thickness equal to or less than a thickness of said inter-element isolation oxide film. 9. A silicon wafer having a buried region of the first conductivity type formed thereon is thermally oxidized to form an oxide film on the surface of the silicon wafer, and a predetermined portion of the oxide film on the buried region of the first conductivity type is formed. A region is removed by etching to form a through-hole, and a non-doped silicon epitaxial film is grown on the surface of the first conductivity type buried region exposed on the through-hole or the surface of the inter-element isolation oxide film. The silicon epitaxial film on the inter-element isolation oxide film is removed while leaving the silicon epitaxial film on the first conductivity type buried region, and then the silicon epitaxial film in the through hole is removed by ion implantation. A bipolar transistor characterized in that the silicon epitaxial film is used as a collector region by doping to a conductivity type. Manufacturing method of transistor. 10. A step of etching a predetermined region of the inter-element isolation oxide film by dry etching to remove 70 to 95% of the thickness of the oxide film, and a step of removing remaining oxide film by wet etching. The method for manufacturing a bipolar transistor according to claim 9, comprising: 11. The manufacturing method of a bipolar transistor according to claim 9, wherein said non-doped silicon epitaxial film is formed to a thickness equal to or less than a thickness of said inter-element isolation oxide film.