JPH0574794A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be lessened in parasitic capacitance and enhanced in high speed operation. CONSTITUTION:An intrinsic semiconductor layer 102 is formed on a first conductivity type semiconductor 101, a second conductivity type semiconductor layer 104 is formed on the intrinsic semiconductor layer 102, a first conductivity type semiconductor region 110 is formed on the semiconductor layer 104, and a first conductivity type region 108 is formed on the intrinsic semiconductor layer 102 under the semiconductor region 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, which can achieve high speed and high integration.

[0002]

2. Description of the Related Art In general, the speed of a bipolar semiconductor device is increased by improving the cutoff frequency by shallow diffusion and reducing the parasitic component by a fine processing technique.

Conventionally, a technique utilizing a thin epitaxial layer has been disclosed for shallow diffusion, and the structure of a bipolar transistor using such a technique will be described below with reference to FIG.

That is, a thin p-type base layer 18 is formed by epitaxial growth on the n-collector layer 12 on which the field oxide film 16 is selectively formed, and an opening is formed on a predetermined portion of the p-type base layer 18. The insulating layer 55 is formed, and the p-type base layer 18 and the insulating layer 55 excluding the openings are formed.
A p ++ base lead-out portion 34 whose surface is covered with an insulating film 42 is formed on the top. Further, an As-doped polysilicon layer 52 is deposited on the opening of the insulating layer 55, and an n + emitter layer 54 is formed on the surface of the p-type base layer 18 facing the opening of the insulating layer 55.

Further, in order to form a large number of elements on a semiconductor substrate to form an integrated circuit, it is necessary to separate the elements so as to electrically insulate the elements from each other. For this element isolation, a method of selectively oxidizing the periphery of the element region by thermal oxidation to form a thick insulating film is used. However, this method has a drawback that it is difficult to form a deep insulating region, and a bird's beak is formed by lateral growth of a thick oxide film to increase the area of the element isolation region.

Therefore, a trench element isolation method as shown in FIG. 13 has been proposed as a method of forming a deep element isolation region having a small element isolation region. This is because a thin and deep groove 4 is formed in the element isolation region by anisotropic etching, the surface of the deep groove 4 is thermally oxidized to form a relatively thick thermal oxide film 9, and then a polycrystal is formed in the deep groove 4. The silicon layer 7 and the silicon oxide film 8 are sequentially buried and planarized.

[0007]

However, in the above-mentioned conventional bipolar transistor, the crystallinity of the p-type base layer 18 is deteriorated at the boundary between the field oxide film 16 and the n-collector layer 12, so that It is necessary to separate the boundary from the active region immediately below the n + emitter layer 54. Therefore, the junction region between p type base layer 18 and n @-collector layer 12 becomes large, and the base / collector junction capacitance, which is a parasitic capacitance, increases, and there is a problem that high speed operation cannot be performed.

Further, in the conventional trench element isolation method, it is necessary to make the thermal oxide film 9 formed on the surface of the deep groove 4 relatively thick in order to reduce the parasitic capacitance. For this reason, a long-time thermal oxidation process is required, so that redistribution of impurities in the buried layer in the semiconductor substrate occurs during the thermal oxidation process, and the time of the thermal oxidation process is shortened to suppress the redistribution of impurities. This causes a problem that the oxide film becomes thin and the parasitic capacitance increases.

The object of the present invention is to solve the above-mentioned problems.
The present invention provides a semiconductor device that can reduce parasitic capacitance, can operate at high speed, and can be highly integrated, and a manufacturing method thereof.

[0010]

In order to achieve the above object, the present invention has an intrinsic semiconductor layer formed on a semiconductor substrate of the first conductivity type and a second intrinsic semiconductor layer formed on the intrinsic semiconductor layer.
A conductive type base layer, a first insulating layer having an opening formed on a predetermined portion of the base layer, and the base layer and the first insulating layer excluding the opening. A base lead-out portion whose surface is covered with a second insulating layer; a first conductivity type emitter layer formed on the surface of the base layer immediately below the opening; and an intrinsic semiconductor layer directly below the opening. And a formed collector layer of the first conductivity type.

Also, a step of selectively forming a first insulating film on the semiconductor substrate, and a step of anisotropically etching the semiconductor substrate with the first insulating film as a mask to form a first groove. A step of selectively forming a second groove at a predetermined position of the first groove, a step of thermally oxidizing the surfaces of the first and second grooves to form a second insulating film, and A step of forming a third insulating film on the second insulating film by a CVD method, a step of embedding a conductor film in the second groove, and a step of embedding an insulator in the first groove. is there.

[0012]

In the present invention, since the first conductivity type region is formed only in the intrinsic semiconductor layer immediately below the first conductivity type semiconductor region, the junction region between the base layer and the collector layer is reduced and the collector junction capacitance is reduced. To do.

Further, since the third insulating film is formed as a thick film by the CVD method in a short time, redistribution of impurities is suppressed.

[0014]

EXAMPLES Examples of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to FIGS.

First, the structure of the bipolar transistor according to this embodiment will be described with reference to FIG.

That is, the intrinsic semiconductor layer 102 and the field oxide film 103 are selectively formed on the n + buried layer 101, and the p-type base layer 104 is formed on the intrinsic semiconductor layer 102 and the field oxide film 103. .. Then, the insulating layer 10 having an opening on a predetermined portion of the p-type base layer 104.
5 is formed, and a base lead portion 106 whose surface is covered with an insulating film 107 is formed on the p-type base layer 104 and the insulating layer 105 except for the opening. Further, an As-doped polysilicon layer 109 is formed on the opening of the insulating layer 105.
Is deposited to form an n-type collector layer 108 on the intrinsic semiconductor layer 102 immediately below the opening of the insulating layer 105.
An n @ + emitter layer 110 is formed on the surface of the p-type base layer 104 facing the opening of No. 5.

Next, a method of manufacturing the bipolar transistor having such a structure will be described with reference to FIGS.

First, an intrinsic semiconductor layer 102 is formed on the n + buried layer 101, and then a field oxide film 103 is selectively formed. After that, the p-type base layer 104 is formed on the entire surface by epitaxial growth (FIG. 2).

Next, the insulating layer 10 is formed on the p-type base layer 104.
5 is formed and this is patterned. After that, the base lead portion 106 is formed so that the insulating layer 105 is exposed on the entire surface, and the insulating film 107 is formed on the surface of the base lead portion 106 (FIG. 3).

Then, using the insulating film 107 as a mask, the insulating layer 105 is opened. Further, ion implantation of phosphorus or the like is performed using the insulating film 107 as a mask to form an n-type collector layer 108 in the intrinsic semiconductor layer 102 immediately below the opening of the insulating layer 105. After that, an As-doped polysilicon layer 109 is deposited on the opening of the insulating layer 105, whereby As is diffused,
An n + emitter layer 110 is formed on the surface of the p-type base layer 104 facing the opening of the insulating layer 105 to complete the transistor (FIG. 1).

Next, the trench element isolation method according to this embodiment will be described with reference to FIGS.

First, the surface of the silicon substrate 1 is thinly oxidized to form a silicon oxide film 2a, and then the silicon oxide film 2 is formed.
A silicon nitride film 2b and a silicon oxide film 2c are sequentially deposited on a (FIG. 4).

Next, the insulating film composed of the silicon oxide film 2a, the silicon nitride film 2b and the silicon oxide film 2c is selectively removed by anisotropic etching to expose the substrate surface. After that, using the insulating films 2a, 2b, 2c as a mask,
The substrate 1 is anisotropically etched to form the shallow groove 3 (FIG. 5).

Next, the bottom surface of the shallow groove 3 is selectively anisotropically etched to form a deep groove 4. Next, the silicon oxide film 2c is removed (FIG. 6).

Then, the surfaces of the shallow groove 3 and the deep groove 4 are thinly oxidized to form a silicon oxide film 5 (FIG. 7).

Then, a thick silicon oxide film 6 is deposited on the entire surface by low pressure chemical vapor deposition (FIG. 8).

Then, a polycrystalline silicon layer 7 is buried in the deep groove 4 (FIG. 9).

Further, a silicon oxide film 8 is buried in the shallow groove 3 by low pressure chemical vapor deposition (FIG. 10).

Then, the silicon oxide film 8 is etched back to form the silicon oxide film 2a and the silicon nitride film 2b.
Are removed to planarize the device and complete the device isolation (see FIG.
1).

The silicon nitride film 2b is not necessarily used here, and only the silicon oxide films 2a and 2c may be used. Further, the chemical vapor deposition method (CVD method) does not necessarily have to be a low pressure, and can form a film at a relatively low temperature.
Any law is acceptable.

[0031]

As described above, according to the present invention, since the first conductivity type region is formed only in the intrinsic semiconductor layer immediately below the first conductivity type semiconductor region, the junction region between the base layer and the collector layer is formed. And the base / collector junction capacitance is reduced. Therefore, the speed of the device can be improved.

Further, since the third insulating film is thickly formed by the CVD method in a short time, redistribution of impurities is suppressed. Therefore, the parasitic capacitance can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a bipolar transistor of the present invention.

FIG. 2 is a manufacturing process drawing of the bipolar transistor of the present invention.

FIG. 3 is a manufacturing process drawing of the bipolar transistor of the present invention.

FIG. 4 is a process drawing of the trench element isolation method of the present invention.

FIG. 5 is a process drawing of the trench element isolation method of the present invention.

FIG. 6 is a process drawing of the trench element isolation method of the present invention.

FIG. 7 is a process drawing of the trench element isolation method of the present invention.

FIG. 8 is a process drawing of the trench element isolation method of the present invention.

FIG. 9 is a process drawing of the trench element isolation method of the present invention.

FIG. 10 is a process drawing of the trench element isolation method of the present invention.

FIG. 11 is a process drawing of the trench element isolation method of the present invention.

FIG. 12 is a cross-sectional view of a conventional bipolar transistor.

FIG. 13 is an explanatory diagram of conventional trench element isolation.

[Explanation of symbols]

 1 Silicon substrate 2a Silicon oxide film 2b Silicon nitride film 2c Silicon oxide film 3 Shallow groove 4 Deep groove 5,6,8 Silicon oxide film 7 Polycrystalline silicon layer 101 n + Buried layer 102 Intrinsic semiconductor layer 103 Field oxide film 104 p Type base layer 105 insulating layer 106 base extraction electrode 107 insulating film 108 n-type collector layer 109 As-doped polysilicon layer 110 n + emitter layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chihiro Yoshino 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research Institute Ltd. (72) Inventor Koji Usuda Komukai-Toshiba, Kawasaki-shi, Kanagawa 1 Incorporated Toshiba Research Laboratories, Inc. (72) Inventor Ichiro Kataeki, Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa 1 Incorporated Toshiba Tamagawa Plant

Claims (2)

[Claims] 1. An intrinsic semiconductor layer formed on a semiconductor substrate of a first conductivity type, and a second semiconductor layer formed on this intrinsic semiconductor layer.
A conductive type base layer, a first insulating layer having an opening formed on a predetermined portion of the base layer, and the base layer and the first insulating layer excluding the opening. A base lead-out portion whose surface is covered with a second insulating layer; a first conductivity type emitter layer formed on the surface of the base layer immediately below the opening; and an intrinsic semiconductor layer directly below the opening. A semiconductor device comprising the formed first conductivity type collector layer. 2. A step of selectively forming a first insulating film on a semiconductor substrate, and a step of anisotropically etching the semiconductor substrate using the first insulating film as a mask to form a first groove. A step of selectively forming a second groove at a predetermined position of the first groove, a step of thermally oxidizing the surfaces of the first and second grooves to form a second insulating film, and C on the second insulating film
A step of forming a third insulating film by a VD method, and the second step
And a step of burying an insulating material in the first trench, and a step of burying an insulator in the first trench.