JP3128818B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a structure of a bipolar transistor having good high-frequency characteristics.

[Prior Art] FIG. 4 shows an example of a conventional bipolar transistor.

In FIG. 4, an N ⁺ type buried layer 2 is formed in a P type silicon substrate 1.
And an N-type epitaxial layer 3 are formed.
, Horizontal element isolation is achieved. Reference numeral 5 denotes a P-type base layer, 6 denotes an N ⁺ -type emitter layer, and 11 denotes an N ⁺ -type extraction layer for extracting a collector from a buried layer. It is connected to the.

The above part is basic, but in this example, in order to increase the speed, the SiO ₂ film 8, which penetrates the P-type base layer 5 and the N ⁺ -type emitter layer 6 inside except for the periphery of the emitter opening, There are nine.

[Problems to be solved by the invention]

However, the structure of the bipolar transistor described above has a problem that the emitter area is small, the current density is high, the effect of extruding the base is likely to occur, and the increase in speed is limited.

[Means for solving the problem]

The semiconductor integrated circuit according to the present invention includes a high-concentration reverse-conductivity-type buried layer formed on a surface of a one-conductivity-type semiconductor substrate, a reverse-conductivity-type epitaxial layer formed on the buried layer, and a layer formed on the epitaxial layer. A semiconductor integrated circuit having a base layer of one conductivity type, an emitter layer of the opposite conductivity type formed on the base layer, and an insulating layer formed through the emitter layer and the base layer. A high-concentration reverse conductivity type impurity layer is provided in contact with the buried layer in the epitaxial layer immediately below the layer.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a sectional view of a first embodiment of the present invention.

In FIG. 1, an N ⁺ -type buried layer 2 and an N-type epitaxial layer 3 are formed on a P-type silicon substrate 1, and a P-type base layer 5 and an N ⁺ -type An emitter layer 6 is formed. And this N ⁺ type emitter layer 6 and through the P-type base layer 5 and SiO ₂ films 8 and 9 are formed, further high concentrations of the N-type epitaxial layer 3 immediately below the SiO ₂ film 8 N ⁺ A mold layer 10 is formed. In FIG. 1, 4 is an oxide film, 7 is an N ⁺ type polysilicon layer, and 11 is
N ⁺ type extraction layer, 12 is a collector electrode, 13 is an emitter electrode, 14
Is a base electrode. At this time, the concentration of the P-type base layer 5 is
10 ¹⁸ cm ^-3 , depth 0.2 μm, depth of N ⁺ type emitter layer 6 is 0.
5 μm, and the bottom of the SiO ₂ film 8 has a depth of 0.3 μm. The concentration of the epitaxial layer is 1 × 10 ¹⁶ cm ³ and the depth is 0.6 μm.

Next, an example of a manufacturing process of the emitter section will be described with reference to FIG.

First, as shown in FIG. 2 (a), an N ⁺ type buried layer 2, an N type epitaxial layer 3, an oxide film 4,
After the formation of the P-type base layer 5, a 0.1 μm-thick SiN film 15 is adhered to the entire surface. Next, the SiN film 15 and the oxide film 4 are etched to form an emitter opening, and a 0.25 μm N ⁺ type polysilicon layer
Grow.

Next, as shown in FIG. 2 (b), the N ⁺ -type polysilicon layer 7 and the epitaxial layer are etched deeper than the bottom of the P-type base layer 5 by anisotropic dry etching. By ion implantation under the condition of × 10 ¹³ cm ⁻² , the N ⁺ -type layer 10 having a concentration of about 10 ¹⁸ cm ⁻³ is formed.

Next, as shown in FIG. 2C, an SiO ₂ film 8 is grown by heat treatment in an oxidizing atmosphere, and simultaneously an N ⁺ -type emitter layer 6 is formed by diffusing impurities from the N ⁺ -type polysilicon layer 7. I do.

Next, as shown in FIG. 2 (d), S
An iO ₂ film 9 is grown so that the upper portion is substantially flat, and then the SiO ₂ films 8 and 9 are etched back as shown in FIG. Thereafter, processing is performed according to a conventional method to complete the transistor shown in FIG.

In FIG. 1, an N ⁺ type layer 10 is provided near the bottom of the P type base layer 5.
Is present, the effect of extruding the base is suppressed, and the high speed of the transistor can be improved by about several tens of percent.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention. In the second embodiment, another N ⁺ -type layer 16 is added to the entire surface immediately below the emitter opening.

In order to provide this N ⁺ type layer 16, for example, before forming the N ⁺ type polysilicon layer 7 in FIG. 2 (a), as shown in FIG. Ions are implanted. Hereinafter, as shown in FIG. 3 (b), a transistor is formed in the same process as described with reference to FIGS. 2 (a) to 2 (e).

According to the second embodiment, there is an advantage that the base extrusion effect can be further suppressed by adding the N ⁺ type layer 16.

〔The invention's effect〕

As described above, the present invention relates to a bipolar transistor having an epitaxial layer, an insulating film penetrating the base layer and the emitter layer inside the periphery except for the periphery of the emitter opening, and an epitaxial layer immediately below the insulating film. By providing a layer having the same conductivity type and a high concentration, the effect of extruding the base can be suppressed, so that a semiconductor integrated circuit capable of operating at higher speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing an example of a conventional semiconductor integrated circuit. 1 ... P-type silicon substrate, 2 ... N ⁺ type buried layer, 3 ... N
... P-type base layer, 6... N ⁺ type emitter layer, 8,9... SiO ₂ film, 10, 16... N ⁺ type layer.

Claims (1)

(57) [Claims] 1. A buried layer of a high concentration opposite conductivity type formed on a surface of a semiconductor substrate of one conductivity type, an epitaxial layer of a reverse conductivity type formed on the buried layer, and a buried layer formed on the epitaxial layer. In a semiconductor integrated circuit having a conductive type base layer, an opposite conductive type emitter layer formed on the base layer, and an insulating layer formed to penetrate the emitter layer and the base layer, A semiconductor integrated circuit, wherein a high-concentration reverse conductivity type impurity layer is provided in contact with the buried layer in the epitaxial layer.