JPS5879735A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS5879735A JPS5879735A JP17803481A JP17803481A JPS5879735A JP S5879735 A JPS5879735 A JP S5879735A JP 17803481 A JP17803481 A JP 17803481A JP 17803481 A JP17803481 A JP 17803481A JP S5879735 A JPS5879735 A JP S5879735A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- substrate
- integrated circuit
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000002265 prevention Effects 0.000 claims 4
- 239000012535 impurity Substances 0.000 abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000000855 fermentation Methods 0.000 description 1
- 230000004151 fermentation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Abstract
Description
【発明の詳細な説明】 本発明は半導体集積回路の構造に関する。[Detailed description of the invention] The present invention relates to the structure of a semiconductor integrated circuit.
半導体集積回路においては、各能動素子間の電気的絶縁
をとる為、素子間分離の技術が用いられている。素子間
分離の方法として、大別してＰＮ接合による方法と、酸
化膜などによる誘電体分離の方法の２通りがある。In semiconductor integrated circuits, element isolation technology is used to provide electrical insulation between active elements. There are two main methods of isolation between elements: a method using a PN junction and a method using dielectric isolation using an oxide film or the like.
ところで、いずれの方法で素子間分離を行なうにしろ、
集積回路に於いて考慮しなければならないのが、集積回
路の基板とコレクタ間との耐圧（以後、ＶＣ−７１１と
いう）である。集積回路を使用する場合、コレクタ側を
最高電位、即ち電源電圧十Ｖｃｃに等しくとり、基板側
を最低電位−Ｖｌｍ又はＯに等しくとる。従って、集積
回路のコレクター基板間の耐圧ＶＣ−１は、最高電位と
最低電位の差ｌ Ｖｃｃ ｌ ＋ ｌ Ｖｕ ｌ又はＶ
ＣＣより余裕をもつ大きさが必要である。また、集積回
路の出力電力を向上させる為には、電流よりむしろ電源
電圧を増加させる方が容易である。この意味からもｓ
ｖｃ−ａはできる限り大きいことが望ましい。しかし、
従来の誘電体分離による集積回路の製造方法では、以下
に示すように、大きな耐圧を得ることは困難である。By the way, whichever method is used to isolate elements,
What must be considered in integrated circuits is the withstand voltage (hereinafter referred to as VC-711) between the substrate and collector of the integrated circuit. When using an integrated circuit, the collector side is set equal to the highest potential, ie, the power supply voltage 10 Vcc, and the substrate side is set equal to the lowest potential -Vlm or O. Therefore, the breakdown voltage VC-1 between the collector substrates of an integrated circuit is the difference between the highest potential and the lowest potential l Vcc l + l Vu l or V
A size with more margin than CC is required. Furthermore, in order to improve the output power of an integrated circuit, it is easier to increase the power supply voltage rather than the current. In this sense, s
It is desirable that vc-a be as large as possible. but,
In the conventional method of manufacturing an integrated circuit using dielectric separation, it is difficult to obtain a large withstand voltage as described below.
従来の半導体集積回路について帛１図を用いて説明する
。これは酸化膜分離法を用いた集積回路の一例であり、
分離用フィールド醗化Ｉ！１、コレクタ電極２、コレク
タ・エピタキシャル層３、チャネル・ストッパー用Ｐ型
不純物層４．Ｐ型基板５、Ｎ型不純物の埋込層６および
基板側電極７を有する。A conventional semiconductor integrated circuit will be explained using FIG. This is an example of an integrated circuit using the oxide film separation method.
Separation field fermentation I! 1. Collector electrode 2, collector epitaxial layer 3, P-type impurity layer for channel stopper 4. It has a P-type substrate 5, an N-type impurity buried layer 6, and a substrate-side electrode 7.
各々の層の不純物濃度は、Ｐ型基板５が最も低濃度で、
次いでエピタキシャル層３、チャネルストッパ層４の順
であり、埋込層６が最高濃度となるようにされている。The impurity concentration of each layer is the lowest in the P-type substrate 5,
Next, the epitaxial layer 3 and the channel stopper layer 4 are formed in this order, with the buried layer 6 having the highest concentration.
ＰＮ接合の耐圧は、接合を形成する対立する導電型の領
域の不純物濃度、特にその低濃度側の不純物濃度及び接
合の形状で決定される為、コレクタ・基板間の耐圧ＶＣ
−１は、埋込層６とＰ型基板５とではなく埋込層６とＰ
型基板より高濃度のチャネル・ストッパ４とで主として
決定されてしまう。チャネル・ストッパ濃度はチャネル
防止の為、１０”３−”程度の濃度を維持する必要があ
り、従って、コレクタ・基板間の耐圧ＶＣ−Ｓは１０〜
１５Ｖの比較的低い耐圧しかとれない。その結果、使用
する電源電圧も制限され、集積回路の出力電力も制限を
うける。The breakdown voltage of a PN junction is determined by the impurity concentration of the regions of opposing conductivity types that form the junction, especially the impurity concentration on the lower concentration side, and the shape of the junction, so the breakdown voltage between the collector and the substrate VC
-1 is not the buried layer 6 and the P type substrate 5, but the buried layer 6 and the P type substrate 5.
This is mainly determined by the channel stopper 4 having a higher concentration than the mold substrate. The channel stopper concentration needs to be maintained at about 10"3-" to prevent the channel, and therefore the withstand voltage VC-S between the collector and the substrate is 10~
It can only withstand a relatively low voltage of 15V. As a result, the power supply voltage that can be used is also limited, and the output power of the integrated circuit is also limited.
本発明は、従来の欠点を改着し、コレクタ・基板間の耐
圧ＶＣ−８を向上させることができる集積回路を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that can correct the conventional drawbacks and improve the withstand voltage VC-8 between the collector and the substrate.
以下に図面を用いてその一実施例を詳細に説明する。One embodiment will be described in detail below with reference to the drawings.
まず、＠２図（ａ） においてＰ型シリコン基板８に埋
込層を形成する前に、あらかじめ、チャネル・ストッパ
の濃度より１〜２ケタ小さい濃度でＮ型不純物層９を形
成する。その後、高濃度であるが拡散深さは、Ｎ型不純
物層９より浅い、Ｎ型不純物の埋込層１ｏを形成する（
同図ｂ）。しがる後Ｎ型をドープしたエピタキシャル層
１１を成長させ、フィールド酸化膜を形成すべき部位の
表面のシリコンをエツチングする（同図ｅ）。チャネル
ストッパ１２としてＰ型不純物を１〜２ Ｘ １０ｊ６
備 の濃度で拡散し、９００〜９５０℃程度の温度で高
圧酸化を行ない、厚い酸化ｙ！１３を形成する（同図ｄ
）。しかる後１通常のベース、エミッタ、コレクタ形成
工程及び電極工程によって、集積回路を完成する。First, in Figure 2 (a), before forming a buried layer in a P-type silicon substrate 8, an N-type impurity layer 9 is formed in advance at a concentration one to two orders of magnitude lower than that of the channel stopper. Thereafter, a buried layer 1o of N-type impurity is formed, which has a high concentration but a shallower diffusion depth than the N-type impurity layer 9.
Figure b). After that, an N-type doped epitaxial layer 11 is grown, and the silicon on the surface of the area where the field oxide film is to be formed is etched (see e in the figure). 1 to 2 P-type impurities as channel stopper 12 x 10j6
It is diffused at a concentration of 1,000 yen, and high-pressure oxidation is performed at a temperature of about 900 to 950°C to form a thick oxidized y! 13 (see figure d)
). Thereafter, the integrated circuit is completed through the usual base, emitter, and collector forming steps and electrode steps.
この実施例によれば、コレクタ・基板間の耐圧は、低濃
度のＮ型不純物層９とＰＷ基板８の不純物濃度とで決定
されるから、従来に比べ、約１０倍以上の耐圧ＶＣ−ａ
が得られる。According to this embodiment, the breakdown voltage between the collector and the substrate is determined by the low concentration N-type impurity layer 9 and the impurity concentration of the PW substrate 8, so the breakdown voltage VC-a is about 10 times or more compared to the conventional one.
is obtained.
以下にその更に詳しい実施例を第３図を用いてその工程
順に説明する。Ｐ型基板１４表面に絶縁膜１５を成長さ
せ、選択的に開口１６を設け、Ｎｍ不純物ヲ１ ｘ １
０１４〜１ ｘ、 １０１１ｓｃａｒ−３程ｆｊｌ拡散
スる（＆）。ウェハー表面に更に絶縁膜１７を成長させ
開口１６内にそれより小さな開口部１８を選択的に設け
た後、高濃度のＮ型不純物を拡散して埋込層１９を形成
する（ｂ）。該ウェハー表面の絶縁膜を全面除失した後
、Ｎ型不純物をドープした８１Ｈ。A more detailed embodiment will be explained below in the order of its steps with reference to FIG. An insulating film 15 is grown on the surface of the P-type substrate 14, an opening 16 is selectively formed, and Nm impurities are added 1 x 1.
014~1x, 1011scar-3 fjl diffusion (&). After further growing an insulating film 17 on the wafer surface and selectively providing smaller openings 18 within the openings 16, a buried layer 19 is formed by diffusing N-type impurities at a high concentration (b). After completely removing the insulating film on the wafer surface, 81H was doped with N-type impurities.
岬でシリコン単結晶層１９を成長させ％酸化に対してマ
スクとなる窒化膜２０及び増化膜層２１を成長させる（
Ｃ）。しかるのち、フィールド酸化膜を一形成すべき部
位のシリコンを選択的にエツチングし、Ｐ型不純物を２
Ｘ １０１６ｃａｒ−３程度の濃度で拡散し、チャネ
ル・ストッパー２２を形成する（ｄ）。A silicon single crystal layer 19 is grown at the cape, and a nitride film 20 and an enhanced film layer 21 are grown to serve as a mask against oxidation (
C). After that, the silicon in the area where the field oxide film is to be formed is selectively etched, and the P-type impurity is removed by etching.
It diffuses at a concentration of about X 1016 car-3 to form the channel stopper 22 (d).
骸ウェハーを９００〜９５０℃で高圧酸化を行ない、１
．５μｍ程度のフィールド酸化膜２３を形成した後、コ
レクタ・フンタクトとなるべき部分２４を選択的に開口
し、埋込層に達するようにＮ型不純物の高濃度拡散を行
なう（・）。更に、ベースを開口し、イオン注入などで
Ｐ型不純物を注入してペース２５を形成した後、酸化膜
などの絶縁層を成長させ、エミッタ２６、ベース・コン
タクト２７及びコレクタ・コンタクト２８を関口する（
ｆ）。該ウェハー表面上にヒ素を高濃度にドープした多
結晶シリコン層を成長させ、エミッタ及びコレクタコン
タクト部のみを憶して、選択的にエツチングＬ、たＬ
１０００℃程度で拡散し、工ｔツタ２９１コレクタ・コ
ンタクト３ｏを形成する（ｇ）。更にボロンなどのＰ型
不純物を９００１：程度で、短時間拡散してペース・コ
ンタクト３１を形成する（ｈ）。The skeleton wafer is subjected to high pressure oxidation at 900 to 950°C, and 1
．． After forming a field oxide film 23 of about 5 .mu.m, a portion 24 which is to become a collector substrate is selectively opened, and N-type impurities are diffused at a high concentration so as to reach the buried layer (.). Furthermore, after opening the base and injecting P-type impurities by ion implantation or the like to form a paste 25, an insulating layer such as an oxide film is grown to form an emitter 26, a base contact 27, and a collector contact 28. (
f). A polycrystalline silicon layer doped with a high concentration of arsenic is grown on the wafer surface, and selectively etched L and L, leaving only the emitter and collector contacts.
It is diffused at about 1000° C. to form the collector contact 3o of the ivy 291 (g). Furthermore, a P-type impurity such as boron is diffused for a short period of time to form a pace contact 31 (h).
皺ウェハーにアル之ニウムなどの金属を積層し、工主ツ
タ、ペース・コンタクト、コレクタ・コンタクトを残し
て選択的にエツチングし、電極３２を形成すれば、集積
回路の製造工程は完了する（１）。The integrated circuit manufacturing process is completed by laminating a metal such as aluminum on a wrinkled wafer and selectively etching it leaving the main vine, pace contact, and collector contact to form the electrode 32 (1). ).
以上の工程によって作成された半導体集積回路は、チャ
ンネルストッパー２２とコレクタ埋込層１９との間に、
低濃度のＮ″′層１６が設けられているため、高耐圧の
集積回路素子を得ることができる。In the semiconductor integrated circuit produced by the above steps, between the channel stopper 22 and the collector buried layer 19,
Since the low concentration N'' layer 16 is provided, an integrated circuit element with high breakdown voltage can be obtained.
第１図は従来の酸化膜分離を用いた集積回路の断面図で
ある。
１−フィールド酸化膜、２−コレクタ引出電極、３−コ
レクタ・エピタキシャル層、４−チャネルストッパ層、
５−Ｐ型基板、６−埋込層、７−基板側電極。
第２図（ａ）〜（ｄ）は夫々本発明の一実施例の集積回
路の主要工程における断面図である。
８−Ｐ型基板、９−低濃度のＮ型不純物領域、１Ｏ−ｊ
ｌｌ込層、１１−Ｎ型エピタキシャル層、１２−チャネ
ル・ストッパ領域、１３−フィールド酸化膜。
第３図（ａ）〜（１）は本発明の一実施例による集積回
路の製造工程を詳細に示す断面図である。
１４−Ｐ型基板、１５−絶縁膜、１６−開口部、１７−
絶縁膜、１８−関口部、１９−埋込層、２〇−酸化膜、
２１−窒化膜、２２−チャネル・ストッパ領域、２３−
フィールド酸化膜、２４゜２８．３０−コレクタ番コン
タクト、２５−ペース、２６．２９−エミツタ・コンタ
クト、２７゜３１−ベース・コンタクト、３２−引出し
電極。
（Ｃ）
）
第２図
（Ｃ）
（ｅ） ｆｙＪ領FIG. 1 is a cross-sectional view of an integrated circuit using conventional oxide isolation. 1-field oxide film, 2-collector extraction electrode, 3-collector epitaxial layer, 4-channel stopper layer,
5-P type substrate, 6-buried layer, 7-substrate side electrode. FIGS. 2(a) to 2(d) are sectional views showing main steps of an integrated circuit according to an embodiment of the present invention. 8-P type substrate, 9-Low concentration N type impurity region, 1O-j
11-N type epitaxial layer, 12-channel stopper region, 13-field oxide film. FIGS. 3(a) to 3(1) are cross-sectional views showing in detail the manufacturing process of an integrated circuit according to an embodiment of the present invention. 14-P type substrate, 15-insulating film, 16-opening, 17-
Insulating film, 18-Sekiguchi part, 19-buried layer, 20-oxide film,
21-Nitride film, 22-Channel stopper region, 23-
Field oxide film, 24°28.30-Collector number contact, 25-Pace, 26.29-Emitter contact, 27°31-Base contact, 32-Leader electrode. (C) ) Figure 2 (C) (e) fyJ territory
Claims (1)
数の領域に分離されて形成され、この分離された領域間
の前記半導体基板表面にはチャンネル防止層が形成され
、前記分離された領域内には前記異なる導電型の埋込層
を前記チャンネル防止層に接触することなく形成してい
ることを特徴とする半導体集積回路。Semiconductor layers of different conductivity types are formed on a semiconductor substrate of one conductivity type, separated into a plurality of regions, a channel prevention layer is formed on the surface of the semiconductor substrate between the separated regions, and a channel prevention layer is formed on the surface of the semiconductor substrate between the separated regions, and A semiconductor integrated circuit characterized in that the buried layer of the different conductivity type is formed inside the channel prevention layer without contacting the channel prevention layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17803481A JPS5879735A (en) | 1981-11-06 | 1981-11-06 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17803481A JPS5879735A (en) | 1981-11-06 | 1981-11-06 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5879735A true JPS5879735A (en) | 1983-05-13 |
Family
ID=16041424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17803481A Pending JPS5879735A (en) | 1981-11-06 | 1981-11-06 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5879735A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59213155A (en) * | 1983-05-17 | 1984-12-03 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| WO2000079584A1 (en) | 1999-06-23 | 2000-12-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Semiconductor and manufacturing method for semiconductor |
-
1981
- 1981-11-06 JP JP17803481A patent/JPS5879735A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59213155A (en) * | 1983-05-17 | 1984-12-03 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH0348662B2 (en) * | 1983-05-17 | 1991-07-25 | Mitsubishi Electric Corp | |
| WO2000079584A1 (en) | 1999-06-23 | 2000-12-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Semiconductor and manufacturing method for semiconductor |
| EP1188185A1 (en) * | 1999-06-23 | 2002-03-20 | Infineon Technologies AG | Semiconductor and manufacturing method for semiconductor |
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