JPH0855999A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of processes greatly during manufacturing by eliminating an isolation region by constituting a device of a series diode which is formed by connecting diodes in series by p-n junction inside one chip. CONSTITUTION:An n-type epitaxial growth layer 2 is provided to an upper surface of a p-type semiconductor substrate 1 and a first diode 3a is formed lengthwise by a p-n junction 3 between the semiconductor 1 and the epitaxial growth layer 2. A p-type region 4 is provided inside the epitaxial growth layer 2, an n-type region 5 is provided inside the p-type region 4 and a second diode 6a is formed lengthwise by a p-n junction 6 between the p-type region 4 and the n-type region 5. A first electrode 7 is provided to both regions of the epitaxial growth layer 2 and the p-type region 4, a second electrode 8 is provided to the n-type region 5 and a third electrode 9 is provided to a lower surface of the semiconductor substrate 1. Since the device does not have an isolation region, the number of processes during manufacturing can be greatly reduced and a manufacturing period can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device which is composed of a series diode in which diodes are connected in series within one chip, which can significantly reduce the number of manufacturing steps and at the same time achieve miniaturization.

[0002]

2. Description of the Related Art Generally, a series diode is composed of two diodes connected in series, and electrode terminals connected to the connection point and both ends thereof. Used in rectifier circuits such as rectifier circuits.

FIG. 8A shows a cross-sectional view of a conventional series diode having two pn junctions, and FIG. 8B shows an equivalent circuit diagram of the series diode of FIG. 8A. It is shown. The series diode shown in FIG. 8A is manufactured as follows. First, p
-Type epitaxial growth layer 2 on type-type semiconductor substrate 21
2 is formed, and a photolithography process including exposure, development, etching, etc., on the epitaxial growth layer 22,
By introducing impurities to a depth reaching the semiconductor substrate 21 by an ion implantation process or a diffusion process, p
A mold isolation region 23 is formed. Further, a p-type region 24 is formed by impurity diffusion in the second well 22b of the epitaxial growth layer 22 partitioned by the isolation region 23. Furthermore, the p-type region 24
The electrodes 25, 26 and 27 are formed on the respective surfaces of the first well 22a, the isolation region 23 and the second well 22b of the epitaxial growth layer 22 in which the p-type region 24 is not formed, and the surface of the p-type region 24. Is provided. As a result, the first diode 28a formed of the first pn junction 28 between the first well 22a of the epitaxial growth layer 22 and the isolation region 23,
And a second diode 29a formed of a second pn junction 29 between the second well 22b of the epitaxial growth layer 22 in which the p-type region 24 is formed and the p-type region 24 is connected in series, and at the connection point thereof. The structure is such that the electrode 26 and the electrodes 25 and 27 are formed on both ends, respectively.

Reference numeral 30 is an n ⁺ type region having a high impurity concentration formed to obtain ohmic contact between the electrodes 25 and 26, 31 is a silicon oxide film, and 32 is a silicon nitride film as a passivation film.

[0005]

However, when the epitaxial growth layer 22 is partitioned at a predetermined position on the semiconductor substrate 21 by the isolation region 23, first, the surface of the epitaxial growth layer 22 is covered with a silicon oxide film, and the An opening is provided in the silicon oxide film through a photolithography process such as applying a resist, exposing, developing, and etching, and then, about 10 processes including the introduction of impurities by ion implantation and the diffusion process, a large number of processes are required. It will take 1-2 days more work. Therefore, there is a problem that the manufacturing cost becomes high.

The present invention has been made in order to solve such a problem, and by eliminating the isolation region, the number of steps can be significantly reduced during manufacturing, and the manufacturing time and manufacturing cost can be reduced. It is an object of the present invention to provide a semiconductor device which can be miniaturized at the same time.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
(A) A second conductivity type epitaxial growth layer is provided on the upper surface of the first conductivity type semiconductor substrate, whereby a first diode formed by a pn junction between the semiconductor substrate and the epitaxial growth layer; ) A region of the first conductivity type is provided in the epitaxial growth layer, and a region of the second conductivity type is further provided in the region of the first conductivity type, so that the region between the first conductivity type region and the second conductivity type region is provided. A second diode formed by the pn junction of
A first electrode provided so as to be connected to both the epitaxial growth layer and the first conductivity type region, and (d) a second electrode provided so as to be connected to the second conductivity type region, e) The third electrode provided on the lower surface of the semiconductor substrate.

The first conductivity type and the second conductivity type are
When the first conductivity type is p-type, the second conductivity type is n-type, and when the first conductivity type is n-type, the second conductivity type is Means p-type.

[0009]

According to the present invention, one diode is formed by the first pn junction between the semiconductor substrate and the epitaxial growth layer, and the second diode is formed by the second pn junction by the diffusion region in the epitaxial growth layer. Since the two diodes are formed to form the series diode, the two diodes are formed in the vertical direction (thickness direction) of the substrate. Therefore, p between the semiconductor substrate and the epitaxial growth layer
The n-junction is formed over the entire chip area, and becomes a semiconductor device having high current and high breakdown voltage for the same chip area. Further, since no isolation region is formed, about 10 steps such as a photolithography step and a diffusion step can be omitted, the construction period can be shortened by about 1 to 2 days, and trial production for examining electrical characteristics can be facilitated.

[0010]

The semiconductor device of the present invention will now be described in detail with reference to the drawings. 1 is a sectional explanatory view showing an embodiment of a semiconductor device of the present invention and its equivalent circuit diagram, FIG.
7 to 7 are cross-sectional explanatory views showing the respective manufacturing steps of the semiconductor device of FIG.

As shown in FIG. 1A, reference numeral 1 is a semiconductor substrate of a first conductivity type (for example, p type), and an epitaxial growth layer of a second conductivity type (for example, n type) is formed on the semiconductor substrate 1. Two are provided. Between the semiconductor substrate 1 and the epitaxial growth layer 2, the first pn in the vertical direction is formed.
The joint 3 is formed. Further, a first conductivity type region 4 is formed in a part of the epitaxial growth layer 2 by impurity diffusion, and a second conductivity type region 5 is further formed in a part of the first conductivity type region 4. A second pn junction 6 is formed between the first conductivity type region 4 and the second conductivity type region 5. The second conductivity type epitaxial growth layer 2 and the first
The conductivity type region 4 is connected by the first electrode 7. Therefore, a series diode in which the first diode 3a formed of the first pn junction 3 and the second diode 6a formed of the second pn junction 6 are connected in series is formed, and the first diode is formed at the connection point of both diodes. Electrode 7 is provided, the second electrode 8 is provided on the cathode side (second conductivity type region 5) of the second diode 6a, and the third electrode 9 is provided on the anode side (back surface side of the semiconductor substrate 1) of the first diode 3a. Are provided respectively. Reference numeral 10 is a second-conductivity-type high-concentration impurity diffusion region formed to obtain ohmic contact with the first electrode 7, 11 is a silicon oxide film, and 12
Is a silicon nitride film as a passivation film.

Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

First, as shown in FIGS. 2 to 3, p-type impurities such as boron or gallium are contained in the amount of 10 ¹⁸ to 10 ¹⁹ /.
500-700 doped with an impurity concentration of about cm ³
By performing epitaxial growth on a semiconductor substrate 1 having a thickness of about μm while doping an n-type impurity such as phosphorus or arsenic to an impurity concentration of about 10 ¹⁴ to 10 ¹⁶ / cm ³ , 10 to 30 μm is obtained. An epitaxial growth layer 2 having a thickness of about 2 is formed.

Next, as shown in FIG. 4, a silicon oxide film 11 having a thickness of about 1 μm is formed on the entire surface of the epitaxial growth layer 2 by a thermal oxidation method or a CVD method, and then the first conductivity type region 4 is formed. The silicon oxide film 11 at the place to be formed is opened by a photolithography process including exposure, development, etching and the like. Next, a thin silicon oxide film is provided to prevent damage to the semiconductor layer due to ion implantation, and ion implantation is performed through the thin silicon oxide film so that the impurity concentration is about 10 ¹⁶ to 10 ¹⁸ / cm ³ and diffusion is performed. First p-type with a depth of about 15 μm
The conductivity type region 4 is formed.

Next, similarly, a silicon oxide film is provided as a mask and, as shown in FIG. 5, 10 ¹⁷ to 10 ²⁰ / c.
so that the impurity concentration of about m ^3, n ⁺ -type impurity diffusion region 10 for ohmic contact to the portion ranging from both the n ⁺ second conductivity type type region 5 and the epitaxial growth layer 2 and the first conductivity type region 4 To form.

After that, as shown in FIG. 6, a contact hole is formed in the impurity diffusion region 10 and the second conductivity type region 5 by a photolithography process, and then a metal such as aluminum is deposited or sputtered. The first electrode 7 is formed by
And the second electrode 8 is provided. Further, as shown in FIG. 7, a silicon nitride film 12 is provided as a passivation film around each electrode and on the entire surface of the silicon oxide film 11. Finally, by providing the third electrode 9 made of metal such as gold on the entire lower surface of the semiconductor substrate 1, the semiconductor device shown in FIG. 1A can be obtained.

[0017]

Since the series diode in the semiconductor device of the present invention does not have an isolation region, it is possible to greatly reduce the number of steps in manufacturing and reduce the manufacturing period, and to reduce the cost of the product. Greatly contribute. Two more diodes are formed vertically,
Since the structure is not laterally arranged as in the conventional case, a pn junction forming a diode can be formed over the entire chip area, a larger amount of current can be applied to the same chip area, and the breakdown voltage can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.

FIG. 8A is a sectional view of a conventional series diode,
(B) is the equivalent circuit diagram.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial growth layer 3 1st pn junction 3a 1st diode 4 1st conductivity type area 5 2nd conductivity type area 6 2nd pn junction 6a 2nd diode 7 1st electrode 8 2nd electrode 9th 3 electrodes

Claims (1)

[Claims] 1. (a) A first conductivity type semiconductor substrate is provided with an epitaxial growth layer of a second conductivity type on an upper surface thereof, whereby a first pn junction is formed between the semiconductor substrate and the epitaxial growth layer. A diode,
(B) The first conductivity type region is provided in the epitaxial growth layer, and the second conductivity type region is further provided in the first conductivity type region, whereby the first conductivity type region and the second conductivity type region are formed. A second diode formed by a pn junction between the two, and (c) a first diode provided so as to be connected to both the epitaxial growth layer and the first conductivity type region.
A semiconductor device comprising an electrode, (d) a second electrode provided so as to be connected to the second conductivity type region, and (e) a third electrode provided on the lower surface of the semiconductor substrate.