JPS6347972A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6347972A JPS6347972A JP19346386A JP19346386A JPS6347972A JP S6347972 A JPS6347972 A JP S6347972A JP 19346386 A JP19346386 A JP 19346386A JP 19346386 A JP19346386 A JP 19346386A JP S6347972 A JPS6347972 A JP S6347972A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- schottky junction
- schottky
- diodes
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置、特に全波整流回路をワンチップ内
に構成した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a full-wave rectifier circuit is constructed on one chip.
（ロ）従来の技術
一般にダイオードブリッジ回路装置を製作する際、複数
のダイオードチップをリードの表裏面に接着し、更に各
チップの表面に別のリードを接着する構成であったり、
更には前記リードの重なりによる短絡や製造法の困難性
の問題を解決した特開昭６０−１０１９５８号公報の如
き構成の半導体装置があった。(b) Conventional technology Generally, when manufacturing a diode bridge circuit device, a plurality of diode chips are bonded to the front and back surfaces of a lead, and another lead is bonded to the surface of each chip.
Furthermore, there was a semiconductor device having a structure as disclosed in Japanese Patent Laid-Open No. 60-101958, which solved the problems of short circuits caused by overlapping leads and difficult manufacturing methods.
（ハ）発明がｍ決しようとする問題点
前述の如き構成に於いては、４チツプのダイオードかま
たはカソード・コモンとアノード・コモンのダイオード
チップを使用して構成する必要があり、更には夫々のチ
ップをリードに半田付けする必要があるため、工程数が
多く、また工程が複雑であった。(c) Problems to be Solved by the Invention In the above-mentioned configuration, it is necessary to use four diode chips or cathode common and anode common diode chips. Because it is necessary to solder the chip to the leads, the number of steps is large and the process is complicated.
また前述の構成では各チップの特性を整える必要がある
問題点を有していた。Furthermore, the above-mentioned configuration has a problem in that it is necessary to adjust the characteristics of each chip.
（ニ）問題点を解決するための手段
本発明は上述した問題点を解決するために、少なくとも
一導電型の半導体基板（２）と、該半導体基板（２）内
に形成される高不純物濃度の一導電型の分離拡散領域（
３）と、前記半導体基板（２）上に形成される第１の絶
縁膜（４）と、該第１の絶縁膜（４）を介して前記半導
体基板（２）とショットキ接合される第１および第２の
ショットキ接合電極（５）（６）と、該第１および第２
のショットキ接合電極（５）（６）とオーミックコンタ
クトする一導電型の第１および第２のシリコン層（１１
）（１２）と、該第１および第２のシリコンｆｆｍ＞（
１２）上に夫々形成される一導電型の第３および第４の
シリコン層（１３）（１４）と、前記第１および第２の
ショットキ接合電極（５）（６）、第１および第２のシ
リコン層（１１０１２）、第３および第４のシリコン層
（１３）（１４）を分離する第２の絶縁膜（１５）と、
前記第３および第４のシリコン層（１３）（１４）とシ
ョットキ接合する電極（１６）と、前記半導体基板（２
）底面にオーミックコンタクトする電極（９）とにより
解決するものである。(d) Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate (2) of at least one conductivity type and a high impurity concentration formed in the semiconductor substrate (2). Isolated diffusion region of one conductivity type (
3), a first insulating film (4) formed on the semiconductor substrate (2), and a first Schottky bonded to the semiconductor substrate (2) via the first insulating film (4). and second Schottky junction electrodes (5) (6), and the first and second Schottky junction electrodes (5) (6);
The first and second silicon layers (11) of one conductivity type are in ohmic contact with the Schottky junction electrodes (5) (6) of
)(12) and the first and second silicon ffm>(
12) third and fourth silicon layers (13) (14) of one conductivity type formed thereon, the first and second Schottky junction electrodes (5) (6), the first and second a second insulating film (15) separating the silicon layer (11012) and the third and fourth silicon layers (13) and (14);
An electrode (16) that makes a Schottky junction with the third and fourth silicon layers (13) (14), and the semiconductor substrate (2).
) The electrode (9) makes ohmic contact with the bottom surface.
（＊〉作用
カソード・コモン（またはアノード・コモン）の構成の
ショットキ・バリア・ダイオード（７）（８）を半導体
基板（２）と第１および第２のショットキ接合電極（５
）（６）で左右対称に形成する。更には前記カソード・
コモン（またはアノード・コモン）の構成のショットキ
・バリア・ダイオード（７）（８）の上に、第３および
第４のシリコンＪＷ （１３）（１４）とショットキ接
合％Ｅｉ（１６）とを形成することでアノード・コモン
（またはカソード・コモン）の構成のダイオード（１７
）（１８）を左右対称に形成する。(*>Working Schottky barrier diodes (7) (8) with a common cathode (or common anode) configuration are connected to the semiconductor substrate (2) and the first and second Schottky junction electrodes (5).
) (6) to form the left and right sides symmetrically. Furthermore, the cathode
Third and fourth silicon JWs (13) (14) and Schottky junctions %Ei (16) are formed on the Schottky barrier diodes (7) (8) in common (or anode-common) configuration. By doing this, the diode (17
) (18) are formed bilaterally symmetrically.
従って夫々のカソード・コモン（アノード・コモン）と
アノード・コモン（カソード・コモン）のダイオード（
７）と（８）、（１７）とく１８）は左右対称の形で、
左右同時に形成されるため左右のダイオード（７）と（
８）、（１７〉とく１８）の特性のバラツキを小きくで
きる。Therefore, the respective cathode common (anode common) and anode common (cathode common) diodes (
7), (8), (17) and 18) are symmetrical,
Since the left and right diodes are formed simultaneously, the left and right diodes (7) and (
8), (17> and 18) variations in characteristics can be reduced.
更には１チップ化しであるために集積度が向上し、チッ
プを小型化でき、また各電極と端子間をワイヤボンドで
きるので量産に最適で組立工数を減らせコストを低減で
きる。Furthermore, since it is a single chip, the degree of integration is improved and the chip can be made smaller. Furthermore, since each electrode and terminal can be wire-bonded, it is ideal for mass production, reducing assembly man-hours and reducing costs.
（へ）実施例
以下に本発明の半導体装置（１）の実施例を図面を参照
しながら詳述する。(F) Embodiments Below, embodiments of the semiconductor device (1) of the present invention will be described in detail with reference to the drawings.
先ず第１図に示す如く、Ｎ型の半導体基板（２）と、該
半導体基板（２）内に形成されるＮ１型の分離拡散領域
（３）と、前記半導体基板＜２）上に形成される第１の
絶縁膜（４）と、該第１の絶縁膜（４）を介して前記半
導体基板（２）とショットキ接合される第１および第２
のショットキ接合電極（５）（６）とがある。First, as shown in FIG. 1, an N-type semiconductor substrate (2), an N1-type isolation diffusion region (3) formed within the semiconductor substrate (2), and an N1-type isolation diffusion region (3) formed on the semiconductor substrate <2). a first insulating film (4), and first and second insulating films that are Schottky bonded to the semiconductor substrate (2) via the first insulating film (4).
Schottky junction electrodes (5) and (6).
ここで分離拡散領域（３）は熱拡散法やイオン注入法等
で形成され、カソード・コモンの形に形成される２つの
ダイオードをＰＮ接合分離するものであり、他に絶縁層
分離等が考えられる。また第１の絶縁膜（４）は例えば
ＣＶＤ法で形成されるシリコン酸化膜である。更には第
１および第２のショットキ接合電極＜５）（６）はＮ型
の半導体基板（２）とショットキ接合し、例えばモリブ
デンを使用する。Here, the separation diffusion region (3) is formed by thermal diffusion method, ion implantation method, etc., and is used to separate the two diodes formed in the cathode/common shape into a PN junction. It will be done. Further, the first insulating film (4) is, for example, a silicon oxide film formed by a CVD method. Furthermore, the first and second Schottky junction electrodes <5) (6) form a Schottky junction with the N-type semiconductor substrate (2), and are made of, for example, molybdenum.
本構成は本発明の第１の特徴とする点であり、左右対称
にカソード・コモンの形のダイオード（７）（８）が形
成されることにある。（またここではアノード・コモン
の形のダイオードを形成しても良い、）つまり第２図に
示す等価回路のノード■、ノード■、ノード■間に形成
されるダイオード（７＞（８）が形成きれ、第１および
第２の電極（５〉（６）はノード■、ノード■が対応し
、半導体基板（２）の底面部（９）はノード■と対応す
る。従って左右のダイオード（７）（８）を同時に形成
してゆくため左右のダイオード特性が均一となる。This configuration is the first feature of the present invention, and is that the diodes (7) and (8) are formed in a symmetrical cathode-common configuration. (In this case, an anode-common type diode may also be formed.) In other words, the diode (7>(8) formed between the nodes ■, node ■, and node ■ in the equivalent circuit shown in Figure 2) The first and second electrodes (5> (6) correspond to the nodes ■ and node ■, and the bottom part (9) of the semiconductor substrate (2) corresponds to the node ■. Therefore, the left and right diodes (7) Since (8) is formed simultaneously, the characteristics of the left and right diodes become uniform.
ここではシールドメタル電極（１０）が反転防止用に形
成され、更にはアニユラ−・リング（３）が形成されて
いる。Here, a shield metal electrode (10) is formed to prevent reversal, and an annular ring (3) is also formed.
次に前記第１および第２のショットキ接合電極（７）（
８）とオーミックコンタクトするＮ”型の第１および第
２のシリコン層（１１）（１２）と、該第１および第２
のシリコンｆｆ１（１１）（１２＞上に夫々形成される
Ｎ−型の第３および第４のシリコン層（１３）（１４）
と、前記第１および第２のショットキ接合電極（５）（
６）、第１および第２のシリコン層（１１）（１２）、
第３および第４のシリコン層（１３）（１４）を分離す
る第２の絶縁膜（１５）と、前記第３および第４のシリ
コン層（１３）（１４）とショットキ接合する電極（１
６）と、前記半導体基板（２）底面にオーミックコンタ
クトする電極（９）がある。Next, the first and second Schottky junction electrodes (7) (
N'' type first and second silicon layers (11) (12) in ohmic contact with
N- type third and fourth silicon layers (13) (14) formed on the silicon ff1 (11) (12), respectively.
and the first and second Schottky junction electrodes (5) (
6), first and second silicon layers (11) (12),
A second insulating film (15) separating the third and fourth silicon layers (13) (14), and an electrode (1) making a Schottky junction with the third and fourth silicon layers (13) (14).
6) and an electrode (9) that makes ohmic contact with the bottom surface of the semiconductor substrate (2).
ここでシリコン層は予めドープされたものを使用し更に
所定の濃度にイオン注入をしている。また第２の絶縁膜
（１５）はシリコン酸化膜やシリコン窒化膜等が考えら
れ、電極（１６）はモリブデン金属を蒸着することで形
成される。Here, the silicon layer used is doped in advance, and ions are further implanted to a predetermined concentration. Further, the second insulating film (15) may be a silicon oxide film, a silicon nitride film, etc., and the electrode (16) is formed by vapor depositing molybdenum metal.
本構成は本発明の第２の特徴とする点であり、左右対称
にアノード・コモンの形のダイオード（１７）（１８）
が形成されることにある。（またここではカソード・コ
モンの形のダイオードを形成しても良い。）つまり第２
図に示す等価回路のノード■、ノード■、ノード■の間
にダイオード（１７）（１８）が形成され、前記第１お
よび第２のショットキ接合電極＜５）＜６月よノード■
、ノード■が対応し、第３および第４のシリコン層（１
３）（１４）とショットキ接合する電極（１６）がノー
ド■と対応する。This configuration is the second feature of the present invention, in which the diodes (17) and (18) are symmetrically arranged in the form of an anode and a common.
is formed. (Also, a cathode-common type diode may be formed here.) In other words, the second
Diodes (17) and (18) are formed between the nodes ■, node ■, and node ■ in the equivalent circuit shown in the figure, and the first and second Schottky junction electrodes <5) < June y node ■
, node ■ corresponds to the third and fourth silicon layers (1
3) The electrode (16) that forms a Schottky junction with (14) corresponds to node (2).
従って左右のダイオード（１７）（１Ｂ）を同時に形成
できるため特性が均一にできる。Therefore, the left and right diodes (17) and (1B) can be formed at the same time, so that the characteristics can be made uniform.
ここで前記シリコン層はショットキ接合を形成できるも
のであれば良く、レーザ等による再結晶化層でも、ポリ
シリコン層でも良い。しかしポリシリコン層の方が再結
晶化等をしない分形成が容易である。Here, the silicon layer may be any material that can form a Schottky junction, and may be a recrystallized layer using a laser or the like, or a polysilicon layer. However, a polysilicon layer is easier to form since it does not require recrystallization or the like.
（ト）発明の効果
以上の説明からも明らかな如く、半導体基板（２）と第
１および第２のショットキ接合電極（５）（６）で形成
きれたカソード・コモン・ダイオード（７）（８）と、
ショットキ接合電極（１６〉と第３および第４のシリコ
ン層（１３）＜１４）で形成されたアノード・コモン・
ダイオード（１７）（１８）を夫々左右対称に形成し、
更には前記カソード・コモン・ダイオード（７）（８）
、アノード・コモン・ダイオード（１７）（１８）は夫
々左右同時に形成されるために左右のダイオード（７）
と（８）、（１７）とく１８）の特性のバラツキを小さ
くできる。(g) Effects of the invention As is clear from the above explanation, the cathode common diodes (7) (8) formed by the semiconductor substrate (2) and the first and second Schottky junction electrodes (5) (6) )and,
An anode common electrode formed by a Schottky junction electrode (16> and third and fourth silicon layers (13)<14)
The diodes (17) and (18) are formed symmetrically, respectively,
Furthermore, the cathode common diodes (7) (8)
, the anode common diodes (17) and (18) are formed simultaneously on the left and right sides, respectively, so the left and right diodes (7)
Variations in characteristics (8), (17), and (18) can be reduced.
更には１チップ化しであるために集積度が向上できるた
め、チップを小型化にでき、またワイヤボンディングで
きるため組立工数を減らせコストを低減できる。Furthermore, since it is a single chip, the degree of integration can be improved, so the chip can be made smaller, and since wire bonding can be performed, the number of assembly steps can be reduced and costs can be reduced.
またポリシリコン層（１３）（１４）（１６）を使用し
た場合は再結晶化がない分ショットキ接合を容易にする
ことができる。Furthermore, when polysilicon layers (13), (14), and (16) are used, Schottky junctions can be easily formed since there is no recrystallization.
第１図は本発明の実施例である半導体装置の断面図、第
２図は本発明の等価回路図である。
（１）は半導体装置、 （２）は半導体基板、 （３）
は分離拡散領域、 （４）はシリコン酸化膜、 （５）
（６）は第１および第２のショットキ接合電極、（７）
（８）はカソード・コモン・ダイオード、（９）は電極
、 （１０）はシールドメタル１極、 （１１）（１２
）（１３）（１４）は第１乃至第４のシリコン層、 （
１５）はシリコン酸化膜、（１６）はモリブデン電極、
（１７）（１８）はアノード・コモン・ダイオードであ
る。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the present invention. (1) is a semiconductor device, (2) is a semiconductor substrate, (3)
is the isolation diffusion region, (4) is the silicon oxide film, (5)
(6) are the first and second Schottky junction electrodes, (7)
(8) is a cathode common diode, (9) is an electrode, (10) is one shield metal pole, (11) (12)
)(13)(14) are the first to fourth silicon layers, (
15) is a silicon oxide film, (16) is a molybdenum electrode,
(17) and (18) are anode common diodes.
Claims (1)
板内に形成される高不純物濃度の一導電型の分離拡散領
域と、前記半導体基板上に形成される第１の絶縁膜と、
該第１の絶縁膜を介して前記半導体基板とショットキ接
合される第１および第２のショットキ接合電極と、該第
１および第２のショットキ接合電極とオーミックコンタ
クトする一導電型の第１および第２のシリコン層と、該
第１および第２のシリコン層上に夫々形成される一導電
型の第３および第４のシリコン層と、前記第１および第
２のショットキ接合電極、第１および第２のシリコン層
、第３および第４のシリコン層を分離する第２の絶縁膜
と、前記第３および第４のシリコン層とショットキ接合
する電極と、前記半導体基板底面にオーミックコンタク
トする電極とを具備することを特徴とした半導体装置。(1) a semiconductor substrate of at least one conductivity type, a highly impurity-concentrated isolation diffusion region of one conductivity type formed in the semiconductor substrate, and a first insulating film formed on the semiconductor substrate;
first and second Schottky junction electrodes that are in Schottky contact with the semiconductor substrate via the first insulating film; first and second Schottky junction electrodes of one conductivity type that are in ohmic contact with the first and second Schottky junction electrodes; a second silicon layer, third and fourth silicon layers of one conductivity type formed on the first and second silicon layers, the first and second Schottky junction electrodes, the first and second Schottky junction electrodes; a second insulating film that separates the second silicon layer, the third and fourth silicon layers, an electrode that makes Schottky contact with the third and fourth silicon layers, and an electrode that makes ohmic contact with the bottom surface of the semiconductor substrate. A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19346386A JPS6347972A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19346386A JPS6347972A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6347972A true JPS6347972A (en) | 1988-02-29 |
Family
ID=16308422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19346386A Pending JPS6347972A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6347972A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5280194A (en) * | 1988-11-21 | 1994-01-18 | Micro Technology Partners | Electrical apparatus with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device |
| US5403729A (en) * | 1992-05-27 | 1995-04-04 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5521420A (en) * | 1992-05-27 | 1996-05-28 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5557149A (en) * | 1994-05-11 | 1996-09-17 | Chipscale, Inc. | Semiconductor fabrication with contact processing for wrap-around flange interface |
| US6121119A (en) * | 1994-06-09 | 2000-09-19 | Chipscale, Inc. | Resistor fabrication |
| US6355981B1 (en) | 1997-01-24 | 2002-03-12 | Chipscale, Inc. | Wafer fabrication of inside-wrapped contacts for electronic devices |
-
1986
- 1986-08-18 JP JP19346386A patent/JPS6347972A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5280194A (en) * | 1988-11-21 | 1994-01-18 | Micro Technology Partners | Electrical apparatus with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device |
| US5455187A (en) * | 1988-11-21 | 1995-10-03 | Micro Technology Partners | Method of making a semiconductor device with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device |
| US5789817A (en) * | 1988-11-21 | 1998-08-04 | Chipscale, Inc. | Electrical apparatus with a metallic layer coupled to a lower region of a substrate and a metallic layer coupled to a lower region of a semiconductor device |
| US5403729A (en) * | 1992-05-27 | 1995-04-04 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5441898A (en) * | 1992-05-27 | 1995-08-15 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5444009A (en) * | 1992-05-27 | 1995-08-22 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5521420A (en) * | 1992-05-27 | 1996-05-28 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| US5592022A (en) * | 1992-05-27 | 1997-01-07 | Chipscale, Inc. | Fabricating a semiconductor with an insulative coating |
| US5557149A (en) * | 1994-05-11 | 1996-09-17 | Chipscale, Inc. | Semiconductor fabrication with contact processing for wrap-around flange interface |
| US5656547A (en) * | 1994-05-11 | 1997-08-12 | Chipscale, Inc. | Method for making a leadless surface mounted device with wrap-around flange interface contacts |
| US6121119A (en) * | 1994-06-09 | 2000-09-19 | Chipscale, Inc. | Resistor fabrication |
| US6355981B1 (en) | 1997-01-24 | 2002-03-12 | Chipscale, Inc. | Wafer fabrication of inside-wrapped contacts for electronic devices |
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