JPH02184026A - Method of forming semiconductor device - Google Patents

Method of forming semiconductor device

Info

Publication number
JPH02184026A
JPH02184026A JP443489A JP443489A JPH02184026A JP H02184026 A JPH02184026 A JP H02184026A JP 443489 A JP443489 A JP 443489A JP 443489 A JP443489 A JP 443489A JP H02184026 A JPH02184026 A JP H02184026A
Authority
JP
Japan
Prior art keywords
grooves
holes
diffusion
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP443489A
Other languages
Japanese (ja)
Inventor
Hitoshi Kawanabe
川那辺 均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP443489A priority Critical patent/JPH02184026A/en
Publication of JPH02184026A publication Critical patent/JPH02184026A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it hard to cause cracks at a place where an isolating and diffusion part is formed by forming a plurality of grooves or holes at one surface of the place, where the isolating and diffusion part of a semiconductor substrate is formed, and forming a plurality of grooves or holes at the other surface alternately to the said grooves or holes, and then forming an isolating and diffusion part. CONSTITUTION:A plurality of grooves (or holes) 31a and 31b are formed by etching at the upper face of the place to form the isolating and diffusion part of a semiconductor substrate 1. Also, at the lower face too are formed a plurality of grooves (holes) 32a-32c by etching. And the grooves 32a, 32b, and 32c are formed so that the part between the grooves 32a and 32b may be opposed to the groove 31a, and that the part between the grooves 32b and 32c may be opposed to the groove 31b. Hereafter, an isolating and diffusion part 4 is formed at the part where these grooves 31a, 31b, and 32a to 32c are formed.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体装置の形成方法に関し、特に分離拡散
を必要とするブレーナ型のサイリスク、トライアック等
の半導体装置の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device such as a Brehner-type SIRISK or TRIAC that requires separation and diffusion.

〈従来の技術〉 以下、サイリスクの形成方法を例にとり第2図を参照し
つつ従来の技術を説明する。
<Prior Art> Hereinafter, the conventional technology will be explained with reference to FIG. 2, taking as an example a method of forming a cyrisk.

第2図はサイリスタの従来の形成方法を説明するだめの
図面であって、第2図(a)は基板に分離拡散を施した
状態の断面説明図、第2図(b)はこの基板にサイリス
クを形成した後チップに分割した状態の断面説明図であ
る。
FIG. 2 is a diagram for explaining the conventional method of forming a thyristor, and FIG. 2(a) is a cross-sectional view of a state in which separation and diffusion have been performed on a substrate, and FIG. FIG. 3 is an explanatory cross-sectional view of a state in which the cyrisk is formed and then divided into chips.

ブレーナ型のサイリスクを製作するに際しては、基板に
分離拡散部を形成した後に、分離拡散部間にサイリスタ
を形成し、分離拡散部のほぼ中央部分を切断してチップ
状のサイリスクを得ている。
When manufacturing a Brainer-type thyrisk, after forming separation diffusion parts on a substrate, a thyristor is formed between the separation diffusion parts, and a chip-shaped thyrisk is obtained by cutting approximately the center of the separation diffusion part.

ウェーへのサイズが大口径化するに伴い、半導体基板の
板厚寸法が大きくなるので、分離拡散部を形成する時間
も長くかかる。従って、この時間を短縮するために、分
離拡散部を形成しようとする個所に、あらかじめエツチ
ングによって溝を設けてこの個所の厚みを薄くした後に
この個所に分離拡散部を形成している。
As the size of the wafer becomes larger, the thickness of the semiconductor substrate becomes larger, so it takes a longer time to form the separation diffusion section. Therefore, in order to shorten this time, a groove is previously formed by etching at the location where the isolation/diffusion section is to be formed to reduce the thickness of this location, and then the isolation/diffusion section is formed at this location.

即ち、第2図(a)に示すように、N型の半導体基板1
の分離拡散部を形成しようとする個所の両面に、エツチ
ングによって対向した溝3を形成してこの個所の厚さを
薄くしておき、この個所の両面から濃度の大きいP型不
純物を拡散して分離拡散部4を形成している。この後、
第2図(b)に示すように、分離拡散部4間のN型半導
体基板1の下面にアノード部としてP”層11を、上面
にゲート部として24層12を形成する。次いでP゛層
12上の一部にカソード部としてN°層13を形成した
後、P+層11.23層12およびN゛層13にそれぞ
れ接触したアノード電極15、ゲート電極16およびカ
ソード電極17を形成する。最後に、分離拡散部4のほ
ぼ中央部分をダイシング法によって切断してサイリスタ
のチップを得る。なお、2は酸化膜であり、また10は
もとから半導体基板1を構成していたN層である。
That is, as shown in FIG. 2(a), an N-type semiconductor substrate 1
Opposite grooves 3 are formed by etching on both sides of the area where the isolation diffusion part is to be formed to reduce the thickness of this area, and a high concentration P-type impurity is diffused from both sides of this area. A separation/diffusion section 4 is formed. After this,
As shown in FIG. 2(b), a P'' layer 11 is formed as an anode section on the lower surface of the N-type semiconductor substrate 1 between the isolation diffusion sections 4, and a 24 layer 12 is formed as a gate section on the upper surface. After forming the N° layer 13 as a cathode part on a part of the layer 12, an anode electrode 15, a gate electrode 16, and a cathode electrode 17 are formed in contact with the P+ layer 11, the 23 layer 12, and the N′ layer 13, respectively. Then, a thyristor chip is obtained by cutting approximately the central part of the isolation diffusion part 4 by a dicing method.Note that 2 is an oxide film, and 10 is an N layer that originally constituted the semiconductor substrate 1. .

〈発明が解決しようとする課題〉 しかしながら、第2図(a)に示した半導体装置は、半
導体基板1の両面の対向する個所に溝3が設けられてこ
の個所の厚みが薄くなっているから、この個所から割れ
が生じ易い欠点があった。
<Problems to be Solved by the Invention> However, in the semiconductor device shown in FIG. 2(a), grooves 3 are provided at opposing locations on both sides of the semiconductor substrate 1, and the thickness of these locations is reduced. However, there was a drawback that cracks were likely to occur at this location.

本考案は上記事情に鑑みて創案されたものであって、分
離拡散部を短時間に形成することができ、且つ分離拡散
部が形成された個所から割れが生じにくい半導体装置の
形成方法を提供することを目的としている。
The present invention has been devised in view of the above circumstances, and provides a method for forming a semiconductor device that can form an isolation/diffusion section in a short time and is less prone to cracking at the location where the isolation/diffusion section is formed. It is intended to.

〈課題を解決するための手段〉 上記問題点を解決するために本発明の半導体装置の形成
方法は、半導体基板の所定の個所に分離拡散部を形成す
る半導体装置の形成方法において、前記個所の一方の表
面に複数の溝或いは穴を形成し、他方の表面に前記溝或
いは穴と互い違いに配置した複数の溝或いは穴を形成し
た後に前記分離拡散部を形成する。
<Means for Solving the Problems> In order to solve the above-mentioned problems, a method for forming a semiconductor device according to the present invention includes a method for forming a semiconductor device in which an isolation diffusion portion is formed at a predetermined location of a semiconductor substrate. After forming a plurality of grooves or holes on one surface and forming a plurality of grooves or holes arranged alternately with the grooves or holes on the other surface, the separation diffusion section is formed.

〈作用〉 半導体基板の所定の個所の一方の表面に複数の溝或いは
穴を形成し、他方の表面に前記溝或いは穴と互い違いに
配置した複数の溝或いは穴を形成して後に分離拡散部を
形成する。従って、半導体基板の厚さが厚くても分離拡
散に要する時間が短く、また半導体基板が割れにくい。
<Operation> A plurality of grooves or holes are formed on one surface of a predetermined location of a semiconductor substrate, and a plurality of grooves or holes arranged alternately with the grooves or holes are formed on the other surface, and then an isolation diffusion section is formed. Form. Therefore, even if the semiconductor substrate is thick, the time required for separation and diffusion is short, and the semiconductor substrate is difficult to break.

〈実施例〉 以下、図面を参照して本発明の一実施例を説明する。<Example> Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を説明するための断面説明図
であって、第1図(a)は半導体基板に溝奴いは穴を形
成した状態、第1図Φ)は分離拡散部を形成した状態、
第1図(C)はサイリスクを形成した状態、第1図(d
)はチップに分割した状態をそれぞれ示す。なお、従来
の技術で説明したものと同等のものには同一の符号を付
して説明する。
FIG. 1 is a cross-sectional explanatory diagram for explaining one embodiment of the present invention, in which FIG. 1(a) shows a state in which grooves or holes are formed in a semiconductor substrate, and FIG. 1(Φ) shows a separated diffusion state. The state where the part is formed,
Figure 1 (C) shows the state in which Cyrisk is formed, Figure 1 (d)
) indicates the state divided into chips. Note that the same reference numerals are given to the same parts as those described in the related art section.

1はN型の半導体基板であって、この半導体基板1の分
離拡散部を形成しようとする個所の上面に、エツチング
によって複数(本実施例では2個)の溝(或いは穴)3
1a、31bを形成する。また、下面にもエツチングに
よって複数(本実施例では3個)の溝(或いは穴)32
a、 32b 、 32cを形成する。そして、第2図
に示すように、溝32a 、 32b、32cは溝31
a 、 31bと互い違いに配置されているように形成
する。即ち、溝32aと32bの間が溝31aに対向し
ており、溝32bと32cの間が溝31bに対向するよ
うに溝32a 、32bおよび32cを形成する。この
後、これら溝31a 、 31b 、 32a 、 3
2b、32cが形成された部分に、第1図(b)に示す
ように、分離拡散部4を形成する。
Reference numeral 1 denotes an N-type semiconductor substrate, and a plurality of grooves (or holes) 3 (in this example, two) are formed by etching on the upper surface of the semiconductor substrate 1 at a location where an isolation diffusion section is to be formed.
1a and 31b are formed. Also, a plurality of (three in this example) grooves (or holes) 32 are formed on the bottom surface by etching.
a, 32b, and 32c are formed. As shown in FIG. 2, the grooves 32a, 32b, and 32c are
A, 31b are arranged alternately. That is, the grooves 32a, 32b, and 32c are formed so that the space between the grooves 32a and 32b faces the groove 31a, and the space between the grooves 32b and 32c faces the groove 31b. After this, these grooves 31a, 31b, 32a, 3
As shown in FIG. 1(b), a separation/diffusion section 4 is formed in the portion where 2b and 32c are formed.

以後は、第1図(C)に示すように、分離拡散部4間の
N型半導体基板1の下面にアノード部としてP゛層11
を、上面にゲート部としてP”1i12を形成する。次
いでP+層12上の一部にカソード部としてN0層13
を形成した後、P゛層If p”層I2およびN+層1
3にそれぞれ接触したアノード電極15、ゲート電極1
6およびカソード電極17を形成する。最後に、第1図
(d)に示すように、分離拡散部4のほぼ中央部分をダ
イシング法によって切断してサイリスタのチップを得る
。なお、2は酸化膜であり、また10はもとから半導体
基板1を構成していたNNである。
Thereafter, as shown in FIG. 1(C), a P layer 11 is formed as an anode part on the lower surface of the N-type semiconductor substrate 1 between the separation diffusion parts 4.
A P"1i12 is formed on the upper surface as a gate part. Next, a N0 layer 13 is formed as a cathode part on a part of the P+ layer 12.
After forming P′ layer If p” layer I2 and N+ layer 1
3, an anode electrode 15 and a gate electrode 1 in contact with each other.
6 and a cathode electrode 17 are formed. Finally, as shown in FIG. 1(d), a thyristor chip is obtained by cutting approximately the central portion of the separation/diffusion section 4 by a dicing method. Note that 2 is an oxide film, and 10 is a NN that originally constituted the semiconductor substrate 1.

なお、本実施例はサイリスタのチップを形成する方法を
例にとって説明したが、本発明はこれにこだわるもので
はなく、分離拡散部を形成することが必要な全ての半導
体装置の形成方法に適用することができる。
Although this embodiment has been explained using a method of forming a thyristor chip as an example, the present invention is not limited to this and is applicable to any method of forming a semiconductor device that requires the formation of an isolation diffusion section. be able to.

〈発明の効果〉 以上説明したように本発明の半導体装置の形成方法は、
半導体基板の分離拡散部を形成する個所の一方の表面に
複数の溝或いは穴を形成し、他方の表面に前記溝或いは
穴と互い違いに配置した複数の溝或いは穴を形成した後
に分離拡散部を形成する。
<Effects of the Invention> As explained above, the method for forming a semiconductor device of the present invention has the following effects:
A plurality of grooves or holes are formed on one surface of a portion of a semiconductor substrate where an isolation diffusion portion is to be formed, and a plurality of grooves or holes arranged alternately with the grooves or holes are formed on the other surface, and then the isolation diffusion portion is formed. Form.

従って、ウェーハのサイズが大口径化して半導体基板の
板厚寸法が大きくなっても、本発明によれば、半導体基
板に分離拡散部を形成するために不純物を拡散させる深
さが、本発明の方法による溝(或いは穴)を設けない場
合に比べて浅くなるので短時間に分離拡散部を形成する
ことができ、且つ分離拡散部の厚みは従来の溝を形成し
た分離拡散部の厚みよりも大きいので分離拡散部が形成
された個所から割れが生じにくくなる利点がある。
Therefore, even if the diameter of the wafer increases and the thickness of the semiconductor substrate increases, according to the present invention, the depth at which impurities are diffused to form the isolation diffusion portion in the semiconductor substrate can be adjusted according to the present invention. Compared to the case where grooves (or holes) are not provided by this method, the separation and diffusion part can be formed in a short time because it is shallower, and the thickness of the separation and diffusion part is smaller than the thickness of the separation and diffusion part in which conventional grooves are formed. Since it is large, it has the advantage that cracks are less likely to occur at the location where the separation/diffusion section is formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明するための断面説明図
であって、第1図(a)は半導体基板に溝或いは穴を形
成した状態、第1図(b)は分離拡散部を形成した状態
、第1図(C)はサイリスタを形成した状態、第1図(
d)はチッ、ブに分割した状態をそれぞれ示す。第2図
はサイリスクの従来の形成方法を説明するための図面で
あって、第2図(a)は基板に分離拡散を施した状態の
断面説明図、第2図(b)はこの基板にサイリスクを形
成した後チップに分割した状態の断面説明図である。 1 ・・・半導体基板、31a 、31b 、 32a
 、 32b、32c  ・・・溝(或いは穴)、4 
・・・分離拡散部。 特許出廓人  シャープ株式会社
FIG. 1 is an explanatory cross-sectional view for explaining one embodiment of the present invention, in which FIG. 1(a) shows a state in which a groove or hole is formed in a semiconductor substrate, and FIG. 1(b) shows a state in which a groove or hole is formed in a semiconductor substrate, and FIG. Figure 1 (C) shows the state in which the thyristor is formed, Figure 1 (C) shows the state in which the thyristor is formed.
d) shows the state where the image is divided into chips and parts. FIG. 2 is a drawing for explaining the conventional method of forming SIRISK, in which FIG. 2(a) is a cross-sectional explanatory diagram of a state in which separation and diffusion has been performed on a substrate, and FIG. FIG. 3 is an explanatory cross-sectional view of a state in which the cyrisk is formed and then divided into chips. 1...Semiconductor substrate, 31a, 31b, 32a
, 32b, 32c...Groove (or hole), 4
...Separation and diffusion section. Patent distributor Sharp Corporation

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の所定の個所に分離拡散部を形成する
半導体装置の形成方法において、前記個所の一方の表面
に複数の溝或いは穴を形成し、他方の表面に前記溝或い
は穴と互い違いに配置した複数の溝或いは穴を形成した
後に前記分離拡散部を形成することを特徴とする半導体
装置の形成方法。
(1) In a method for forming a semiconductor device in which an isolation diffusion portion is formed at a predetermined location on a semiconductor substrate, a plurality of grooves or holes are formed on one surface of the location, and a plurality of grooves or holes are formed on the other surface alternately with the trenches or holes. 1. A method for forming a semiconductor device, characterized in that the separation diffusion portion is formed after forming a plurality of arranged grooves or holes.
JP443489A 1989-01-11 1989-01-11 Method of forming semiconductor device Pending JPH02184026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP443489A JPH02184026A (en) 1989-01-11 1989-01-11 Method of forming semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP443489A JPH02184026A (en) 1989-01-11 1989-01-11 Method of forming semiconductor device

Publications (1)

Publication Number Publication Date
JPH02184026A true JPH02184026A (en) 1990-07-18

Family

ID=11584134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP443489A Pending JPH02184026A (en) 1989-01-11 1989-01-11 Method of forming semiconductor device

Country Status (1)

Country Link
JP (1) JPH02184026A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994028586A1 (en) * 1993-06-01 1994-12-08 Komatsu Ltd. Semiconductor device having high breakdown strength
FR2785089A1 (en) * 1998-10-23 2000-04-28 St Microelectronics Sa CONSTRUCTION OF INSULATION WALL
EP1111684A1 (en) * 1999-12-24 2001-06-27 STMicroelectronics SA Process for making vertical power components

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994028586A1 (en) * 1993-06-01 1994-12-08 Komatsu Ltd. Semiconductor device having high breakdown strength
FR2785089A1 (en) * 1998-10-23 2000-04-28 St Microelectronics Sa CONSTRUCTION OF INSULATION WALL
EP0997931A1 (en) * 1998-10-23 2000-05-03 STMicroelectronics SA Process for forming an isolating wall in a semiconductor substrate
US6759726B1 (en) 1998-10-23 2004-07-06 Stmicroelectronics S.A. Formation of an isolating wall
EP1111684A1 (en) * 1999-12-24 2001-06-27 STMicroelectronics SA Process for making vertical power components
FR2803101A1 (en) * 1999-12-24 2001-06-29 St Microelectronics Sa PROCESS FOR MANUFACTURING VERTICAL POWER COMPONENTS
US6579782B2 (en) * 1999-12-24 2003-06-17 Stmicroelectronics S.A. Vertical power component manufacturing method

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