JPH01315171A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent cracks and chips on glass passivation at the time of dicing by having a PN junction part which is deeply formed at one face side of a substrate and the depth which reaches the PN junction part at the other face side of the board and providing the board with a mesa channel on which the glass passivation is performed. CONSTITUTION:A P<+>-type layer 12 is formed on the lower side surface of an N-type silicon substrate 1 in the form of approximately a mountain, a deep PN junction part 13 is provided, P<+>-type layers 2, 3 are formed on the upper side surface and the lower side surface on the N-type silicon substrate 1, an N<+>-type impurity is diffused on a part of the surface of these P<+>-type layers 2, 3 and N<+>-type layers 4, 5 are formed respectively. Mesa channels 6 which have the depth reaching the PN junction part 13 on the upper side surface of the substrate shaped in this way are formed and the glass passivation 7 is formed on the surface of the mesa channels 6. Finally main electrodes T1, T2 and a gate electrode G are formed and divided into each chip. Thereby cracks and chips on the glass passivation can be prevented from producing at the time of dicing.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device such as a triac having a high-voltage chip structure.

<Prior Art> FIG. 2 is a cross-sectional view of a conventional triac chip in which a mesa-shaped glass passivation is formed, and a simple explanatory diagram of a method of manufacturing such a chip.

As shown in FIG. 2(a), P'' type impurities are diffused into the upper and lower surfaces of the N type silicon substrate l to form P'' type layers 2 and 3. N° type impurities are diffused into a part of the surface of 3 to form N° type N4 and 5, respectively.

Next, as shown in FIG. 2(b), a mesa-shaped groove 6 is formed in a part of the surface of the P-type layers 2 and 3 by a mesa etching technique, and a mesa-shaped groove 6 is formed in the mesa groove 6 using an electrophoresis method or the like. A glass passivation 7.8 is formed by.

Finally, as shown in FIG. 3(C), the main electrodes T, , T
2 and a gate electrode G are formed and divided into chips by a dicing method.

<Problems to be Solved by the Invention> However, the semiconductor device having the structure shown in FIG. 2(C) has mesa grooves on both the upper and lower sides of the silicon substrate.
The silicon substrate is prone to breakage, and the glass passivation formed on the lower surface of the silicon substrate is cracked or chipped during dicing, which can cause quality deterioration of the silicon substrate.

The present invention has been made in view of the above, and an object of the present invention is to provide a high quality semiconductor device in which the substrate is hard to break and the glass passivation is not cracked or chipped during dicing.

<Means for Solving the Problems> In order to solve the above problems, a semiconductor device of the present invention includes a PN junction formed deeply on one side of a substrate, and a PN junction connected to the PN junction on the other side of the substrate. The mesa groove is provided with a glass passivated mesa groove.

Effect> No cracks, nicks or chips will occur in the glass passivation during dicing.

<Example> An embodiment of the present invention will be described below with reference to FIG.

Components equivalent to those in FIG. 2 are given the same symbols.

As shown in FIG. 1(a), a P' type impurity is diffused into the lower surface of an N type silicon substrate 1 in a substantially chevron shape to form a P' type layer 12, and a deep PNN association 13 is provided. Then the first
As shown in FIG.
and 3 are formed, and N' type impurities are diffused into a part of the surface of these P' type layers 2 and 3 to form N' type layers 4 and 5, respectively.

On the upper surface of the substrate thus formed, a mesa groove 6 having a depth connected to the PN junction 13 is formed as shown in FIG. The glass passivation 7 is formed by et al.

Finally, as shown in FIG. 1(d), main electrodes T1 and T2 and a gate electrode G are formed, and the semiconductor device of this example is completed by dividing into chips by a dicing method.

Although the present embodiment has been described using a triac chip as an example, the present invention is not limited to this, and the present invention can also be applied to a thyrisk chip and the like.

<Effects of the Invention> As explained above, in the semiconductor device of the present invention, since the mesa groove is formed only on one side of the substrate, the strength of the substrate is high and it is difficult to break. Further, since glass passivation is not applied to the other side, there is no occurrence of cracks or chips in the glass passivation during dicing as in the conventional case, and a high quality semiconductor device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG.
Figure 1 (a) shows a state in which a deep PN junction is formed on a silicon substrate, Figure 1 (b) shows a state in which a P' type layer and an N' type layer are formed on a silicon substrate, and Figure 1 (C) shows a state in which a mesa groove is formed. Figure 1 (d) shows the state in which glass passivation is applied to the grooves formed.
) indicates the diced state. FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIG.
Figure 2(c) shows the state in which mesa grooves are formed on the upper and lower surfaces and glass passivation is applied within these grooves. ,
FIG. 2(C) shows the diced state. 1...Silicon substrate, 6...Mesa groove, 7...
・Glass passivation, 13...PN junction. Figure 1 (1,000) Figure 1 (Door 2) - Figure 2

Claims (1)

[Claims] (1) A PN junction formed deeply on one side of the substrate, and a mesa groove formed on the other side of the substrate to a depth connected to the PN junction and subjected to glass passivation. A semiconductor device characterized by: