JPS6380561A - Manufacture of complementary semiconductor device - Google Patents
Manufacture of complementary semiconductor deviceInfo
- Publication number
- JPS6380561A JPS6380561A JP61223732A JP22373286A JPS6380561A JP S6380561 A JPS6380561 A JP S6380561A JP 61223732 A JP61223732 A JP 61223732A JP 22373286 A JP22373286 A JP 22373286A JP S6380561 A JPS6380561 A JP S6380561A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- plane
- vertical
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000000295 complement effect Effects 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000005669 field effect Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシリコン基板に高密度に形成される相補型半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing complementary semiconductor devices formed in high density on a silicon substrate.
近来、半導体デバイスにおける高集積化が進み、低消費
電力かつ高速動作の期待できる相補型半導体装置の構造
に関して多くの提案がなされている。2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, many proposals have been made regarding the structure of complementary semiconductor devices that can be expected to have low power consumption and high-speed operation.
従来、基板平面のみを利用して形成されていた半導体素
子も、縮小化の限界から、基板に溝を掘り、側壁を用い
て素子を縦型構造とする報告がある。Conventionally, semiconductor devices have been formed using only the flat surface of a substrate, but due to the limitations of miniaturization, there are reports of trenches being dug in the substrate and sidewalls being used to form the device into a vertical structure.
たとえば、衣用らにより、第３３回応用物理学関係連合
講演会講演予稿集の５４９ページ３ｐ−Ｑ−１１に発表
された論文において、次の方法が紹介されている。すな
わち、第３図に示すように、ｎ型シリコン基板２１にｎ
ウェル２２とｐウェル２３を形成し、ｎウェル領域に側
壁の結晶面が（１１０）面となるようにシリコンの溝を
形成する。ｐウェル上には通常用いられている平面型の
ｎチャネル電界効果トランジスタを、ｎウェル上には側
壁をチャネルとして用いる縦型のｐチャネル電界効果ト
ランジスタを形成し、相補型半導体装置を構成するもの
である。なお図中、２４は素子を分離するためのＳ １
０２５．２５はｐチャネル電界効果トランジスタのゲー
ト電極、２６はｐ型拡散層であり、２８はｎチャネル電
界効果トランジスタのゲート電極、２７はｎ型拡散眉で
ある。For example, the following method is introduced by Kinyo et al. in a paper published on page 549, 3p-Q-11 of the 33rd Applied Physics Conference Proceedings. That is, as shown in FIG.
A well 22 and a p-well 23 are formed, and a silicon trench is formed in the n-well region so that the crystal plane of the sidewall is the (110) plane. A commonly used planar n-channel field effect transistor is formed on the p-well, and a vertical p-channel field-effect transistor using the sidewall as a channel is formed on the n-well, forming a complementary semiconductor device. It is. In the figure, 24 is S 1 for separating the elements.
025.25 is a gate electrode of a p-channel field effect transistor, 26 is a p-type diffusion layer, 28 is a gate electrode of an n-channel field effect transistor, and 27 is an n-type diffusion layer.
本構造の特徴は、ｐチャネル電界効果トランジスタの電
流駆動能力が（１００）面より （１１０）面の方が大
きいことを利用して相補型半導体装置の動作の高速化を
図るものである。また、ｎチャネル電界効果トランジス
タを縦型とすることで素子の高密度化が可能となる。The feature of this structure is to utilize the fact that the current driving capability of the p-channel field effect transistor is larger in the (110) plane than in the (100) plane to increase the operation speed of the complementary semiconductor device. Further, by making the n-channel field effect transistor vertical, it becomes possible to increase the density of the device.
上述した従来の構造の相補型半導体装置において、ｎチ
ャネル電界効果トランジスタを縦型とすることで高密度
化が図られているが、ｎチャネル電界効果トランジスタ
は平面に形成されているために、高密度化を行う余地が
残されている。また縦型と横型を合わせ持つために、製
造工程中のリソグラフィー工程において問題点がある。In the complementary semiconductor device with the conventional structure described above, high density is achieved by making the n-channel field effect transistor vertical. However, since the n-channel field effect transistor is formed in a plane, high density There is still room for densification. Furthermore, since it has both vertical and horizontal types, there are problems in the lithography process during the manufacturing process.
本発明の目的は、このような問題点を解決した相補型半
導体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a complementary semiconductor device that solves these problems.
本発明の相補型半導体装置の製造方法は、シリコン基板
に、側面の結晶面が（１００）である第１の溝と、側面
の結晶面が（１１０）である第２の溝とを形成し、第１
の溝の前記側面に縦型のｎチャネル電界効果トランジス
タを、第２の溝の前記側面に縦型のｎチャネル電界効果
トランジスタを形成することを特徴としている。The method for manufacturing a complementary semiconductor device of the present invention includes forming in a silicon substrate a first groove whose side surface has a (100) crystal plane and a second groove whose side surface has a (110) crystal plane. , 1st
A vertical n-channel field effect transistor is formed on the side surface of the groove, and a vertical n-channel field effect transistor is formed on the side surface of the second groove.
以下、本発明の第１の実施例について図面を用いて詳細
に説明する。Hereinafter, a first embodiment of the present invention will be described in detail using the drawings.
第１図は、本発明の第１の実施例を説明するための試料
の構造を、主な製造工程における断面および表面を示す
斜視図である。第１図（ａ）において、面方位（１１０
）ｐ型シリコン基板１に、素子を分離するための５ｉ０
２層２を形成し、イオン注入法と熱アニール工程により
ｎウェル３を形成する。FIG. 1 is a perspective view showing the cross section and surface of the structure of a sample in the main manufacturing steps for explaining the first embodiment of the present invention. In Fig. 1(a), the plane orientation (110
) 5i0 for separating elements on p-type silicon substrate 1
Two layers 2 are formed, and an n-well 3 is formed by ion implantation and a thermal annealing process.
次にｎウェル領域では溝側壁の面方位が（１１０）面４
となるように、ｐ型基板領域では溝側壁の面方位が（１
００）面５となるように、深さ約１μｍの垂直形状の溝
を形成すると第１図（ｂ）となる。Next, in the n-well region, the plane orientation of the trench sidewall is (110) plane 4
In the p-type substrate region, the plane orientation of the trench sidewall is (1
When a vertical groove with a depth of about 1 μm is formed so as to form the surface 5 (00), the result is as shown in FIG. 1(b).
次に、溝側壁にゲート絶縁膜を形成した後、溝側面と所
望の表面にゲート電極６を形成し、続いてイオン注入法
によりｎウェル領域のＳｉ表面に高濃度ｐ型拡散層７を
、ｐ型基板領域のＳｉ表面に高濃度ｎ型拡散層８を形成
すると第１図（ｃ）となる。Next, after forming a gate insulating film on the sidewalls of the trench, a gate electrode 6 is formed on the sidewalls of the trench and a desired surface, and then a highly concentrated p-type diffusion layer 7 is formed on the Si surface of the n-well region by ion implantation. When a high concentration n-type diffusion layer 8 is formed on the Si surface of the p-type substrate region, the result is as shown in FIG. 1(c).
以後は、通常用いられる眉間絶縁膜堆積工程およびアル
ミニウム配線工程等を経て、溝側面の結晶面が（１００
）である側面５に縦型のｎチャネル電界効果トランジス
タが、溝側面の結晶面が（１１０）である側面４に縦型
のｎチャネル電界効果トランジスタが形成され、相補型
半導体装置が構成される。Thereafter, the crystal planes on the side surfaces of the grooves are (100
), a vertical n-channel field effect transistor is formed on the side surface 5 whose crystal plane is (110), and a vertical n-channel field effect transistor is formed on the side surface 4 whose crystal plane is (110), forming a complementary semiconductor device. .
次に、本発明の第２の実施例について図面を用いて詳細
に説明する。Next, a second embodiment of the present invention will be described in detail using the drawings.
第２図は、本発明の第２の実施例を説明するための試料
の構造を、主な製造工程における断面および表面を示す
斜視図である。第２図（ａ）において、面方位（１００
）ｐ型シリコン基板１１に、素子を分離するためのＳ
ｉ ０２ 層１２を形成し、イオン注入法と熱アニール
工程によりｎウェル１３を形成する。FIG. 2 is a perspective view showing the cross section and surface of the main manufacturing process of the structure of a sample for explaining the second embodiment of the present invention. In Fig. 2(a), the surface orientation (100
) S on the p-type silicon substrate 11 to separate the elements.
An i 02 layer 12 is formed, and an n-well 13 is formed by ion implantation and thermal annealing.
次にｎウェル領域では溝側壁の面方位が（１１０）面１
４となるように、ｐ型基板領域では溝側壁の面方位が（
１００）面１５となるように、深さ約１μｍの垂直形状
の溝を形成すると第２図（ｂ）となる。Next, in the n-well region, the plane orientation of the trench sidewall is (110) plane 1
4, the plane orientation of the trench sidewall in the p-type substrate region is (
100) When a vertical groove with a depth of about 1 μm is formed so as to form a surface 15, the result is as shown in FIG. 2(b).
次に、溝側壁にゲート絶縁膜を形成した後、溝側面と所
望の表面にゲート電極１６を形成し、続いてイオン注入
法によりｎウェル領域のＳｉ表面に高濃度ｐ型拡散層１
７を、ｐ型基板領域の３ｉ表面に高濃度ｎ型拡散層１８
を形成すると第２図＜ｃ＞となる。Next, after forming a gate insulating film on the sidewalls of the trench, a gate electrode 16 is formed on the sidewalls of the trench and a desired surface, and then a highly concentrated p-type diffusion layer 1 is formed on the Si surface of the n-well region by ion implantation.
7, and a high concentration n-type diffusion layer 18 on the surface of 3i of the p-type substrate region.
When formed, the result is as shown in Fig. 2 <c>.
以後は、通常用いられろ眉間絶縁膜堆積工程およびアル
ミニウム配線工程等を経て、溝側面の結晶面が（１００
）である（！１．１１面１５に本型のｎチャネル電界効
果トランジスタが、溝側面の結晶が（１１０）である側
面１４に縦型のｎチャネル電界効果トランジスタが形成
され、相補型半導体装置が構成される。After that, the crystal planes on the side surfaces of the grooves are (100
) (!1.11 An n-channel field effect transistor of this type is formed on the surface 15, and a vertical n-channel field effect transistor is formed on the side surface 14 where the crystal on the side surface of the groove is (110), thereby forming a complementary semiconductor device. is configured.
以上節１および第２の実施例においては、ｐ型基板でｎ
ウェルを形成したが、ｎ型基板を用いてｎウェルを形成
したものでもかまわない。また、溝の深さを１μｍとし
たが、これに限定するものでなく、また溝の形状は側面
にゲート電界で制御できるチャネルが形成される形状で
あればよい。In Section 1 and the second embodiment above, the p-type substrate is n
Although a well is formed in the above example, an n-well may be formed using an n-type substrate. Further, although the depth of the groove is 1 μm, the present invention is not limited to this, and the shape of the groove may be any shape as long as a channel that can be controlled by a gate electric field is formed on the side surface.
本発明によれば、両導電型電界効果トランジスタともに
縦型とし、しかも素子の駆動能力が大きく、かつ高密度
の相補型半導体装置を製造することができる。According to the present invention, it is possible to manufacture a complementary semiconductor device in which both conductivity type field effect transistors are vertically typed, the element driving capability is large, and the device density is high.
第１図は本発明の第１の実施例の主な製造工程における
断面および表面を示す斜視図、第２図は本発明の第２の
実施例の主な製造工程における断面および表面を示す斜
視図、第３図は従来構造の相補型半導体装置の断面構造
を示す模式図である。
１・・・・・ （１１０）ｐ型Ｓｉ基板２．１２．２４
・・５ＳＯ２層
３．１３．２２ ・・ｎウェル
４．１４ ・・・ （１１０）側面
５．１５ ・・・ （１００）側面
６．１６．２５・・ゲート電極
７．１７ ・・・高濃度ｐ型拡散眉
８．１８ ・・・高濃度ｎ型拡散層
１１・・・・・ （１００）ｐ型Ｓｉ基板２３・・・・
・ｎウェル
２６・・・・・ｐ型拡散層
２７・・・・・ｎ型拡散層FIG. 1 is a perspective view showing the cross section and surface of the main manufacturing process of the first embodiment of the present invention, and FIG. 2 is a perspective view showing the cross section and surface of the main manufacturing process of the second embodiment of the present invention. 3 are schematic diagrams showing the cross-sectional structure of a complementary semiconductor device having a conventional structure. 1... (110) p-type Si substrate 2.12.24
... 5SO2 layer 3.13.22 ... N well 4.14 ... (110) Side surface 5.15 ... (100) Side surface 6.16.25 ... Gate electrode 7.17 ... High concentration P-type diffusion layer 8.18...High concentration n-type diffusion layer 11... (100) P-type Si substrate 23...
・N-well 26...P-type diffusion layer 27...N-type diffusion layer
Claims (1)
る第１の溝と、側面の結晶面が（１１０）である第２の
溝とを形成し、第１の溝の前記側面に縦型のｎチャネル
電界効果トランジスタを、第２の溝の前記側面に縦型の
ｐチャネル電界効果トランジスタを形成することを特徴
とする相補型半導体装置の製造方法。(1) A first groove whose side surface has a (100) crystal plane and a second groove whose side surface has a (110) crystal plane are formed in a silicon substrate, and the side surface of the first groove is A method for manufacturing a complementary semiconductor device, comprising forming a vertical n-channel field effect transistor and a vertical p-channel field effect transistor on the side surface of the second groove.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223732A JPS6380561A (en) | 1986-09-24 | 1986-09-24 | Manufacture of complementary semiconductor device |
| EP19870113917 EP0261666B1 (en) | 1986-09-24 | 1987-09-23 | Complementary type insulated gate field effect transistor |
| DE19873780895 DE3780895T2 (en) | 1986-09-24 | 1987-09-23 | COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH ISOLATED GATE. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223732A JPS6380561A (en) | 1986-09-24 | 1986-09-24 | Manufacture of complementary semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6380561A true JPS6380561A (en) | 1988-04-11 |
Family
ID=16802822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61223732A Pending JPS6380561A (en) | 1986-09-24 | 1986-09-24 | Manufacture of complementary semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380561A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4971926A (en) * | 1984-08-28 | 1990-11-20 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
| JP2005019978A (en) * | 2003-06-04 | 2005-01-20 | Tadahiro Omi | Semiconductor device and its manufacturing method |
| WO2005022637A1 (en) * | 2003-08-28 | 2005-03-10 | Nec Corporation | Semiconductor device having fin-type field effect transistors |
| US7473946B2 (en) | 2006-02-22 | 2009-01-06 | International Business Machines Corporation | CMOS structure and method including multiple crystallographic planes |
| US7649243B2 (en) | 2006-11-06 | 2010-01-19 | International Business Machines Corporation | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof |
| US7652353B2 (en) | 2006-03-24 | 2010-01-26 | Sanyo Electric Co., Ltd. | Semiconductor device |
-
1986
- 1986-09-24 JP JP61223732A patent/JPS6380561A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4971926A (en) * | 1984-08-28 | 1990-11-20 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
| JP2005019978A (en) * | 2003-06-04 | 2005-01-20 | Tadahiro Omi | Semiconductor device and its manufacturing method |
| WO2005022637A1 (en) * | 2003-08-28 | 2005-03-10 | Nec Corporation | Semiconductor device having fin-type field effect transistors |
| US7473946B2 (en) | 2006-02-22 | 2009-01-06 | International Business Machines Corporation | CMOS structure and method including multiple crystallographic planes |
| US7785955B2 (en) | 2006-02-22 | 2010-08-31 | International Business Machines Corporation | CMOS structure and method including multiple crystallographic planes |
| US7652353B2 (en) | 2006-03-24 | 2010-01-26 | Sanyo Electric Co., Ltd. | Semiconductor device |
| US7649243B2 (en) | 2006-11-06 | 2010-01-19 | International Business Machines Corporation | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof |
| US7888780B2 (en) | 2006-11-06 | 2011-02-15 | International Business Machines Corporation | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof |
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