JP2005019978A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same which is improved in its properties such as reduction of interface level between a substrate and insulation films. <P>SOLUTION: In the method of manufacturing a semiconductor device of this invention, gate insulation films are formed on a plurality of crystal planes of a substrate made of silicon by means of plasma deposition. Uniform insulation films made on the surfaces of the substrate having a three dimensional structure suppresses the increase of the interface level between the substrate and the insulation films. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a plurality of crystal planes functioning as transistors, such as a double gate structure and a triple gate structure, and a method for manufacturing the same.

  In recent years, punch-through resistance has been enhanced, and a short channel transistor can be formed. Therefore, semiconductor devices having a double gate structure or a triple gate structure have been proposed. Concavities and convexities are formed on the surface of the silicon substrate, a gate insulating film and a gate electrode are formed on the side surface and the top surface, and the side surface or the silicon substrate surface on the side surface and the top surface is used as a channel of the transistor. A case where two side surfaces are used as a channel is called a double gate structure, and a case where two side surfaces and an upper surface are used as a channel is called a triple gate structure.

  Incidentally, a gate insulating film such as a silicon oxide film is formed on the surface of the substrate, not only in a double gate structure or a triple gate structure but also in a single gate structure. Conventionally, a silicon oxide film by a thermal oxidation method has been formed as a gate insulating film.

However, in a semiconductor device having a double gate structure or a triple gate structure, when a gate insulating film is formed on the substrate surface by heat treatment, the interface state between silicon and the insulating film (Si / SiO ₂ ) is not present in the crystal plane (100). As a result, the quality of the oxide film decreased, and it was difficult to obtain good characteristics as a semiconductor device. Further, there is a problem that an insulating film cannot be uniformly formed on the edge portion of the three-dimensional structure, and a good gate insulating film cannot be obtained.

  The present invention has been made in view of the above situation, and an object thereof is to provide a method for manufacturing a semiconductor device that contributes to improving the characteristics of the semiconductor device, and a semiconductor device manufactured by these manufacturing methods. To do.

  In the method for manufacturing a semiconductor device according to the first aspect of the present invention, a gate insulating film is formed on the surface of the substrate by using plasma for the semiconductor device having a plurality of crystal planes on the surface of the substrate made of silicon. Thereby, an insulating film can be uniformly formed on the surface of a three-dimensional substrate, and an increase in the interface state between the substrate and the insulating film can be suppressed.

  As the gate insulating film, any one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film can be used. In forming the gate insulating film, at least one of krypton (Kr), argon (Ar), and xenon (Xe) can be used as an inert gas.

  When the semiconductor device is a PMOS transistor, the widest surface in contact with the gate insulating film is preferably a (110) surface. On the other hand, when the semiconductor device is an NMOS transistor, the widest surface in contact with the gate insulating film is the (100) surface.

  In the semiconductor device according to the second aspect of the present invention, the NMOS transistor and the PMOS transistor are formed on the same substrate, and a gate insulating film is formed by plasma treatment on the surface of the substrate on which each of the transistors is formed. The widest surface where the PMOS transistor and the gate insulating film are in contact is the (110) surface, and the widest surface where the NMOS transistor and the gate insulating film are in contact is the (100) surface. Preferably, the gate insulating film includes at least one of krypton (Kr), argon (Ar), and xenon (Xe).

  In the method for manufacturing a semiconductor device according to the present invention, a gate insulating film is formed on the surface of a three-dimensional silicon substrate having a plurality of crystal planes as surfaces using plasma. The plasma gate insulating film does not increase the interface state even on a surface having a plurality of crystal planes, and has a uniform film thickness even in a corner portion of a three-dimensional structure. A semiconductor device having good characteristics can be obtained by forming a high-quality gate insulating film by plasma.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

  FIG. 1 shows an example of a schematic configuration of a plasma processing apparatus 10 used in the present invention. The plasma processing apparatus 10 includes a processing container 11 provided with a substrate holder 12 that holds a silicon wafer W as a substrate to be processed. The gas (gas) in the processing container 11 is exhausted from exhaust ports 11A and 11B via an exhaust pump (not shown). The substrate holder 12 has a heater function for heating the silicon wafer W. A gas baffle plate (partition plate) 26 made of aluminum is disposed around the substrate holder 12. A quartz cover 28 is provided on the upper surface of the gas baffle plate 26.

An opening is provided above the processing container 11 so as to correspond to the silicon wafer W on the substrate holder 12. This opening is closed by a dielectric plate 13 made of quartz or Al ₂ O ₃ . A planar antenna 14 is disposed on the top of the dielectric plate 13 (outside the processing container 11). The planar antenna 14 is formed with a plurality of slots for transmitting electromagnetic waves supplied from the waveguide. A wavelength shortening plate 15 and a waveguide 18 are disposed further above (outside) the planar antenna 14. A cooling plate 16 is disposed outside the processing container 11 so as to cover the upper portion of the wavelength shortening plate 15. Inside the cooling plate 16, a refrigerant path 16a through which the refrigerant flows is provided.

  A gas supply port 22 for introducing a gas during plasma processing is provided on the inner side wall of the processing vessel 11. The gas supply port 22 may be provided for each gas to be introduced. In this case, a mass flow controller (not shown) is provided for each supply port as a flow rate adjusting means. On the other hand, the introduced gas may be mixed and sent in advance, and the supply port 22 may be a single nozzle. Although not shown in this case, the flow rate of the introduced gas is adjusted by a flow rate adjusting valve or the like in the mixing stage. Further, a coolant channel 24 is formed inside the inner wall of the processing container 11 so as to surround the entire container.

  The plasma substrate processing apparatus 10 used in the present invention includes an electromagnetic wave generator (not shown) that generates an electromagnetic wave of several gigahertz for exciting plasma. Microwaves generated by the electromagnetic wave generator propagate through the waveguide 18 and are introduced into the processing container 11.

  Using the plasma processing apparatus 10 having the above structure, a gate insulating film (oxide film) according to the present invention is formed on the substrate surface. First, a region where a transistor is to be formed is three-dimensionally formed as convex silicon blocks 52n and 52p by a well-known method, for example, polysilicon film formation by low pressure CVD. A silicon wafer W having silicon blocks 52n and 52p is introduced into the processing container 11 and set on the substrate holder 12. Thereafter, the air inside the processing container 11 is exhausted through the exhaust ports 11A and 11B, and the inside of the processing container 11 is set to a predetermined processing pressure. Next, inert gas and oxygen gas are supplied from the gas supply port 22. As the inert gas, at least one of krypton (Kr), argon (Ar), and xenon (Xe) is used.

  On the other hand, a microwave having a frequency of several GHz generated by the electromagnetic wave generator is supplied to the processing container 11 through the waveguide 18. This microwave is introduced into the processing container 11 through the planar antenna 14 and the dielectric plate 13. High frequency plasma is excited by the microwaves, the reaction gas becomes radicals, and a plasma gate oxide film is formed on the substrate surface of the silicon wafer W. The wafer temperature during the formation of the plasma oxide film is 400 ° C. or lower.

  FIG. 2 shows an outline of a transistor structure of a semiconductor device according to the present invention. In the semiconductor device, an NMOS transistor silicon block 52n in which an NMOS transistor is formed and a PMOS transistor silicon block 52p in which a PMOS transistor is formed are formed in a convex shape on a silicon substrate having the same crystal structure. Gate insulating films 54 are formed on both side surfaces and upper surfaces of these silicon blocks 52n and 52p.

  In the plasma processing apparatus shown in FIG. 1, the gate oxide film was formed by setting the power as 2000 W, the pressure as 57 Pa, the temperature as 400 ° C., the supply gas as argon and oxygen, and the time as 30 seconds. . The film thickness variation σ = 0.67% and the interface state variation σ = 0.66% in a 300 mmφ substrate were obtained. The gate insulating film 54 formed using plasma in the plasma processing apparatus has a uniform film thickness even at the edge portion of the silicon block, and a good insulating film without an increase in interface state due to a difference in crystal plane. Obtained.

  Further, a gate electrode (not shown) is formed on the gate insulating film 54. The transistor is turned on and off by applying an appropriate voltage to the gate electrode. In the on state of the transistor, for example, in FIG. 2, when a source region is formed on the front side of the paper and a drain region is formed on the back side, holes or electrons are perpendicular to the paper surface from the drain to the source. It flows from the side to the near side. Thus, the two side surfaces of the silicon block and the three sides of the upper surface serve as channels, allowing current to flow. Since the three sides are three-dimensionally channeled, there is an advantage that the size of the transistor can be reduced.

  As shown in FIG. 2, the crystal plane in the silicon substrate plane (horizontal plane) direction is the (100) plane, and the crystal plane in the side plane (vertical plane) direction of the silicon blocks 52n and 52p is the (110) plane. The silicon transistor block 52p for the PMOS transistor is designed to have a larger side surface (vertical surface = (110) surface) than the silicon block 52n for the NMOS transistor. Conversely, regarding the area of the upper surface (horizontal plane = (100) plane) of the silicon block, the PMOS transistor silicon block 52p is smaller than the NMOS transistor silicon block 52n.

  The speed of electrons (negative charges) flowing on the (100) plane is about 20% faster than the speed of electrons flowing on the (110) plane. On the other hand, the velocity of holes (positive charge) flowing on the (100) plane is about 1/3 slower than the velocity of holes flowing on the (110) plane. The present invention has been made using such a principle. That is, a structure is adopted in which many holes flow on the (110) plane and many electrons flow on the (100) plane. Here, the crystal plane includes those within a range of ± 8 ° with respect to the crystal axis.

  In this embodiment, the case where the silicon substrate surface is the (100) plane is taken as an example. Therefore, the height of the silicon block 52n where the NMOS transistor is formed is low, but the silicon substrate surface is the (110) plane. In this case, contrary to the case of FIG. 2, the height of the silicon block 52n in which the NMOS transistor is formed is increased. The point is to move holes and electrons more efficiently. Reference numeral 54 in the drawing denotes an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

  When a convex silicon block is formed on a silicon substrate, the upper surface and the side surface on which the silicon block is formed have different crystal axes. Moreover, it is a three-dimensional structure and has a corner part. When a gate oxide film is formed by a conventional thermal oxidation method on different crystal planes having corner portions, there is a drawback that a uniform film thickness cannot be obtained at the corner portions. Further, when compared with the crystal plane (100), the interface state is increased in the crystal plane (110), the quality of the insulating film is lowered, and the threshold voltage of the transistor is different in the crystal plane. However, the gate insulating film 54 formed using plasma by the plasma processing apparatus has a uniform film thickness even at the corner portion of the silicon block, and the crystal plane (110) does not increase the interface state. A good insulating film equivalent to the surface (100) is obtained.

  The present invention relates to a semiconductor device having a three-dimensional channel formation region, in which the channel has a plurality of crystal faces, and the area of the crystal face having a high mobility of electrons or holes among the plurality of crystal faces is increased. A formation region is formed. Furthermore, a good insulating film can be obtained by forming a gate insulating film using plasma on a plurality of crystal surface surfaces, and a high-quality semiconductor device can be obtained.

  The embodiments and examples of the present invention have been described above based on some examples. However, the present invention is not limited to these examples, and the technical aspects shown in the claims are not limited. It can be changed in the category of thought.

It is the schematic (sectional drawing) which shows an example of a structure of the plasma processing apparatus which concerns on this invention. 1 schematically shows a transistor structure of a semiconductor device according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plasma processing apparatus 11 Plasma processing container 18 Waveguide 22 Gas supply port 52n Silicon block for NMOS transistor 52p Silicon block for PMOS transistor 54 Gate insulating film

Claims (13)

  A method for manufacturing a semiconductor device, comprising: forming a gate insulating film on a surface of a substrate made of silicon using a plasma for a semiconductor device having a plurality of crystal planes on the surface of the substrate.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film includes any one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.   3. The method according to claim 1, wherein at the time of forming the gate insulating film, at least one of krypton (Kr), argon (Ar), and xenon (Xe) is used as an inert gas. Semiconductor device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein one of the plurality of crystal faces is a (100) face.   4. The method of manufacturing a semiconductor device according to claim 1, wherein one of the plurality of crystal faces is a (110) face.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of crystal planes include a (100) plane and a (110) plane.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is a PMOS transistor, and the widest surface among the surfaces having the plurality of crystal planes is a (110) plane.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is an NMOS transistor, and the widest surface among the surfaces having the plurality of crystal planes is a (100) plane.   9. The method of manufacturing a semiconductor device according to claim 5, wherein the (110) plane is in a range up to ± 8 °. In a semiconductor device having a plurality of crystal planes on a substrate surface made of silicon,
An NMOS transistor and a PMOS transistor are formed on the same substrate,
Each transistor has a gate insulating film formed by plasma treatment,
2. The semiconductor device according to claim 1, wherein the widest surface of the PMOS transistor in contact with the gate insulating film is a (110) surface, and the widest surface of the NMOS transistor in contact with the gate insulating film is a (100) surface.   The semiconductor device according to claim 10, wherein the gate insulating film includes one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.   The semiconductor device according to claim 10, wherein the gate insulating film includes at least one of krypton (Kr), argon (Ar), and xenon (Xe). The semiconductor device according to claim 10, wherein the (110) plane is in a range up to ± 8 °.

Images