JPS61214457A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To inhibit a diffused junction capacitance between source-drain and a substrate at a small value by implanting ions in order to increase substrate concentration while counter-doping ions so that only an ion implanting layer under a gate region is left. CONSTITUTION:Oxide films (SiO2) 12 having trench structure deeply penetrating in the vertical direction in the surface of a substrate 11 are formed to the substrate 11 in order to isolate each element. The substrate 11 is thermally oxidized to shape a thermal oxide film 13, and the ions of pentavalent atoms such as phosphorus are implanted to the whole surface twice. The ions are implanted by changing over acceleration voltage to a high value for the first time and to a low value for the second time at that time. An ion implanting layer 14 having low concentration (N<->) through the first ion implantation is shaped in depth in the same extent as the bottom of an oxide film 11 for isolating elements, and the depth of ion implanting layers 15 having low concentration (N<->) through the second ion implantation is brought to depth in the same extent as the bottoms of source-drain, 18, 18 formed in a post-process.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same.
It is particularly applied to fine MOS devices that are intended to operate at higher speeds.

(Technical Priority of the Invention) MOS devices have been significantly miniaturized, and recently devices with a diameter of about 2 μm have been put into practical use. The prior art will be described below with reference to FIG. 2 of the accompanying drawings.

In the explanation of FIG. 2, the same elements are indicated by the same reference numerals.

Figure 2 shows a Pchi 1 in a CMOS device with a channel length of approximately 2 μm. FIG. 3 is a cross-sectional view showing the manufacturing process of a channel transistor.

First, an N-type semiconductor substrate 1 made of, for example, silicon is thermally oxidized to form a thermal oxide film 2 on its surface. Next, a nitride film is deposited on the thermal oxide film 2, and the nitride film in other regions (hereinafter referred to as field regions) is removed, leaving the nitride film 3 in the transistor formation region. Then, the entire surface is covered with pentavalent atoms, for example * (P
) is ion-implanted at a low temperature of 1°C to form an oxide film 2 in the field area.
A field ion implantation layer 4 of N'' is provided inside the layer.The above steps result in the state shown in FIG. 2(A).Here,
The field ion implantation layer 4 is provided to prevent the formation of parasitic transistors.

Next, from the state shown in FIG. 2(A), thermal oxidation is performed in, for example, steam. At this time, only the field region is oxidized to cover the nitride lI3, and a thick oxide film 5 is formed there. This field oxide film 5 is formed to a deeper position than the surface of the substrate 1 on which the transistor is formed, so that this transistor is separated from other elements by a distance of 1lIIv. Next, the nitride film 3 and oxide film 2 in the transistor formation region are sequentially removed. In this case, the substrate 1 is exposed only in the transistor formation region, as shown in FIG. 2(B).

Next, a thin oxide film 6 is formed on the surface of the substrate 1 in the transistor formation region, and then pentavalent atoms, such as phosphorus, are ion-implanted into the entire surface. This ion implantation layer 7 is provided at a depth comparable to that of the field ion implantation 114 to increase the impurity concentration of the substrate 1 under the transistor formation region. This state is shown in FIG. 2(C). Here, the ion implantation layer 7 is used firstly to prevent bunch-through between the source and drain when the transistor is formed, secondly to reduce the short channel effect caused by the fine structure, and thirdly to prevent the formation of the transistor. It is provided to set the threshold voltage to an appropriate value.

Once the state shown in FIG. 2(C) is obtained, next, for example, a polycrystalline silicon layer 8 is deposited on the entire surface, leaving only the polycrystalline silicon layer 118 in the center of the transistor formation region.
Other polycrystalline silicon layer 8 is removed. At this time, the remaining polycrystalline silicon layer 8 becomes the gate. The reason for this is the polycrystalline silicon layer 8 for the gate and the left and right field oxide films 5.
, 5, respectively, by thermally diffusing trivalent atoms, such as boron (B), to form P+ layers 9, 9. These P+ layers 9 and 9 serve as the source and drain, respectively, and thus the basic structure of the transistor as shown in FIG. 2(D) is obtained.

[Problems with background technology]

As described above, conventional semiconductor devices are miniaturized according to the scaling law in order to obtain the effects of miniaturization, and as shown in FIG. It is increasing.

This is intended to prevent the occurrence of anomalous transistors, reduce short channel effects, and prevent bunch-through between the source and drain.

However, since the bottoms of the source and drain 9.9 are in contact with the ion implantation layer 7, the resulting diffusion junction capacitance ff1 (parasitic capacitance) increases compared to the case where the ion implantation layer 3.7 is not present. Furthermore, since the ends of the sources and drains 9, 9 are in contact with the field ion implantation layer 3, the resulting diffusion junction capacitance increases. Therefore, the value of the entire diffusion junction capacitance becomes large. Such a large diffusion bonding volume ffi-cell impedes improvement in operating speed accompanying miniaturization. This drawback becomes more significant as the substrate concentration increases in accordance with the scaling law in an attempt to achieve further miniaturization.

(Objective of the Invention) The present invention has been made to overcome the drawbacks of the above-mentioned prior art, and provides a semiconductor device and a method for manufacturing the same that enable high-speed operation by reducing the junction capacitance of the entire device. The purpose is to provide.

[Summary of the Invention] In order to achieve the above object, the present invention realizes transistor isolation (element isolation) using a trench-structured insulator, and insulates a region with a depth similar to the bottom of the element isolation insulator. The present invention provides a semiconductor device in which a high concentration impurity diffusion layer is formed and a low concentration impurity diffusion layer is formed in a region of a predetermined depth below a gate, and a method for manufacturing the same.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings. FIG. 1 is a cross-sectional view showing the manufacturing process of an embodiment in which the present invention is applied to a P-channel transistor of a CMOS device. In the explanation of FIG. 2, the same elements are indicated by the same reference numerals.

In this embodiment, first, for example, a silicon substrate 1
1, as shown in FIG. 1A, an oxide film (S i O 2 ) 12 having a trench structure is formed deeply in the vertical direction of the substrate surface in order to separate each element.

Formation of isolation grooves in such a trench structure can be performed using well-known techniques.

Thereafter, the substrate 11 is thermally oxidized to form a thermal oxide film 13 that will become a gate oxide film on the surface of the substrate. Next, pentavalent atoms such as phosphorus are ion-implanted twice over the entire surface.

At this time, the acceleration voltage is switched high the first time and low the second time. The low concentration (N-) ion implantation layer 14 obtained by the first ion implantation is formed to a depth comparable to the bottom of the element isolation oxide film 11. The depth of the low concentration (N-) layer 15 of 11 ions formed by the second 11 ions is the same as the source and drain 18.18 (Fig.
D) The depth should be about the same as the bottom of (D)). In this way, the state after ion implantation becomes as shown in FIG. 1(B). Note that the ion implantation layer 14 is for preventing parasitic transistors.

Next, polycrystalline silicon 16 is deposited over the entire surface, and except for the polycrystalline silicon 16 in the central part of the transistor forming region, that is, the gate part, the rest is patterned by, for example, photoetching using photoresist 17 as a mask. After that, with the photoresist 17 coated on the remaining polycrystalline silicon 16 (which will become the gate) remaining,
Trivalent atoms, such as boron, are ion-implanted over the entire surface. The ion implantation for this hollow line is performed by implanting ions to the depth of the ion implantation layer 15 described above, and at a low concentration (P-) comparable to that of the ion implantation layer 15. At this time, since the resist 17 blocks ion implantation, the lower ion implantation layer 15 of the gate 16 remains, and the concentration of the other portions of the ion implantation layer 15 is significantly reduced due to this counter doping. Thus, the first
The state 1' shown in Figure (C) is obtained.

Thereafter, trivalent atoms, such as boron, are ion-implanted into the region excluding the gate 16 and then thermally diffused to form P+ layers 18.18 that will become the source and drain.

In this way, the basic structure of transistors 1 to 1 is obtained as shown in FIG. 1(D).

According to the embodiment shown in FIG. 1, since the ion implantation layer 15 is provided below the substrate 11, when the substrate 11 is miniaturized, the impurity concentration can be increased according to the scaling law. Moreover, at that time, source, drain 18.
The ion implantation layer 15 is not provided near the bottom of the substrate 1 .
Since the a degree of 1 is made low, the diffusion junction capacitance can be reduced to a small value. Furthermore, according to this embodiment, element isolation is performed using an insulator having an i-wrench structure.
Field ion implantation li? It is possible to prevent the generation of parasitic transistors without providing i4 (Fig. 2).
It is possible to prevent the occurrence of a large diffusion junction capacitance between the field ion-implanted layer 4 and the sources and drains 9, 9, as shown in FIG. In this way, the overall diffusion junction capacitance can be significantly reduced, thus increasing the V'' operation speed.

Although the above embodiments relate to P-channel transistors, it goes without saying that the present invention can be applied to N-channel transistors. In addition, the above example is 3
Counter-doping of valence atoms is performed using the resist 17 as a mask, but in order to lower the resistance of the polycrystalline silicon layer 16, a metal such as molybdenum is added to the polycrystalline silicon layer 16.
If formed on top, the gold fi layer can be used as a mask.

〔Effect of the invention〕

As described above, in the present invention, ion implantation is performed to increase the substrate concentration, and Goo! - Counterdoping is performed so that only the ion-implanted layer under the region has IA, so the diffusion junction capacitance between the source, drain and substrate can be suppressed to a small value, and device isolation can be achieved using trench-structured insulators. Since the diffusion capacitance caused by the conventional feed ion implantation layer can be reduced, it is possible to provide a semiconductor device and its manufacturing method that can reduce the overall diffusion junction capacitance and improve the operating speed. . Incidentally, if the substrate concentration is reduced by 1/10 by counter-doping, the value of the junction capacitance becomes approximately 173.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional manufacturing process of a semiconductor device. 11... Semiconductor substrate, 12... Oxide film for element isolation,
13... Gate oxide film, 14... Ion implantation layer for preventing parasitic transistors, 15... Ion implantation layer (high a substrate region), 16... Gate polycrystalline silicon, 18° 18... source, drain. Figure 1

Claims (1)

[Scope of Claims] 1. An element isolation groove having a trench structure formed to a predetermined depth to isolate individual MOS transistors on a semiconductor substrate, and a trench structure formed at a depth comparable to the bottom of the element isolation groove. a lightly doped impurity layer of the first conductivity type, a high concentration impurity region of the second conductivity type that is to become the source and drain, and a layer below the gate that is approximately the same depth as the bottom of the high concentration impurity region. A semiconductor device comprising a first conductivity type low concentration impurity layer formed in a region. 2. A first step of forming an element isolation groove in a trench structure at a predetermined depth to isolate individual MOS transistors on a semiconductor substrate, and a position at a depth comparable to the bottom of the element isolation groove; a second step of forming, by ion implantation, a first conductivity type low concentration impurity layer at the same depth as the bottom of the source and drain regions of the MOS transistor; and a shallower layer of the low concentration impurity layer. The above M
a third step of counter-doping a region other than a gate region of an OS transistor with a second conductivity type low concentration impurity by ion implantation.