JPS61194874A - Semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with a separative diffusion layer by a method wherein an one reverse-conductive-type region is used as the channel formation layer for a MOS transistor, the p-n-junction-formation layer for a Zener diode, and the base layer for a bipolar transistor. CONSTITUTION:An n-type epitaxial layer 2 and an n<+> type region 58 are formed on a p-type silicon substrate 1. An n-channel MOS transistor 11 consists of an electrode formed on an oxide film 6, and electrodes 15 and 16 ohmically contacting with n-type regions 55 and 56. In this case, a drain electrode 16 is used also as cathode electrode for the Zener diode, ad a Zener diode 12 consists of a p-type region 4 and the n-type region 56. A bipolar transistor 13 is formed with the n-type region 57 as a emitter, the region 4 as a base, and the layer 2 and region 58 as collectors.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention is a MOS transistor and f-W* that protects it.
ty*p--t I+ r-ノ y I
III rw+y; nrwmut+asx, , a relates to a semiconductor device in which a polar transistor and a Zener diode connected between its base and drain are formed within one semiconductor substrate.

[Prior art and its problems]

In order to protect the MOS transistor from applying excessive voltage between its source and drain, MO3 is connected as shown in Figure 2.
The drain electrode 16 of the I-transistor 11 is connected to the cathode electrode 17 of the Zener diode 12, and the anode electrode 18 of the Zener diode 12 is connected to the MOS transistor 11.
Source electrode 15, emitter electrode 21°, drain electrode 1
The collector electrode 20 of the bipolar transistor 13 is connected to the base 41M electrode 19 of the bipolar transistor 13, and the voltage between the source and drain becomes high and the Zener diode 1
There is a known circuit that turns on the bipolar transistor 13 when the voltage applied between the cathode and the anode of the MOS transistor 2 exceeds the Zener voltage, thereby preventing excessive voltage from being applied between the source and drain of the MOS transistor 11. There is. Such a MOS transistor and its protection circuit are
Conventionally, it has been integrated into a semiconductor device as shown in Figure 3, that is, an n-type epitaxial layer 2 is formed on a p-type silicon substrate 1.
are stacked and divided into several regions by p-type isolation JW3 formed by diffusion. Within this region, p shadow regions 41, 42, and 43 are formed, and within the p@ region 41, two n shadow regions 51, 52 and a p shadow region 42 are formed.
．． One n-type square region 53, 54 is provided in each of the 43. The p shadow region 41 constitutes the n channel MOS l-transistor 11 shown in FIG.
A drain electrode 16 is in contact with the n-type 11 region 52, and a metal gate electrode I4 is provided on the oxide film 6 on the intermediate surface of both electrodes. P shadow region 42 and n type iJ
The f region 53 constitutes the Zener diode 12, and the cathode electrode 17 and the anode electrode 18 are in contact with each other. n
The type epitaxial layer 2 constitutes the collector of the bipolar transistor, the p-type shadow region 43 constitutes the base, and the n-type rectangular region 54 constitutes the emitter, and a collector electrode 20. Base electrode 1
9. Emitter electrode 21 is in contact. Each electrode or each other and metal arrangement! ? 1.72.73.74 as electrode 1
Connect the drain terminal 23 to the wiring connected to the terminal 1i16.1? and an arrangement 472 connected to 20;
Source terminal 24 is connected to wiring 73 connected to electrodes 15 and 21. The arrangement J&I 74 connects the electrodes 18.19 to each other. However, such a configuration is complicated, and the area occupied by the MOS transistor protection circuit in the integrated circuit is large, which has an adverse effect on the economic efficiency of the integrated circuit.

[Purpose of the invention] SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device in which a MOS transistor and its protection circuit consisting of a Zener diode and a bipolar transistor are integrated in an extremely small area of a semiconductor substrate. According to the present invention, a region of another conductivity type formed in a semiconductor layer of one conductivity type, first, second, and third regions of one conductivity type formed within the region; , a gate metal electrode provided via an insulating film on the surface of a region of another conductivity type between the second region of one conductivity type, the first, second and third regions of one conductivity type and the remaining The first, second, third, and fourth metal electrodes are each in ohmic contact with the layer of one conductivity type, and the first electrode is connected to the third electrode, and the second electrode is connected to the fourth electrode, respectively. The above objectives are achieved. [Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 3 are given the same reference numerals. Only one p shadow region 4 is provided in the n type epitaxial layer 2 laminated on the p type silicon substrate l in the same manner as in the case of FIG. Kop
Three n shadow areas 55.56.5 in shadow area 4? , also p
A so-called region 58 outside the shaped area is formed, for example, in the same diffusion step. The metal electrode 14 formed on the oxide film 6 on the intermediate surface of the n-shape region 55, 56 serves as a gate electrode, and the electrodes 15, 16 in ohmic contact with the n-type so-called castles 55 and 56 serve as a source electrode and a drain electrode, respectively. te n channel M
The O5 transistor 11 is constructed, but in this case, the drain 1e Yangsan+1--j tatami-tube-guyen-1.-11
- Embroidery - Also serves as 17) in the figure, p shadow area 4 and n shadow area 56
The Zener diode 12 is configured by the above. The bipolar transistor 13 has an n-type rectangular region 57 as an emitter, a p-shade region 4 as a base, an epitaxial [2] and an n9 region 5
8 as a collector, the electrode in ohmic contact with the n-type N region 57 is the emitter electrode 21, the electrode in ohmic contact with the n''wI region 58 is the collector electrode 20, and the anode electrode of the Zener diode (18 in FIG. ) and the base electrode (19 in FIG. 2) of the bipolar transistor are not required. Therefore, the gate terminal 22 and the electrode 1
By connecting the drain terminal 23 to the electrode 6 and the electrode 20, and the source terminal 24 to the electrode 15 and the electrode 21, the circuit shown in FIG. 2 is integrated. Although the above example uses a p-type substrate, it can also be implemented for a p-channel MO3 transistor and its protection circuit using an n-type substrate with a p-type epitaxial layer and having the conductivity types of each region reversed. It goes without saying that it is possible.

【Effect of the invention】

士 Ja HHI+ je IHL /r
+ 〒 1-"h + ,・-,-++,n
ll ih +wan, +s. By using one region of the opposite conductivity type as the channel generation layer of the MO3I-transistor, the pn junction formation layer of the Zener diode, and the base layer of the bipolar transistor, an isolation diffusion layer is no longer required, and the drain electrode of the MO3I-transistor and the Zener Since one electrode of the diode can be shared, and the other electrode of the Zener diode and the base electrode of the bipolar transistor can be omitted, the structure of the MOS transistor and its protection circuit can be extremely simplified. As a result, the IC of the MOS transistor protection circuit
The area occupied on the chip is significantly reduced, and it is possible to provide an inexpensively integrated MOS transistor protection circuit that has the same function.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view and connection wiring diagram of a MOS transistor according to an embodiment of the present invention, its protection circuit, and FIG.
The circuit diagram of the OS transistor protection circuit, Figure 3 is the conventional M
FIG. 2 is a cross-sectional view and a connection wiring diagram of an O5I-transistor and its protection circuit. l: p-type silicon substrate, 2: n-type epitaxial layer, 4
2p type square area, 55, 56.57: n shadow area, 58:
n9! i region, 6 dioxide film, ll: MOS transistor, 12: Zener diode, 13: bibolar npn
transistor, 14: gate electrode, 15: source electrode,
1fll drain electrode, 20: collector electrode, 21:
Emisota electric wire, 22: gate terminal, 23: drain terminal, piezo terminal, 24: source terminal.

Claims (1)

[Claims] 1) A MOS transistor and its protection circuit consisting of a Zener diode and a bipolar transistor are integrated in one semiconductor substrate, and a region of another conductivity type formed in a semiconductor layer of one conductivity type; first, second, and third regions of one conductivity type formed within the region; and a gate provided on the surface of the region of the other conductivity type between the first and second regions with an insulating film interposed therebetween. metal electrodes, first, second, third and fourth metal electrodes in ohmic contact with the first, second and third regions and the remaining layer, respectively, the first electrode being in contact with the third electrode; , a semiconductor device characterized in that the second electrodes are respectively connected to the fourth electrodes.