JPH0258864A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of absorbing current, eliminate an adverse influence upon another active element, and improve latchup resisting property by completely surrounding an MOS transistor to be a power generation source of one conductivity type with a diffusion layer of one conductivity type and a buried layer of one conductivity type. CONSTITUTION:After an N-type buried layer 2 is formed on a P-type silicon substrate 1, an N-type epitaxial layer 3 is deposited. Next, a P-type well region 6 is formed; an N-type diffusion layer 7a is formed on the main surface of the region 6; an N-type MOS transistor 10 is formed by forming an electrode of polycrystalline silicon 9. An N-type diffusion layer 4 is formed so as to completely surround the whole side surface of the N-type epitaxial layer 3 and reach the depth of the N-type buried layer 2, and fixed at a power supply potential. Hence, the N-type MOS transistor 10 is completely surrounded by the N-type diffusion layer 4 and the N-type buried layer 2 being fixed at the power supply potential. Thereby, data held by an adjacent active element, e.g., memory cell, can be protected from destruction.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device including an input/output protection device. [Prior Art] Fig. 3 illustrates an example of a conventional semiconductor device. FIG. In this conventional example, an N-type MOS transistor will be explained as an example. Conventionally, a semiconductor input/output protection device is represented by an equivalent circuit as shown in FIG. As shown in FIG. 3, after a P-type buried layer 12 is formed on a P-type silicon substrate 1, a P-type well region 6 is formed thereon. Next, a diffusion layer 7a is formed on the P-type well region 6,
It was an N-type MOS transistor. In this case, the diffusion layer 7a is located in the P-type well region 6. It has a structure in which it is separated from other active elements, for example, the N-type diffusion layer 7b of the adjacent memory cell 11, by the P-type buried layer 12 and the P-type substrate 1.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, an N-type diffusion layer region 7a is formed on the P-type substrate 1, the P-type buried layer 12, and the P-type conductive layer of the P-type well region 6, which is equivalently connected to an external terminal. Therefore, when a voltage lower than the ground potential is applied to the external terminal, a parasitic transistor is generated with the N-type diffusion region 7a as the emitter, the P-type trench conductor layer as the base, and the N-type diffusion layer 7b as the collector. , the N-type diffusion region 7a is the N-type diffusion layer 7b.
For example, if the N-type diffusion layer 7b is the memory cell 11, not only will the data held in the memory cell 11 be destroyed, but the current will also flow through the P-type substrate l, so the substrate This has the disadvantage that it increases the potential of

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can eliminate the influence on other active elements by preventing the absorption current from occurring, and which can also improve latch-up resistance.

[Means to solve the problem]

The semiconductor device of the present invention includes: - a buried layer of opposite conductivity type selectively provided on a semiconductor substrate of conductivity type; and an epitaxial layer of one conductivity type or opposite conductivity type not provided on the buried layer of reverse conductivity type; a well region of opposite conductivity type provided on the main surface of the epitaxial layer of one conductivity type or opposite conductivity type; a diffusion region of one conductivity type provided on the main surface of the well region of reverse conductivity type; or a reverse conductivity type diffusion layer provided to a depth reaching the reverse conductivity type buried layer so as to surround all the side surfaces of the reverse conductivity type epitaxial layer.

〔Example〕

Next, five embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the semiconductor device of the present invention. As shown in the figure, P
After forming an N-type buried layer 2 on a type silicon substrate 1, an N-type epitaxial layer 3 is deposited. Next, a P-type well region 6 is formed, an N-type diffusion N 7 a is formed on the main surface thereof, and an electrode is formed of polycrystalline silicon to form an N-type MOS transistor 10. Further, an N-type diffusion layer 4 is formed to a depth that reaches the N-type buried layer 2 so as to surround all the side surfaces of the N-type epitaxial layer 3, and is fixed at the power supply potential. As a result, the N-type MOS transistor 1
0 is completely surrounded by the N type diffusion layer 4 and the N type buried layer 2 which are fixed at the power supply potential.

Although this embodiment has been explained using an N-type MOS transistor as an example, the present invention can have similar effects even with a P-type MOS transistor.9 [Effects of the Invention] As explained above, the present invention has By completely surrounding a MOS transistor of one conductivity type, which serves as a current generation source, with a diffusion layer of one conductivity type and a buried layer of one conductivity type, absorption of current from other active elements of the MOS transistor is prevented, and adjacent The data held in active elements such as memory cells can be prevented from being destroyed, and the potential of the semiconductor substrate will not increase due to the current absorbed from other active elements, so the durability can be improved. It also has the effect of strengthening the latch-up properties.

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the semiconductor device of the present invention, FIG. 2 is an equivalent circuit of an input/output protection device, and FIG. 3 is an example of a conventional semiconductor device. FIG.

■...P-type substrate, 2...N-type buried layer, 3...N-type epitaxial layer, 4...N-type diffusion layer, 5...N-type epitaxial layer, 6...P Type well region, 7a, 7
b... N type diffusion layer, 8... N type diffusion layer, 9... Polycrystalline silicon, 10... N type MOS transistor, 1
1...Memory cell, 12...P-type buried layer.

Claims (1)

[Claims] a buried layer of opposite conductivity type selectively provided on a semiconductor substrate of one conductivity type; an epitaxial layer of one conductivity type or opposite conductivity type provided on the buried layer of opposite conductivity type; a reverse conductivity type well region provided on the main surface of the reverse conductivity type epitaxial layer; a one conductivity type diffusion region provided on the main surface of the reverse conductivity type well region; and one conductivity type or opposite conductivity type epitaxial layer. A semiconductor device comprising: a reverse conductivity type diffusion layer provided to a depth reaching the reverse conductivity type buried layer so as to surround all side surfaces.