JPH09116097A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the resistance of the electric path of static electricity by permitting the distance between impurity diffusion layers, which give potential to a substrate and a well which face at the junction part, to be longer than the distance between the impurity diffusion layers, which give potential to a substrate and a well that face at other junction part. SOLUTION: A distance B between an impurity diffusion layer 11, which faces a substrate formed by adjacently arranging a first diode and a second diode at the junction part of a well 6 and gives potential to the substrate, and an impurity diffusion layer 8 for giving potential to the well 6 is permitted to be longer than the distance A between an impurity diffusion layer 11, which faces other substrate at the junction part of a well 15 and gives potential to the substrate, and an impurity diffusion layer 16 for giving potential to the well 15. Thus, the resistance of the current path of static electricity is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit for a semiconductor integrated device.

[0002]

2. Description of the Related Art Conventionally, as a technique relating to an electrostatic protection circuit of a semiconductor integrated device, a technique shown in a circuit diagram of FIG. 3 has been generally used. The conventional technique will be described with reference to FIG. FIG.
Is an example of an electrostatic protection circuit for an input terminal. Reference numeral 18 is an input pad, 19 is a positive power source, 20 is a negative power source, and 21 is a resistance element, one end of which is connected to the input pad 18 and the other end of which is connected to an internal circuit. Since the resistance element 21 is connected to the input pad 18 in series, the static electricity applied to the input pad 18 has its energy attenuated by the resistance element 21. 22 is a diode, the anode of which is the resistance element 21
Is connected to the other end and the cathode is connected to the positive power source 19. Reference numeral 23 denotes a diode, the anode of which is connected to the negative power source 20 and the cathode of which is connected to the other end of the resistance element 21. A diode 24 is reverse-biased between the positive power source 19 and the negative power source 20, and is parasitically formed at the junction between the substrate and the well in the semiconductor integrated device.

Here, a case where static electricity is applied to the input pad 18 will be described with respect to the absorption path of the static electricity.
When positive static electricity is applied to the input pad 18 with respect to the positive power source 19, it is absorbed by the path of the input pad 18, the resistance element 21, the diode 22, and the positive power source 19. When negative static electricity is applied to the input pad 18 with respect to the positive power source 19, it is absorbed by the path of the positive power source 19, the diode 24, the diode 23, the resistance element 21, and the input pad 18.

On the other hand, the input pad 1 is connected to the negative power source 20.
When a negative static electricity is applied to 8, it is absorbed by the path of the negative power source 20, the diode 23, the resistance element 21, and the input pad 18. When positive static electricity is applied to the input pad 18 with respect to the negative power source 20, the input pad 18, the resistance element 21, the diode 22, the diode 24, the negative power source 2
It is absorbed by the 0 route. As described above, the static electricity is absorbed to protect the elements in the semiconductor integrated device from being destroyed.

Although static electricity flows to the diode 24 in the direction opposite to the cathode direction from the anode direction,
The junction size between the cathode and the anode is secured to 1 to 2 mm or more, and static electricity is dispersed to flow to prevent destruction.

[0006]

However, the conventional technique has the following problems. In the diode 22 and the diode 23 in FIG. 3, for example, if one diode is formed of a substrate and an impurity diffusion layer of a different polarity from the substrate or an ion implantation layer, the other diode is a well and an impurity diffusion layer of a different polarity from the well. Layer or ion-implanted layer. Then, by disposing the diode 22 and the diode 23 close to each other, the junction between the substrate and the well is parasitically formed. This will be described with reference to the circuit diagram of FIG. In FIG. 4, the same components as those in FIG. 3 are given the same numbers for easy understanding. In FIG. 4, the diode 25 arranges the diode 22 and the diode 23 described above in close proximity to each other.
It is a junction diode of a substrate and a well formed parasitically. Reference numerals 26, 27, 28, and 29 represent resistances of power supply wirings formed mainly of metal such as aluminum. In FIG. 4, the resistance of the power supply wiring from the positive power supply 19 to the diode 25 is only the resistance 26. On the other hand, the resistance of the power supply wiring from the positive electrode power supply 19 to the diode 24 is resistance 26 + resistance 27. The resistance of the power supply wiring from the negative power supply 20 to the diode 25 is only the resistance 28. On the other hand, the resistance of the power supply wiring from the negative power supply 20 to the diode 24 is resistance 28 + resistance 29. With such a configuration, for example, a current flowing by the application of static electricity causes the diode 25 or the diode 24 from the positive power source 19 to
When the diode 23, the resistance element 21, and the input pad 18 try to flow, since the resistance of the power supply wiring is lower in the diode 25, static electricity flows in the diode 25 instead of flowing in the diode 24. 25
If the allowable current capacity in the opposite direction is exceeded, the junction of the diode 25 will be destroyed.

[0007]

Means for Solving the Problems (Means 1) A semiconductor integrated device according to the present invention is configured such that at least a pad connected to an external terminal, a resistance element having one end connected to the pad, and a cathode electrically connected to a positive power source. Electrostatic protection consisting of a first diode connected and having its anode connected to the other end of the resistance element, and a second diode having its cathode connected to the other end of the resistance element and its anode connected to the negative power supply In the circuit, an impurity diffusion layer for applying a potential to the substrate, which faces the substrate formed by disposing the first diode and the second diode in close proximity to each other at the junction of the well, and a potential to the well An impurity diffusion layer for giving a potential to a substrate opposed to another substrate at a well junction with another substrate, It is characterized in that it is made wider than the distance from the impurity diffusion layer for applying a potential to the well.

(Means 2) Further, at the junction between the substrate and the well formed by arranging the first diode and the second diode in close proximity to each other, impurity diffusion for applying a potential to the substrate in the opposing portion. The layer and the impurity diffusion layer for applying a potential to the well are not provided with a contact for applying a power supply potential.

(Means 3) Further, at least a pad connected to an external terminal, a resistance element having one end connected to the pad, a cathode electrically connected to a positive power source, and an anode connected to the other end of the resistance element. In an electrostatic protection circuit composed of a connected first diode and a second diode having a cathode connected to the other end of the resistance element and an anode connected to a negative power source, the first or second diode is A series resistance is formed between the anode and the cathode by the impurity diffusion layer forming the anode and the cathode of the first or second diode.

[0010]

According to the above configuration of the present invention, the current generated by the application of static electricity can be discharged to the expected discharge path, so that the static electricity resistance can be improved. Further, since the current generated by the application of static electricity can be limited, the electrostatic withstand capability can be similarly improved.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a layout plan view of an electrostatic protection circuit showing an embodiment of the present invention. In FIG. 1, 1 is a pad for electrical connection to an external terminal, 2 and 7 are wirings mainly made of metal such as aluminum, 3 is an impurity diffusion layer or an ion implantation layer, 4 is a wiring 2 and an impurity diffusion layer or A contact for electrically connecting the ion-implanted layer 3, 6 is a well, 8 is an impurity diffusion layer or an ion-implanted layer having the same polarity as that of the well 6 for applying a potential to the well 6, and 9 is a power source and impurity diffusion of one pole. Contact for electrically connecting the layer or the ion-implanted layer 8 is a contact for electrically connecting the well 6 and the impurity diffusion layer or the ion-implanted layer having a different polarity to the well 6, and the wiring 7 and the impurity diffusion layer or the ion-implanted layer 10 for the electric connection , 11 is an impurity diffusion layer or an ion implantation layer having the same polarity as the substrate, and 12 is an electrical contact between the power source of the other pole and the impurity diffusion layer or the ion implantation layer 11. A contact for making 13 an impurity diffusion layer or an ion implantation layer having a different polarity from the substrate, a 14 a contact for electrically connecting the wiring 7 and the impurity diffusion layer or the ion implantation layer 13, a 15 forming a circuit in the semiconductor integrated device Well 16 having the same polarity as that of the well 6, 16 is an impurity diffusion layer or an ion implantation layer having the same polarity as the well 15 for applying a potential to the well 15, and 17 is a power source of one pole and the impurity diffusion layer or ion implantation A contact that electrically connects layer 16. The power supply wiring formed mainly of metal such as aluminum is not shown in order to make the drawing easy to see.

Here, in the present invention, the impurity regions formed by the impurity diffusion layer or the ion implantation layer have the same structure and the same effect even in the case of the impurity diffusion layer or the ion implantation layer. In the description, the impurity diffusion layer will be described for simplification of description. Further, an N-type substrate will be described as an example. Since it is an N-type substrate, the N-type impurity diffusion layer 11 having the same polarity as the substrate
A positive power source is connected to the contact 12 for applying a potential to the. On the other hand, a negative electrode power source is connected to the contact 9 for applying a potential to the P-type impurity diffusion layer 8 having the same polarity as the well 6 and the contact 17 for supplying a potential to the P-type impurity diffusion layer 16 having the same polarity as the well 15. Reference numeral 3 is a resistance element formed of a P-type impurity diffusion layer, one end of which is connected to the pad 1 by the wiring 2. Since 13 is a P-type impurity diffusion layer and is arranged in the N-type substrate region, the first diode is formed by the junction of the P-type impurity diffusion layer 13 and the N-type substrate, and the cathode of the first diode is formed. The corresponding N-type substrate is electrically connected to the positive power source, and the P-type impurity diffusion layer 13 corresponding to the anode is connected to the other end of the resistance element 3 by the wiring 7. Since 10 is an N-type impurity diffusion layer and is arranged in the region of the P-type well 6, a second diode is formed by the junction between the N-type impurity diffusion layer 10 and the P-type well 6, and the cathode of the second diode is formed. Is connected to the other end of the resistance element 3 by the wiring 7, and the P-type well 6 corresponding to the anode is connected to the negative power source. Impurity diffusion layer 1 for applying a potential to a substrate formed by arranging the first diode and the second diode in close proximity to the substrate and a well 6 facing each other
The distance between 1 and the impurity diffusion layer 8 for applying a potential to the well is B. By joining the well 6 and the substrate, the diode 25 of FIG. 4 described in the conventional example is formed. On the other hand, at the junction between the other substrate and the well 15, the distance between the impurity diffusion layer 11 for applying a potential to the opposing substrate and the impurity diffusion layer 16 for applying a potential to the well 15 is A. The junction between the well 15 and the substrate forms the diode 24 of FIG. 4 described in the conventional example. According to the present invention, as shown in FIG.
The interval B is wider than that. In this way, the resistance value between the impurity diffusion layer 11 and the impurity diffusion layer 8 is increased.

Next, the means 2 will be described with reference to FIG. The substrate is also N-type. 2 is also a layout plan view of the same portion as FIG. 1, but elements not directly related to the description are omitted. In FIG. 2, 101, 102, and 103 are
A contact for connecting a positive electrode power source to the N-type impurity diffusion layer 11 which gives a potential to the substrate. 104, 10
Reference numerals 5 and 106 are contacts for connecting a negative power source to the P-type impurity diffusion layer 8 which gives a potential to the well 6. In the invention of the means 2, the N-type impurity diffusion layer 11 for applying a potential to the substrate is formed at the junction between the substrate and the well 6 which is formed by arranging the first diode and the second diode close to each other. The contacts 103 and 104 for applying the power supply potential are not provided in the portion facing the P-type impurity diffusion layer 8 for applying the potential to the well 6. Since the current due to the applied static electricity tends to flow between the N-type impurity diffusion layer 11 and the P-type impurity diffusion layer 8, the current concentrates on the contacts 103 and 104, which easily causes thermal destruction. By not providing it,
Prevents current concentration.

Next, the means 3 will be described with reference to FIG. In the contact 14 for electrically connecting the P-type impurity diffusion layer 13 and the wiring 7, the distance C between the contact 12 and one side of the contact 14 facing is the contact 10.
It is arranged at a distance D from the other three sides of the contact 14 facing the first, 102, and 103. The contacts 101, 102 and 103 are not provided. The current due to the applied static electricity flows from the contact 14 to the contact 12, but in the invention of the means 3, the distance from the contact 14 to the contact 12 is longer than that in the conventional example, so that the resistance value of the current path should be made higher. You can

Although the N-type substrate has been described above as an example, the same effect can be obtained even in the case of the P-type substrate by only changing the characteristics of the well contact, the sub-contact, the diode, and the positive and negative electrodes of the power supply. Is obtained.

[0016]

As described above, according to the present invention, a substrate formed by arranging the first diode and the second diode in close proximity to each other is formed on the substrate facing each other at the junction of the well. The distance between the impurity diffusion layer for applying a potential and the impurity diffusion layer for applying a potential to the well, the impurity diffusion layer for applying a potential to the substrate facing the other substrate at the junction of the well, Since the distance between the well and the impurity diffusion layer for applying a potential to the well can be made wider and the resistance value of the electrostatic current path can be increased, electrostatic energy is absorbed in the junction region between the substrate and the well having a large area, It is possible to prevent the destruction of the junction between the substrate and the well formed by disposing the first diode and the second diode in close proximity.

Further, according to the present invention, at the junction between the substrate and the well formed by arranging the first diode and the second diode in close proximity to each other, a potential is applied to the opposing substrate. Since the impurity diffusion layer and the impurity diffusion layer for applying a potential to the well are not provided with contacts for applying a power supply potential,
And a substrate formed by disposing the second diode and the second diode in close proximity to each other, and electrostatic current concentration at the junction of the well can be prevented.
It is possible to prevent thermal destruction of the well junction.

Further, according to the present invention, the impedance between the anode and the cathode of the first and second diodes becomes high, so that the current generated by the application of static electricity can be limited, and the heat of the first and second diodes can be limited. Can prevent destruction.

[Brief description of the drawings]

FIG. 1 is a layout plan view of an electrostatic protection circuit that is an embodiment of the present invention.

FIG. 2 is a layout plan view of an electrostatic protection circuit according to another embodiment of the present invention.

FIG. 3 is a conventional electrostatic protection circuit diagram.

FIG. 4 is a conventional electrostatic protection circuit diagram.

[Explanation of symbols]

 1 Aluminum Pad 2 Wiring 3 Resistance Element 4 Contact 5 Contact 6 Well 7 Wiring 8 Contact 9 Contact 10 Impurity Diffusion Layer 11 Impurity Diffusion Layer 12 Contact 13 Impurity Diffusion Layer 14 Contact 15 Well 16 Impurity Diffusion Layer 17 Contact 18 Input Pad 19 Positive Power Supply 20 Negative Power Supply 21 Resistance Element 22 Diode 23 Diode 24 Diode 25 Diode 26 Wiring Resistance 27 Wiring Resistance 28 Wiring Resistance 29 Wiring Resistance 101 Contact 102 Contact 103 Contact 104 Contact 105 Contact 106 Contact

Claims (3)

[Claims] 1. A pad having at least one pad connected to an external terminal, a resistance element having one end connected to the pad, a cathode electrically connected to a positive power source, and an anode connected to the other end of the resistance element. And a second diode whose cathode is connected to the other end of the resistance element and whose anode is connected to the negative power source, the first diode and the second diode are placed close to each other. An impurity diffusion layer or an ion implantation layer for giving a potential to the substrate and an impurity diffusion layer or an ion implantation layer for giving a potential to the substrate, which face each other at the junction of the well and the substrate formed by disposing Of the impurity diffusion layer or ion implantation for applying a potential to the substrate facing the other substrate at the well junction. The semiconductor integrated device comprising a layer that was wider than the distance between the impurity diffusion layer or ion implantation layer for applying a potential to the wells. 2. The semiconductor integrated device according to claim 1, wherein
At the junction between the substrate and the well formed by arranging the first diode and the second diode in close proximity to each other, an impurity diffusion layer or an ion-implanted layer for applying a potential to the substrate at the opposing portion, and the well A semiconductor integrated device characterized in that an impurity diffusion layer or an ion implantation layer for applying a potential is not provided with a contact for applying a power source potential. 3. A first pad having at least a pad connected to an external terminal, a resistance element having one end connected to the pad, a cathode electrically connected to a positive power source, and an anode connected to the other end of the resistance element. And a second diode having a cathode connected to the other end of the resistance element and an anode connected to a negative power source, the first or second diode is the first diode. Alternatively, the semiconductor integrated device is characterized in that a series resistance is formed between the anode and the cathode by an impurity diffusion layer or an ion implantation layer forming the anode and the cathode of the second diode.