JPS63239972A - Input protective circuit of semiconductor device - Google Patents
Input protective circuit of semiconductor deviceInfo
- Publication number
- JPS63239972A JPS63239972A JP62071886A JP7188687A JPS63239972A JP S63239972 A JPS63239972 A JP S63239972A JP 62071886 A JP62071886 A JP 62071886A JP 7188687 A JP7188687 A JP 7188687A JP S63239972 A JPS63239972 A JP S63239972A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- resistor
- contacted
- protection circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000001681 protective effect Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 41
- 229920005591 polysilicon Polymers 0.000 abstract description 41
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 abstract description 23
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000020169 heat generation Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、ＭＯ８ＩＣあるいはＢｉ −０ＭＯ３ＩＣ
等の半導体装置の入力保護回路に関する。[Detailed description of the invention] [Object of the invention] (Industrial application field) This invention is directed to MO8IC or Bi-0MO3IC.
The present invention relates to an input protection circuit for semiconductor devices such as the above.
（従来の技術）
最近の半導体装置にあっては、特に入力段にＭＯＳＦＥ
Ｔを用いている半導体装置にあっては、入力段のＭＯＳ
ＦＥＴを静電破壊から保護するために、例えば第５図に
示すような、抵抗Ｒ＋ 。(Prior art) In recent semiconductor devices, MOSFE is used especially in the input stage.
In a semiconductor device using T, the input stage MOS
To protect the FET from electrostatic damage, a resistor R+, for example as shown in FIG.
Ｒ２，ダイオードＤ１及びダイオードとして機能するＭ
Ｏ８ＦＥＴＭ＋ とからなる入力保護回路が、入力端子
ＩＮと入力段のＭＯＳＦＥＴとの間に設置１られている
。R2, diode D1 and M functioning as a diode
An input protection circuit consisting of O8FETM+ is installed between the input terminal IN and the input stage MOSFET.
第６図は第５図の入力保護回路におけるパクーンの一例
を示す図である。同図において、抵抗Ｒ１はポリシリコ
ン１で形成されており、このポリシリコン１の一方端は
入力端子ＩＮからのアルミ配＃ａ３に接続され、他方端
はダイオードＤ＋及び抵抗Ｒ２を形成する半導体基板と
異なる導電型の拡ｆＢ［層５にアルミ配線７を介して接
続されている。FIG. 6 is a diagram showing an example of a cover in the input protection circuit of FIG. 5. In the figure, the resistor R1 is made of polysilicon 1, one end of which is connected to the aluminum wiring #a3 from the input terminal IN, and the other end connected to the semiconductor substrate forming the diode D+ and resistor R2. The expanded fB layer 5 is connected to the layer 5 via an aluminum wiring 7 and is of a different conductivity type.
拡散層５はアルミ配線９を介して入力段のＭＯＳＦＥＴ
に接続されており、また、この拡散層５とグランドに接
続されたゲート電ｊｆＡ１１によりＭＯＳ Ｆ Ｅ Ｔ
Ｍ＋が形成されている。The diffusion layer 5 is connected to the input stage MOSFET via the aluminum wiring 9.
The gate voltage jfA11 connected to the diffusion layer 5 and the ground causes the MOS FET
M+ is formed.
第７図は第６図におけるｖｒ −ｖ■断面図である。FIG. 7 is a sectional view taken along the line vr-v■ in FIG. 6.
同図において、第５図及び第６図に示した入力保護回路
は、例えばＰ型の半導体基板１３上に形成されている。In the figure, the input protection circuit shown in FIGS. 5 and 6 is formed on a P-type semiconductor substrate 13, for example.
半導体基板１３上には、素子分離用のシリコン酸化膜１
５が形成され、このシリコン酸化膜１５上に抵抗Ｒ＋
となるポリシリコン１が形成されている。このポリシリ
コン１の一方端の表面には、入力端子ＩＮからのアルミ
配線３がコンタク１〜され、伯方端の表面には半導体基
板１３中に形成されたＮ型の拡散層５とポリシリコン１
を接続するアルミ配線７がコンタク１〜されている。A silicon oxide film 1 for element isolation is formed on the semiconductor substrate 13.
A resistor R+ is formed on this silicon oxide film 15.
Polysilicon 1 is formed. The aluminum wiring 3 from the input terminal IN is connected to the surface of one end of the polysilicon 1, and the N-type diffusion layer 5 formed in the semiconductor substrate 13 and the polysilicon 1 are formed on the surface of the opposite end.
Aluminum wiring 7 connecting the contacts 1 to 1 is connected.
なお、これらは保護膜１７によって被覆されている。Note that these are covered with a protective film 17.
（発明が解決しようとする問題点）
以上説明したように、第５図に示した入力保護回路を、
第７図に示したｒ４迄で形成すると、アルミニウムの抵
抗率はポリシリコンのそれに比べて２〜３桁低いために
、静Ｔｉ敢ｍ（ＥＳＤ、Ｅｌｅｃｔｒｏｓｔａｔｉｃ
Ｄ ！５Ｃ１１ａｒ（ｔｏ）による大量の電子（よ、
抵抗率が著しく変化することにより最も電界が高くなる
アルミ配線３，７とポリシリコン１とのコンタクト部傍
、すなわち、第７図のＡ及びＢで示づポリシリコン１の
上層部を集中的に流れることになる。(Problems to be Solved by the Invention) As explained above, the input protection circuit shown in FIG.
When formed up to r4 shown in FIG. 7, the resistivity of aluminum is two to three orders of magnitude lower than that of polysilicon, so the resistivity of aluminum (ESD) is lower than that of polysilicon.
D! A large amount of electrons (yo,
Concentrate on the area near the contact area between the aluminum wirings 3 and 7 and the polysilicon 1, where the electric field is highest due to a significant change in resistivity, that is, the upper layer of the polysilicon 1 shown by A and B in FIG. It will flow.
このため、例えばＩｖｌ Ｉ Ｌ−３ＴＤ８８３Ｂ （
信Ｊ（ｉ ｔ］ｌ試験の試験事項を規定しているアメリ
カ軍用規格）等に記載されているＥＳＤ試験を行なうと
、アルミ配線３．７とポリシリコン１とのコンタクト部
ニのみか、過大な発熱７７１τじてポリシリコン１が溶
ＦＪｉするという問題があった。したがって、静電放電
により過大な電流が入力保護回路を流れると、入力端子
ＩＮと入力段の素子との１ａ続が断れ、入力保護回路及
び半導体装首ｔｉｔ正常に（浸能しなくなる。For this reason, for example, Ivl I L-3TD883B (
When conducting the ESD test described in the U.S. military standard that stipulates the test items for the IT test, only the contact area between the aluminum wiring 3.7 and the polysilicon 1 was detected. There was a problem in that the polysilicon 1 melted due to the heat generated 771τ. Therefore, when an excessive current flows through the input protection circuit due to electrostatic discharge, the connection between the input terminal IN and the input stage element is broken, and the input protection circuit and the semiconductor device are not normally operated.
そこで、この発明は、上記に鑑みてなされた乙のであり
、その目的とするところは、電流の局所的な集中による
過大な発熱を緩和して、抵抗体どなるポリシリコンの断
線不良を防止することがでさ゛る半導体装置の入力保護
回路を提供することにある。Therefore, this invention has been made in view of the above, and its purpose is to alleviate excessive heat generation due to local concentration of current and prevent disconnection of polysilicon caused by resistor. It is an object of the present invention to provide an input protection circuit for a semiconductor device that is capable of providing high power.
［発明の構成］
（問題点を解決するための手段）
上記目的を達成するために、この発明は、電気的に接合
される部材との接合領域の抵抗値を接合領域以外の領域
の抵抗値よりも低くなるように形成した抵抗から構成さ
れる。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for reducing the resistance value of a bonding region with a member to be electrically bonded to the resistance value of a region other than the bonding region. It consists of a resistor formed to be lower than the
（作用）
この発明の半導体装置の入力保護回路にあっては、入力
保護回路を構成する抵抗を、この抵抗と電気的に接合さ
れる部材との接合領域に１１５ける抵抗値が接合領域以
外の領域の抵抗１直よりも低く形成するようにした。(Function) In the input protection circuit for a semiconductor device of the present invention, the resistance value of the resistor constituting the input protection circuit in the bonding area of the resistor and the member electrically connected is 115 in the area other than the bonding area. The resistance of the area is made lower than the resistance of one line.
（実施例） 以下図面を用いてこの発明の詳細な説明する。(Example) The present invention will be described in detail below using the drawings.
第１図乃至第３図はこの発明の第１の実／、Ｉ例乃Ｔ第
３の実施例に係る半導体装置の入力保護回路の構造をポ
リ−断面図である。それぞれの実施例の入力保護回路は
、第５図に示した回路構成のものである。なお、第１図
乃至第３図において、第５図乃至第７図と同筒ｇの６の
は同一機能を有するものであり、その説明は省略ザる。1 to 3 are polygon cross-sectional views showing the structure of an input protection circuit for a semiconductor device according to a first embodiment to a third embodiment of the present invention. The input protection circuit of each embodiment has the circuit configuration shown in FIG. Incidentally, in FIGS. 1 to 3, reference numeral 6 of the cylinder g has the same function as in FIGS. 5 to 7, and the explanation thereof will be omitted.
第１図に示ず入力保護回路は第７図と同様の構造を右す
るものであり、この人り保護回路の特徴とするところは
、ポリシリ」ン１にアルミ配線３゜７をコンタクトする
而に、アルミ配線３．７がコンタクトされるポリシリコ
ンの両端部に不純物を高！！度に導入して、ポリシリコ
ン１の両端部をＩＩ（抵抗領域２１．２３としたことに
ある。この（１（抵抗ダ１域２１．２３は、従来から一
般的に用いら＋’ｔてる半導体１１４造工程の拡散ある
い（、ｔイＡン注入技術により容易に形成することが可
能である。The input protection circuit, not shown in Fig. 1, has the same structure as Fig. 7, and the feature of this human protection circuit is that the aluminum wiring 3°7 is in contact with the polysilicon line 1. In addition, impurities are added to both ends of the polysilicon where the aluminum wiring 3.7 is contacted! ! This is because both ends of polysilicon 1 are made into II (resistance regions 21.23). It can be easily formed by diffusion or ion implantation technology in the semiconductor 114 manufacturing process.
このように、抵抗体と４ｒるポリシリコン１とアルミ配
ＦＡ３．７とのコンタクト部にお（Ｊるポリシリコン１
が低抵抗となるようにしているので、静電放電の際の放
電電流は、ポリシリコン１の断１イ。In this way, at the contact part between the resistor, the polysilicon 1 of 4r, and the aluminum wiring FA3.7 (the polysilicon 1 of
Since the resistance of the polysilicon 1 is made low, the discharge current during electrostatic discharge is caused by the disconnection of the polysilicon 1.
にＪ３けるバルク中を流れるようになる。このため、局
所的な電流集中による発熱を緩和して、ポリシリコン１
の溶断を防止することができ６つ第２図はこの発明の第
２の実施例を示ず図で、ｂす、この第２の実施例の入力
保４回路の特徴とするところは、高濃度に不純物が導入
されて低）代抗となったポリシリコン２５．２７を介在
させ、アルミ配線３，７とポリシリコン１とを接続して
、このポリシリコン２５．２７からの不純物の拡散によ
りポリシリコ１ン１の両端部に低抵抗領域２１゜２３を
形成したことにある。It begins to flow through the bulk of J3. Therefore, heat generation due to local current concentration is alleviated, and polysilicon 1
Figure 2 does not show the second embodiment of the present invention, and the feature of the input protection circuit of this second embodiment is that By interposing the polysilicon 25.27 which has low resistance due to the introduction of impurities into the concentration, the aluminum wirings 3 and 7 and the polysilicon 1 are connected, and by the diffusion of impurities from this polysilicon 25.27. This is because low resistance regions 21 and 23 are formed at both ends of the polysilicon layer 1.
・なお、ポリシリコン２５．２７は、ポリシリコン１の
両端を包み込むように形成することが望ましい。- Note that it is desirable that the polysilicon 25 and 27 be formed so as to wrap both ends of the polysilicon 1.
このような構造どすることにより、アルミ配線３．７か
らポリシリコン１への抵抗変１ヒは小さくなり、第１の
実施例で述べた効果をざらに高めることができる。なお
、アルミ配線３，７とポリシリコン１との間に介在させ
るものは、高濃度に不純物が導入されたポリシリコンに
限定されるものではなく、例えば、ポリシリコンに比べ
て抵抗が約１桁小さい高融点金属系シリサイドであって
も同様の効果を得ることができる。By adopting such a structure, the change in resistance from the aluminum wiring 3.7 to the polysilicon 1 becomes small, and the effects described in the first embodiment can be greatly enhanced. Note that the material interposed between the aluminum wirings 3 and 7 and the polysilicon 1 is not limited to polysilicon into which impurities are introduced at a high concentration; Similar effects can be obtained even with small high melting point metal silicides.
第３図はこの発明の第３の実施例を示す図であり、この
実施例の特徴とするところろは、第２図に示した構造に
おいて、ポリシリコン１の一方端を直接Ｎ型の拡散１５
にベリードコンタクトして、拡散層５からの不純物拡散
によりポリシリコン１と拡散層５とのコンタクト部に低
抵抗領域２３を形成したことにある。FIG. 3 is a diagram showing a third embodiment of the present invention, and the feature of this embodiment is that in the structure shown in FIG. 15
The low resistance region 23 is formed at the contact portion between the polysilicon 1 and the diffusion layer 5 by making a buried contact with the polysilicon 1 and the diffusion layer 5 by diffusing impurities from the diffusion layer 5.
したがって、このような構造においては、第１の実施例
と同様の効果を得ることができる。さらに、過大電流が
ポリシリコン２５と接続されポリシリコン１の上部から
流れ込んだ場合に、ポリシリコン１から流れ出る電流は
、低抵抗領域２３の下方を通り拡散層５に流れ込むため
、過大電流はポリシリコン１のバルク中を流れることに
なる。Therefore, in such a structure, effects similar to those of the first embodiment can be obtained. Furthermore, when an excessive current flows from the upper part of the polysilicon 1 connected to the polysilicon 25, the current flowing out from the polysilicon 1 passes below the low resistance region 23 and flows into the diffusion layer 5. It will flow through the bulk of 1.
したがって、第１の実施例で述べた効果をより高めるこ
とができる。Therefore, the effects described in the first embodiment can be further enhanced.
また、このような構造にあっては、第４図に示すように
、アルミ配線３をポリシリコン１の上部に延長形成する
ことが可能となり、放熱に好ましい＋１１２とすること
ができる。Further, in such a structure, as shown in FIG. 4, it is possible to extend the aluminum wiring 3 above the polysilicon 1, and it is possible to set the aluminum wiring 3 to +112, which is preferable for heat dissipation.
なお、以上説明した第１の実施例乃至第３の実施例は、
半導体幕板を用いたものであるが、絶縁体基板を用いた
もの（ＳＯ８構造）であっても、実施することができる
。Note that the first to third embodiments described above are as follows:
Although a semiconductor screen plate is used, it is also possible to use an insulator substrate (SO8 structure).
［発明の効果］
以上説明したように、この発明によれば、入力保護回路
を構成する抵抗を、この抵抗と電気的に接合される部材
との接合領域における抵抗値が接合領域以外の領域の抵
抗値よりも低くなるように形成したので、抵抗を流れる
過大電流の局所的集中による発熱を緩和して、抵抗の断
線不良を防止した半導体装置の入力保護回路を提供する
ことができる。[Effects of the Invention] As explained above, according to the present invention, the resistance value of the resistor constituting the input protection circuit in the joint region of the resistor and the member electrically connected is equal to that of the region other than the joint region. Since the resistor is formed to have a value lower than the resistance value, it is possible to provide an input protection circuit for a semiconductor device in which heat generation due to local concentration of excessive current flowing through the resistor is alleviated, and disconnection failure of the resistor is prevented.
第１図はこの発明の第１の実施例に係る半導体装置の入
力保護回路の４１′４造を示す断面図、第２図はこの発
明の第２の実施例に係る半導体装置の入力保護回路の構
造をポリ断面図、第３図はこの発明の第３の実施例に係
る半導体装置の入力保護回路の構造を示す断面図、第４
図は第３図におけるアルミ配線を延長形成した構造をポ
リ断面図、第５図は半導体装置の入力保護回路の一構成
例を示す回路図、第６図は第５図のパターンの一例を示
す図、第７図は第５図の構造を示す断面図である。
（図の主要な部分を表わす符号の説明）１・・・ポリシ
リコン
３．７・・・アルミ配線
５・・・拡ｒｌ１層
２１．２３・・・低抵抗領域FIG. 1 is a sectional view showing a 41'4 structure of an input protection circuit for a semiconductor device according to a first embodiment of the invention, and FIG. 2 is an input protection circuit for a semiconductor device according to a second embodiment of the invention. FIG. 3 is a cross-sectional view showing the structure of an input protection circuit of a semiconductor device according to a third embodiment of the present invention, and FIG.
The figure is a poly cross-sectional view of a structure in which the aluminum wiring in Figure 3 is extended, Figure 5 is a circuit diagram showing an example of the configuration of an input protection circuit for a semiconductor device, and Figure 6 is an example of the pattern in Figure 5. 7 are cross-sectional views showing the structure of FIG. 5. (Explanation of the symbols representing the main parts of the diagram) 1...Polysilicon 3.7...Aluminum wiring 5...Extended RL1 layer 21.23...Low resistance region
Claims (2)
接合領域以外の領域の抵抗値よりも低くなるように形成
した抵抗を有することを特徴とする半導体装置の入力保
護回路。(1) An input protection circuit for a semiconductor device, characterized by having a resistor formed such that the resistance value of a bonding region with a member to be electrically bonded is lower than the resistance value of a region other than the bonding region.
の抵抗値よりも低い抵抗値を有する部材が接合されてい
ることを特徴とする特許請求の範囲第１項に記載の半導
体装置の入力保護回路。(2) The input of the semiconductor device according to claim 1, wherein the resistor has a member having a resistance value lower than the resistance value of the resistor joined to at least one end thereof. protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62071886A JPS63239972A (en) | 1987-03-27 | 1987-03-27 | Input protective circuit of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62071886A JPS63239972A (en) | 1987-03-27 | 1987-03-27 | Input protective circuit of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63239972A true JPS63239972A (en) | 1988-10-05 |
Family
ID=13473461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62071886A Pending JPS63239972A (en) | 1987-03-27 | 1987-03-27 | Input protective circuit of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63239972A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393265A (en) * | 1989-09-06 | 1991-04-18 | Nissan Motor Co Ltd | Semiconductor integrated circuit |
| US5465005A (en) * | 1991-10-30 | 1995-11-07 | Texas Instruments Incorporated | Polysilicon resistor structure including polysilicon contacts |
| JP2008078674A (en) * | 2007-10-16 | 2008-04-03 | Toshiba Corp | Semiconductor memory device |
-
1987
- 1987-03-27 JP JP62071886A patent/JPS63239972A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393265A (en) * | 1989-09-06 | 1991-04-18 | Nissan Motor Co Ltd | Semiconductor integrated circuit |
| US5465005A (en) * | 1991-10-30 | 1995-11-07 | Texas Instruments Incorporated | Polysilicon resistor structure including polysilicon contacts |
| US6261915B1 (en) | 1991-10-30 | 2001-07-17 | Texas Instruments Incorporated | Process of making polysilicon resistor |
| JP2008078674A (en) * | 2007-10-16 | 2008-04-03 | Toshiba Corp | Semiconductor memory device |
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