JP2680846B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device.

[Conventional technology]

 The conventional technique will be described using an nMOS transistor.

In the conventional semiconductor memory device, as shown in the sectional view of FIG. 2, the N of the MOS transistor 1 for the peripheral circuit other than the memory cell is excluded.
The type source / drain region 10 is separated from the N-type source / drain region 10 'of the MOS transistor for the memory cell through the P-well 3, the P-type buried layer 7 and the P-type semiconductor substrate 9.

[Problems to be solved by the invention]

In the conventional semiconductor memory device described above, the P-type buried layer and the P-type semiconductor substrate are provided under the P-well in which the nMOS transistor is provided.
Is operated, impact ions are generated from the N-type diffusion layer (10), the N-type diffusion layer (10) is used as an emitter, and the P-type conductive layers 3, 7 and 9 are used as bases and the N-type diffusion layer (10 ') is The parasitic bipolar transistor structure used as the collector absorbs a current from the N-type diffusion layer (10) and destroys the data held in the memory cell. Further, since a current flows through the P-type semiconductor substrate, there is a drawback that the latch-up resistance is deteriorated by raising the substrate potential in the vicinity of the transistor through which a large current flows.

An object of the present invention is to provide a semiconductor memory device in which data held in a memory cell is not destroyed due to a peripheral circuit and the latch-up resistance is improved.

[Means for solving the problem]

A semiconductor memory device according to the present invention is a semiconductor substrate of the second conductivity type, which is selectively provided in the epitaxial layer of a semiconductor substrate formed by forming an epitaxial layer on a semiconductor substrate of the second conductivity type.
And a MOS transistor for a memory cell provided in a first element formation region including a second conductivity type buried layer connected to both the first well and the second conductivity type semiconductor substrate; A MOS transistor for a peripheral circuit provided in a second element formation region that is formed of a second well of the second conductivity type that is selectively provided separately from the first well in the layer, The second well and the surrounding epitaxial layer are surrounded by the first conductivity type latch-up prevention layer connected to the predetermined potential supply end.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.

In this embodiment, a P-type first well 103 ′ and a first P-type well 103 ′ which are selectively provided in an N-type epitaxial layer 105 of a semiconductor substrate formed by forming an N-type epitaxial layer 105 on a P-type semiconductor substrate 109 made of silicon. First well 103 ′ and the N-type epitaxial layer 105 and the MOS transistor 101 ′ for the memory cell provided in the first element formation region formed of the P-type buried layer 107 connected to both the well 103 ′ and the P-type semiconductor substrate 109. The well 103 and the MOS transistor 101 for the peripheral circuit provided in the second element formation region including the P-type second well 103 selectively provided apart from the well 103, and the second well 103 and its The surrounding N-type epitaxial layer 105 is surrounded by the N-type latch-up prevention layer 104 connected to the power supply potential supply end. The bottom of the latch-up prevention layer 104 is a P-type buried layer and the side surface thereof is a P-type extraction region 12, which is connected to an electrode wiring formed of a polycrystalline silicon layer 116a, a W layer 116b, and an Al layer 116c. The peripheral circuit looks like this
Since it is composed of the nMOS transistor provided in the second element formation region surrounded by the latch-up prevention layer fixed to the power supply potential, even if impact ions are generated, the memory cell is not affected adversely. Latch-up characteristics are also improved.

〔The invention's effect〕

As described above, according to the present invention, the MOS transistor for the memory cell is completely surrounded by the N-type latch-up prevention layer connected to the fixed potential supply terminal.
Since the parasitic mutual interference with the transistor is blocked, the data held in the memory cell is not destroyed. Further, since the floating of the potential due to the substrate current does not occur, there is an effect that the anti-latch-up characteristic becomes stronger.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip showing a conventional example. 1,101 ... nMOS transistors for peripheral circuits, 1 ', 101'
... nMOS transistor for memory cell, 12 ... P-type extraction region, 3 ... P well, 103 ... second well, 103 '...
… First well, 5,105 …… N-type epitaxial layer, 6,1
06 …… P type diffusion layer, 7 …… P type buried layer, 8 …… Electrode wiring, 9,109 …… P type buried layer, 10,10 ′, 110,110 ′ ...
... N-type source / drain regions, 11a, 11a ', 111a, 111a'
...... Polycrystalline silicon gate electrode, 11b, 11b ′, 111b, 111
b ′ …… W gate electrode, 12,112 …… Channel stopper, 1
3,113 …… Field oxide film, 14,114 …… SiO ₂ film, 15,11
5 …… BPSG film, 116a …… Polycrystalline silicon layer, 116b …… W
Layer, 116c ... Al layer.

Claims (1)

(57) [Claims] 1. A first well of the second conductivity type, the first well, and the second well of the second conductivity type which are selectively provided in the epitaxial layer of a semiconductor substrate formed by forming an epitaxial layer on a semiconductor substrate of the second conductivity type. A MOS transistor for a memory cell provided in a first element formation region formed of a second-conductivity-type buried layer connected to both second-conductivity-type semiconductor substrates, and an epitaxial layer separated from the first well. A MOS transistor for a peripheral circuit provided in a second element formation region including a second well of the second conductivity type selectively provided, the second well and the epitaxial layer around the second well Is surrounded by a first conductivity type latch-up prevention layer connected to a predetermined potential supply terminal.