JPH0622276B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that includes a guard ring to prevent a latch-up phenomenon.

<Prior Art> In recent years, when a large number of logic elements are integrated on a single semiconductor substrate due to the progress of semiconductor manufacturing technology, it becomes necessary to reduce the power consumption of each logic element. Type MOS transistor (hereinafter abbreviated as C-MOS)
Logic circuits have come to be constructed by.

First, it is formed on a semiconductor substrate. The structure of the conventional C-MOS transistor will be described below with reference to FIG.

Reference numeral 1 is an N-type substrate to which a reference voltage is applied.
A P-type well 2 is formed in an island shape at a constant depth on the surface of the. A guard ring 3 is formed with a high concentration of P-type impurities at the boundary with the well 2 on the surface of the substrate 1, and the well 2 is doped with N-type impurities to form a source region 4.
And a drain region 5 is formed. The well surface portion between the source region 4 and the drain region 5 serves as a channel region, and constitutes an N-channel MOS transistor 7 together with the gate electrode 6 facing the channel region via an insulating layer.

On the other hand, on the surface of the substrate in the vicinity of the well 2, a drain region 8 and a source region 9 are formed by being doped with P-type impurities, and the channel region between the drain region 8 and the source region 9 is opposed via an insulating layer. Gate electrode 1
0 constitutes a P channel MOS transistor 11. These N channel MOS transistor 7 and P
The channel MOS transistor 11 constitutes a C-MOS transistor, and each region is appropriately connected to form a logic circuit such as an inverter.

By the way, in the C-MOS transistor, since the P-type well 2 is formed in the N-type substrate 1, the PNP is formed between the source region 9 of the P-channel MOS transistor 11 and the substrate 1 and the P-type well 2. The junction is formed and the parasitic transistor 12 is formed. The substrate 1 and the P-type well 2 form an NPN junction with the source region 4 of the N-channel MOS transistor 7 to form a parasitic transistor 13. On the other hand, the drain region 5 of the N-channel MOS transistor 7 is PN together with the P-type well 2 and the substrate 1.
Since the P-junction is formed to form the parasitic transistor 14, when an undesired current flows in the parasitic transistor 14,
A latch-up phenomenon may occur in the thyristor formed by the parasitic transistors 12 and 13, and a large current may flow. Therefore, in the conventional C-MOS transistor, the guard ring 3 is formed to prevent the occurrence of the latch-up phenomenon. That is, in the guard ring 3 doped with a high concentration of P-type impurities, chattering occurs in the signal circuit or the like connected to the gate electrode 6, the drain region 5 becomes a negative potential for a moment, and the parasitic transistor 14 Since the source region 4 is grounded even when is turned on, the guard ring 3 connected to the source region 4 functions to keep the P-type well 2 at the ground potential, and the P-type well 2 and the source region at the ground potential. It is possible to prevent a potential difference of 4 or more from the base-emitter barrier voltage of the parasitic transistor 13 from occurring. Furthermore, since the guard ring 3 increases the distance between the source region 9 and the P-type well 2, the base resistance value of the parasitic transistor 12 is equivalently increased, and the potential rise of the P-type well 2 is increased. Along with the suppression, it contributed to the prevention of the latch-up phenomenon.

In the conventional C-MOS transistor, the guard ring 3 is used to prevent the latch-up phenomenon as described above.
In addition, a buried layer doped with a high concentration of P-type impurities is provided below the bottom surface of the P-type well 2 to stabilize the potential of the P-type well 2 and increase the base resistance of the parasitic transistor 14. Was also often done.

<Problems of the Prior Art> However, the guard ring 3 of the conventional C-MOS transistor is not sufficient to stabilize the potential of the entire vast P-type well 2, and the source region 9 is sufficiently removed from the well 2. In order to separate the C-MOS transistors from each other, the width of the guard ring 3 must be increased, so that the area occupied by each C-MOS transistor in the substrate 1 becomes large, and there is a problem that the degree of integration is reduced. Further, in the structure in which the buried layer is provided below the bottom surface of the well 2, although it contributes to the stabilization of the potential of the well 2, a considerable number of P-type impurities need to be doped in the substrate 1 at a high concentration. However, there is a problem in that the manufacturing process of the semiconductor device becomes complicated.

<Means for Solving Problems> The present invention has been made in view of the problems of reduction in degree of integration and complication of manufacturing process, which is based on the above-mentioned conventional technique. Forming a guard ring, which is highly doped with impurities of the second conductivity type, at the boundary between the substrate of the first conductivity type in which is formed and the well of the second conductivity type in which the first conductivity type MOS transistor is formed,
A gate that penetrates through the guard ring in the depth direction and an insulating layer that insulates the gate from the substrate and the well are provided, and the gate and the guard ring are connected to a predetermined bias power supply to prevent the latch-up phenomenon. The gist is the configuration of the semiconductor device.

<Operation> In the semiconductor device having the above structure, the gate penetrating the guard ring in the depth direction constitutes a MOS transistor having the well as the source and the guard ring as the drain, so that a voltage change occurs in the deep portion of the well. , If the voltage difference between the gate and the depth of the well exceeds a threshold value, the well,
A channel is formed between the guard rings. Therefore, the potential of the bias power supply is maintained at the same potential as that of the bias power supply through the guard ring, and the potential of the bias power supply is set to a value at which the contributing transistor constituted by the substrate, the well, and the source region in the well is not turned on. The selection can prevent the occurrence of the latch-up phenomenon.

<Embodiment> Next, a first embodiment of the present invention will be described with reference to FIGS. 1 and 3 to 4. In the figure, the same components as those of the C-MOS transistor in FIG. 1 described in the related art are given the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1 and FIG. 4 which is an enlarged view of a part thereof,
Reference numeral 21 is a guard ring formed on the surface of the N-type substrate 1 by heavily doping P-type impurities.
An annular recess 22 is defined in the central portion of 1. After all, the recess 22 is formed in the first region, which is the well 2, and the substrate 1.
It is formed at the boundary part between them. In other words, the second region, which is the guard ring 21, is formed adjacent to the surface of the recess 22 adjacent to the surface of the substrate 1 and surrounding the recess.
In this case, the depth of the recess 22 is formed deeper than that of the guard ring 21 and shallower than the first region of the well 2. As shown in detail in FIG. 3, a plurality of polysilicon gates 23 are embedded in the recess 22 at intervals, and all the polysilicon gates 23 are connected to the guard ring 21 and are mutually connected. It is connected to a connection line 24 of polysilicon. Each polysilicon gate 23 as an electrode is embedded and surrounded by an insulating layer which is a silicon dioxide layer 25 formed so as to cover the inner wall of the recess 22 so as to be insulated from the substrate 1 and the well 2. The polysilicon gate 23 is grounded (V SS). Therefore, it is sufficient that the polysilicon gate 23 together with the well 2 and the guard ring 21 forms the source region of the P-channel MOS transistor 26.
Narrower than the conventional guard ring 3 is sufficient. A back bias generator 27 is further connected to the guard ring 21, and the back bias generator 27 is connected to the drain region 5.
A voltage equal to or lower than an undesired negative voltage applied to the guard ring 21 is generated and applied to the guard ring 21. For example, if a negative voltage of about −3 V is expected to be applied to the drain region 5 due to chattering or the like, the back bias generator 27 may be set so that a voltage of −3 V or less can be applied to the guard ring. .

Next, a method of forming the embedded MOS transistor 26 will be described. Anisotropic etching from the surface of the substrate 1, for example,
The recess 22 is formed by reactive or ion etching, and then the polysilicon gate 23 and the silicon dioxide layer 25 are formed.

The latch-up prevention device for the C-MOS transistor having the above configuration will be described below.

First, a transient state in which a power supply voltage is applied to a logic circuit composed of C-MOS transistors will be described. In such a transient state, the back bias generator 27 is not functioning, the potential of the drain region 5 becomes lower than the potential of the well 2 for some reason, and the parasitic transistor 14 tends to be turned on. However, the guard ring 21 and the polysilicon gate 23 are connected to the ground potential VSS.
Therefore, when a current is supplied from the substrate 1 to the well 2 by the parasitic transistor 14 and the potential of the well 2 rises, the voltage between the well 2 and the polysilicon gate 23 becomes MO.
When the voltage is equal to or higher than the threshold of the S-transistor 26, a channel is formed between the electrode 23 as a gate and both regions of the transistor including the first and second regions 2 and 21. As a result, a current flows from the well 2 to the guard ring 21 through the channel and is further grounded, so that the potential of the well 2 is lowered and the parasitic transistor 14 can be kept in the OFF state.

Further, due to the rise in the potential of the well 2, the potential difference between the well 2 and the source region 4 becomes equal to or greater than the base-emitter barrier potential difference of the parasitic transistor 13, the parasitic transistor 14 is turned on, and the parasitic transistor 12 is also turned on. Even if a latch-up phenomenon occurs in the parasitic thyristor composed of the parasitic transistors 12 and 13, the potential of the well 2 is lowered as described above. It becomes less than the barrier potential difference between the emitters, and the latch-up phenomenon disappears. In addition, the embedded MOS transistor 26 causes the current path from the substrate 1 to the well 2 (that is, the parasitic transistor 1
Since the collector current path (2) is narrowed, the gain of the parasitic transistor 12 can be reduced to contribute to elimination of the latch-up phenomenon.

Next, when the transient state ends and the back bias generator 27 supplies a negative voltage to the guard ring 21, since the guard ring 21 and the well 2 are in ohmic contact, the well 2 is at a negative potential. Become. for that reason,
Even if the drain region 5 has a negative potential, the parasitic transistor 14 is unlikely to turn on, and the parasitic thyristor latch-up phenomenon is prevented.

FIG. 5 is a diagram showing a second embodiment of the present invention.
Is P-type, well 32 is N-type, guard ring 33 is N-type
_{It is +} doped. Therefore, the polysilicon gate 23 is connected to the power supply voltage VDD, and the back bias generator 34 is applied with a sufficient positive voltage, for example, 8V.

Further, it is needless to say that the present invention can be applied to a twin tap C-MOS transistor.

In the description of the above embodiment, each member is given a reference numeral, and the same reference numeral is used to identify the constituent elements described in the section of the claims. It is not intended to be limited to members.

<Effects of the Invention> As described above, according to the present invention, the first conductivity type substrate on which the second conductivity type MOS transistor is formed and the second conductivity type on the first conductivity type MOS transistor are formed. At the boundary with the well, a guard ring in which impurities of the second conductivity type are doped at a high concentration is formed, and an insulating layer is provided to insulate the gate penetrating the guard ring in the depth direction from the substrate and the well. By configuring the ring to be connected to a predetermined bias power supply, a transistor including the gate and the first and second regions (that is, the well and the guard ring) is formed in the depth direction of the substrate to substantially form the second transistor.
Area (that is, the guard ring) is ensured to have an effect equivalent to that of extending in the depth direction, so that the guard ring is formed as compared with the case where the guard ring is formed only by the diffusion layer as in the past. Since the width of each C-MOS transistor can be reduced, the area occupied by the substrate of each C-MOS transistor can be reduced, and a great improvement in the degree of integration can be achieved.

Further, since the vast well can be kept at the potential of the predetermined bias power source, the buried layer can be eliminated and the manufacturing process can be reduced. In particular, in a highly integrated random access memory, anisotropic etching such as formation of a trench type capacitor is used. Therefore, the step of forming the recess for filling the gate is performed simultaneously with the step of forming the trench type capacitor. By doing so, there is also an advantage that the latch-up prevention device can be formed without increasing the manufacturing process.

[Brief description of drawings]

FIG. 1 is a front sectional view showing a first embodiment of the present invention, and FIG.
FIG. 1 is a front sectional view showing a conventional latch-up prevention device, FIG. 3 is a partial plan view of FIG. 1, FIG. 4 is a partially enlarged view of FIG. 1, and FIG. 5 is a second embodiment of the present invention. It is a front sectional view showing an example. 1 ... Substrate, 2 ... Well, 4 ... Source region, 5 ... Drain region, 6 ... Gate region, 7 ... First conductivity type MOS transistor, 8 ... Drain region, 9 ... Source region, 10 ... Gate electrode, 11 ... Second conductivity type MOS transistor, 21, 33 ... Guard ring, 23 ... Gate (polysilicon gate), 25 ... Insulating layer (silicon dioxide layer), VSS, VDD ... Bias power supply.

Claims (1)

[Claims] 1. A first region 2 of a second conductivity type formed in an island shape on a surface of a substrate 1 of a first conductivity type, and a first region 2 at a boundary portion between the first region 2 and the substrate 1. And the insulating layer 2 formed so as to insulate the inner wall of the recess 22.
5, the second region 21 of the second conductivity type formed on the surface of the substrate 1 of the first conductivity type so as to be adjacent to the surface of the substrate 22 of the recess 22 and surround the recess 22, and the insulation in the recess 22. The electrode 23 is embedded in the layer 25 and is electrically connected to the second region 21, and the first region 2 and the second region 21 are formed in the depth direction of the substrate 1 along the recess 22. A transistor having the gate of the electrode 23 is formed between the region 21 and the first and second transistors when the difference between the potential of the first region 2 and the potential of the electrode 23 exceeds the threshold value of the transistor. A semiconductor device, wherein a channel is formed between regions 2 and 21.