JP6889048B2 - Silicon carbide semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and particularly relates to CMOS (complementary MOSFET).

Currently, most of the industrial products manufactured employ semiconductor devices made of silicon (hereinafter referred to as Si), and the performance has been greatly improved with the development of Si. On the other hand, general-purpose Si devices cannot be applied to products used in a high-temperature environment, and if a cooling device is provided as a countermeasure, it becomes difficult to reduce the size, weight, and cost of the product. In addition, even if a minute signal is output from a highly heat-resistant sensor, the information processing device that cannot withstand high temperatures is installed in a place far away from the device in which the sensor is installed, so the signal-to-noise ratio is sufficient. There is a problem that it cannot be secured.

On the other hand, as a device capable of operating at a high temperature, there is a semiconductor device having a substrate made of silicon carbide (hereinafter, may be referred to as SiC). A silicon carbide semiconductor device using SiC can be used as the information processing device even in a high temperature environment.

There are two types of SiC, a high temperature type (α type) having a hexagonal crystal structure and a low temperature type (β type) having a cubic crystal structure. The α-type SiC has a wider bandgap than the β-type SiC, and 4H-SiC, which is an α-type SiC, is suitable for a high temperature environment.

On the other hand, 4H-SiC is known to have relatively low channel mobility. Therefore, for example, in Patent Document 1 (Japanese Unexamined Patent Publication No. 2014-143248), in order to improve the mobility of 4H-SiC, a defect reduction layer is provided by introducing C (carbon) into a region where a channel is formed. It is stated that it will be provided. In addition, it is described that a BN pair structure is formed by N (nitrogen) diffusion between the channel region and the gate insulating film made of an oxide film or the like in order to stabilize the threshold voltage.

Japanese Unexamined Patent Publication No. 2014-143248

However, the MOSFET described in Patent Document 1 does not consider the p-type MOSFET (hereinafter referred to as pMOS), and does not necessarily improve the performance of CMOS in which the n-type MOSFET (hereinafter referred to as nMOS) and pMOS are combined. There is a problem that it cannot be done. That is, the channel mobility changes depending on the interface state between the SiC and the gate insulating film (presence or absence of nitride treatment, etc.), but the interface treatment that improves the electron mobility does not always contribute to the improvement of the hole mobility. , It is important to improve the mobility of both nMOS and pMOS carriers.

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.

A brief overview of typical embodiments disclosed in the present application is as follows.

Silicon carbide semiconductor devices according to a typical embodiment include a semiconductor substrate containing silicon carbide and having a hexagonal crystal structure, nNOS having the a-plane or m-plane of the semiconductor substrate as a channel region, and the semiconductor substrate. It has a pMOS having a Si plane or a C plane as a channel region.

According to a typical embodiment, the performance of the silicon carbide semiconductor device can be improved. In particular, the channel mobilities of nMOS and pMOS formed on the silicon carbide semiconductor substrate can be improved.

It is a perspective view which shows the silicon carbide semiconductor device which is Embodiment 1 of this invention. It is a circuit diagram which shows the silicon carbide semiconductor device which is Embodiment 1 of this invention. It is a top view which shows the silicon carbide semiconductor device which is Embodiment 1 of this invention. It is a perspective view during the manufacturing process of the silicon carbide semiconductor device which is Embodiment 1 of this invention. It is a perspective view during the manufacturing process of the silicon carbide semiconductor device following FIG. It is a perspective view in the manufacturing process of the silicon carbide semiconductor device which follows FIG. It is a perspective view during the manufacturing process of the silicon carbide semiconductor device following FIG. It is a perspective view in the manufacturing process of the silicon carbide semiconductor device which follows FIG. It is a perspective view during the manufacturing process of the silicon carbide semiconductor device following FIG. It is a perspective view during the manufacturing process of the silicon carbide semiconductor device following FIG. It is a top view which shows the silicon carbide semiconductor device which is the modification 1 of Embodiment 1 of this invention. It is a top view which shows the silicon carbide semiconductor device which is the modification 2 of Embodiment 1 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is the modification 3 of Embodiment 1 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is the modification 4 of Embodiment 1 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is the modification 5 of Embodiment 1 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is the modification 6 of Embodiment 1 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is Embodiment 2 of this invention. It is a top view which shows the silicon carbide semiconductor device which is Embodiment 2 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is Embodiment 3 of this invention. It is a perspective view which shows the silicon carbide semiconductor device which is Embodiment 4 of this invention. It is a perspective view which shows typically the hexagonal lattice model. It is a perspective view which shows typically the hexagonal lattice model. It is a perspective view which shows typically the hexagonal lattice model. It is a perspective view which shows typically the hexagonal lattice model. It is sectional drawing which shows the silicon carbide semiconductor device which is a comparative example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the embodiment, the explanation of the same or similar parts is not repeated in principle unless it is particularly necessary. Further, in the drawings for explaining the embodiments, hatching may be added even in a plan view or a perspective view in order to make the configuration easy to understand.

The sign ^"-" and ^"+", the conductive type represents the relative concentration of the n-type or p-type impurities, if for example, the n-type impurity, "n ^-", "n", " The impurity concentration increases in the order of " ^{n +".}

(Embodiment 1)
<Structure of silicon carbide semiconductor device>
Hereinafter, the structure of the silicon carbide semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 shows a perspective view of the silicon carbide semiconductor device according to the first embodiment of the present invention, and FIG. 2 shows a circuit diagram of a complementary field effect transistor which is the silicon carbide semiconductor device according to the present embodiment. , FIG. 3 shows a plan view of the complementary field effect transistor which is the silicon carbide semiconductor device of the present embodiment. In FIG. 1, the illustration of the insulating film including the gate insulating film and the interlayer insulating film on the SiC substrate and the wiring is omitted. In FIG. 1, the pMOS region 1A is shown on the left side of the figure, and the nMOS region 1B is shown on the right side of the figure. The pMOS region 1A and the nMOS region 1B are regions arranged in a direction along the main surface of the semiconductor substrate. In FIG. 3, the p-type diffusion layer 4 is hatched.

As shown in FIG. 1, the silicon carbide semiconductor device of the present embodiment is composed of a SiC substrate 1 having a hexagonal crystal structure and an epitaxial layer (semiconductor layer) 3 formed on the SiC substrate 1. The semiconductor substrate SB is formed of, and nMOS101 and pMOS102 are formed in the vicinity of the upper surface of the semiconductor substrate SB. The nMOS 101 and the pMOS 102 form a complementary field effect transistor having a MOS structure, that is, a CMOS (Complementary Metal Oxide Semiconductor). It is conceivable that the complementary field effect transistor of the present embodiment is mounted on a semiconductor device together with an IGBT (Insulated Gate Bipolar Transistor) or the like, or is used in a power module or an inverter.

As shown in FIG. 2, CMOS has a structure in which nMOS 101 and pMOS 102 are complementarily connected, and is between an electrode 105 to which a Vdd potential is applied and an electrode 106 to which a Vss potential (ground potential) is applied. The nMOS 101 and the pMOS 102 are connected in series. That is, the drain electrodes of nMOS 101 and pMOS 102 are connected to each other. The drain electrodes are connected to the output terminal (output electrode) 104, and the gate electrodes of the nMOS 101 and the pMOS 102 are connected to one input terminal 103. The source electrode of nMOS 101 is connected to the electrode 106, and the source electrode of pMOS 102 is connected to the electrode 105. The input terminal 103 and the output terminal 104, and the CMOS formed between these terminals form a NOT circuit.

As shown in FIG. 1, the SiC substrate 1 has a Si plane, that is, a (000-1) plane as a main plane among hexagonal planes, and a C plane, that is, a (0001) plane is the opposite of the main plane. It is an n-type semiconductor substrate that has a back surface on the side. Similarly, the epitaxial layer 3 having a hexagonal crystal structure made of SiC has the Si surface as the main surface among the hexagonal surfaces, and the lower surface on the opposite side of the main surface of the epitaxial layer 3 is the SiC substrate 1. It is in contact with the main surface of.

Here, various planes of the hexagonal crystal structure will be described with reference to FIGS. 21 to 24. 21 to 24 are perspective views schematically showing a hexagonal lattice model. In the lattice model shown in FIGS. 21 to 24, some crystal planes are hatched. Further, the C (carbon) atom is indicated by a black ball, and the Si (silicon) atom is indicated by a white ball.

In FIGS. 21 to 24, the horizontal axis shows the respective axes of a1, a2, and a3 located in the same horizontal plane, and the vertical axis indicates the direction perpendicular to the respective axes of a1, a2, and a3. It shows the c-axis to go. The axes of a1, a2, a3 and c extend from the same reference point. In a plan view, the angle formed by the axes of a1, a2, and a3 is 120 degrees.

The plane of the hexagonal lattice model is represented by four indices (plane indices) of (a1, a2, a3, c). In the surface index below, "2" means 1/2 and "-" means the opposite direction of the axis. For example, on the (1-102) plane, a1 = 1, a2 = -1, a3 = 0, and c = 2.

SiC is a compound semiconductor of Si (silicon) and C (carbon), and is composed of covalent bonds between groups IV. As shown in FIG. 21, the crystal structure has a regular tetrahedron having a Si atom or a C atom as a vertex as a basic element, and is laminated in the c-axis direction. In 4H-SiC, the surface on which Si (silicon) is exposed on the outermost surface is called the (000-1) surface or the Si surface, and the surface on which C (carbon) is exposed is called the (0001) surface or the C surface. FIG. 21 shows a (0001) plane (C plane) 201 and a (000-1) plane (Si plane) 202. The C-plane 201 and the Si-plane 202 correspond to the upper surface or the lower surface of the hexagonal crystal shown in FIG.

The (0-110) plane that is perpendicular to the C-plane 201 (see FIG. 21) and corresponds to the side surface of the hexagonal crystal is called the m-plane, and is also perpendicular to the C-plane 201 (see FIG. The (11-20) plane is called the a-plane. FIG. 22 shows the (11-20) plane (a plane) 203 and the (0-110) plane (m plane) 204. In addition, the (10-11) plane oblique to the C plane 201 (see FIG. 21), that is, the S plane 205 (see FIG. 23) or the C plane 201 (see FIG. 21) diagonally. There is a (1-102) plane, that is, an r plane 206 (see FIG. 24). In a silicon carbide semiconductor device using a SiC substrate, a wafer having a Si plane or a C plane as a main plane tends to have a larger diameter than a wafer having a crystal plane other than the Si plane and the C plane as a main plane. Therefore, in the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed on the SiC substrate, the Si plane or C plane which is the main plane of the channel, or the a plane or m plane which is perpendicular to the main plane of the substrate. Can be used.

In the silicon carbide semiconductor device of the present embodiment, the semiconductor substrate SB (see FIG. 1) made of 4H-SiC described with reference to FIGS. 21 to 24 is used. In FIG. 21, a hexagonal crystal having a C-plane 201 on the upper surface and a Si-plane 202 on the lower surface is shown, but the upper surface of the semiconductor substrate SB (see FIG. 1) made of the hexagonal crystal is the Si-plane and the lower surface is the C-plane. is there. As shown in FIG. 1, the silicon carbide semiconductor device of the present embodiment includes a semiconductor substrate SB composed of an n-type SiC substrate 1 and an n-type epitaxial layer 3. The semiconductor substrate SB has a hexagonal lattice structure shown in FIGS. 21 to 24. The SiC substrate 1 and the epitaxial layer 3 have a structure in which, for example, N (nitrogen) is introduced as an n-type impurity into a semiconductor layer made of SiC. The concentration of n-type impurities in the SiC substrate 1 is higher than the concentration of n-type impurities in the epitaxial layer 3.

The back surface of the semiconductor substrate SB, that is, the back surface of the SiC substrate 1, is covered with the back surface electrodes 2. The back surface electrode 2 in contact with the back surface of the semiconductor substrate SB is, for example, an electrode made of a conductor containing Au (gold) and to which, for example, a Vdd potential is applied. In the nMOS region 1B, a p-type diffusion layer (p-type semiconductor layer) 4 is formed on a part of the main surface of the semiconductor substrate SB, that is, a part of the upper surface of the epitaxial layer 3. The lower surface of the p-type diffusion layer 4 does not reach the interface between the SiC substrate 1 and the epitaxial layer 3, but reaches the intermediate depth of the epitaxial layer 3. On the upper surface of the p-type diffusion layer 4, a plurality of grooves 8 extending in the Y direction are formed side by side in the X direction. The depth of the groove 8 is shallower than the depth of the p-type diffusion layer 4. Although only two grooves 8 are shown in FIG. 1, more grooves 8 may be formed side by side in the X direction. The X direction is a direction along the main surface of the semiconductor substrate SB. The Y direction is a direction along the main surface of the semiconductor substrate SB, and is a direction orthogonal to the X direction.

The side surface of the groove 8 is the main surface of the semiconductor substrate SB, that is, the surface perpendicular to the Si surface, and is the a surface of the semiconductor substrate SB. That is, the crystal plane of the side surface of the groove 8 extending in the Y direction is the a-plane of the epitaxial layer 3 made of SiC. In other words, the Y direction is a direction along the a-plane and m-plane of the semiconductor substrate SB composed of hexagonal crystals whose main plane is the Si plane.

As shown in FIGS. 1 and 3, the gate electrode 10 is completely embedded in the groove 8 via the gate insulating film 9. The gate insulating film 9 is made of, for example, a silicon oxide film and covers the side surface and the bottom surface of the groove 8. The gate electrode 10 is made of, for example, polysilicon, Al (aluminum) or W (tungsten). A drain region 5, a source region 6 and a p-type contact layer 7 are formed in this order on the upper surface of the p-type diffusion layer 4 between the grooves 8 adjacent to each other in the X direction.

Each of the drain region 5 and the source region 6 is an n-type semiconductor region, and is formed by introducing an n-type impurity (for example, N (nitrogen)) into the main surface of the semiconductor substrate SB. The p-type diffusion layer 4 and the p-type contact layer 7 are p-type semiconductor regions, and are formed by introducing p-type impurities (for example, Al (aluminum)) into the main surface of the semiconductor substrate SB. The n-type impurity concentration of each of the drain region 5 and the source region 6 is higher than the n-type impurity concentration of the epitaxial layer 3. Further, the p-type impurity concentration of the p-type diffusion layer 4 is higher than the p-type impurity concentration of the p-type contact layer 7. The p-type contact layer 7 has a role of fixing the potential of the p-type diffusion layer 4 and maintaining the potential difference between the gate electrode 10 and the p-type diffusion layer 4.

The drain region 5 and the source region 6 are separated in the Y direction, and a p-type diffusion layer 4 is formed on the main surface of the semiconductor substrate SB in the region between the drain region 5 and the source region 6. There is. Both ends of the drain region 5, the source region 6 and the p-type contact layer 7 in the X direction are terminated by the side surfaces of the grooves 8 adjacent to each other. That is, both ends of the drain region 5, the source region 6, and the p-type contact layer 7 in the X direction are in contact with the side surfaces of the gate insulating film 9. In other words, each of the drain region 5, the source region 6 and the p-type contact layer 7 is formed on the side surface of the groove 8. Similarly, both ends of the p-type diffusion layer 4 between the drain region 5 and the source region 6 in the Y direction in the X direction are terminated by the side surfaces of the grooves 8 adjacent to each other and are in contact with the side surfaces of the gate insulating film 9. ing.

In the Y direction, the source region 6 and the p-type contact layer 7 are in contact with each other. As shown in FIG. 3, the p-type contact layer 7 is sandwiched between two source regions 6 in the Y direction. Here, in the Y direction, the drain region 5, the p-type diffusion layer 4, the source region 6, the p-type contact layer 7, the source region 6, the p-type diffusion layer 4, and the drain region 5 are formed in this order.

The nMOS 101 is composed of a gate electrode 10 in the groove 8, a drain region 5, and a source region 6. That is, the nMOS 101 is a so-called trench gate type MOSFET. Between the drain region 5 and the source region 6 adjacent to each other, the side surface of the p-type diffusion layer 4 adjacent to the gate electrode 10 via the gate insulating film 9 is a region (channel region) in which a channel is formed during the operation of the nMOS 101. ). That is, the nMOS 101 is a field effect transistor having a channel on the side surface of the groove 8 which is the side surface of the semiconductor substrate SB, not on the main surface (Si surface) of the semiconductor substrate SB.

The side surface of the groove 8 extending in the Y direction is the a-plane perpendicular to the main surface of the semiconductor substrate SB. Between the drain region 5 and the source region 6, the operating current of the nMOS 101 mainly flows to the side surface of the groove 8 extending in the Y direction, that is, the side surface of the p-type diffusion layer 4, and the drain region 5 Even within the p-type diffusion layer 4 between the source region 6 and the source region 6, the current flowing in the region between the grooves 8 adjacent to each other in the X direction and away from the side surface of the groove 8 is very large. small.

Further, a plurality of contact plugs (conductive connection portions) 15 are formed on the semiconductor substrate SB. Each contact plug 15 is electrically connected to electrodes (wiring, terminals) formed on them. The input terminal 103, the output electrode (output terminal) 104, and the electrodes 105 and 106 are all formed on the contact plug 15. A Vss potential is applied to the contact plugs 15 arranged so as to straddle the upper surfaces of the source region 6 and the p-type contact layer 7 and electrically connected to the source region 6 and the p-type contact layer 7, respectively. It is connected to the electrode 106. The contact plug 15 connected to the upper surface of the drain region 5 is electrically connected to the output electrode 104. The contact plug 15 connected to the upper surface of the gate electrode 10 is electrically connected to the input terminal (gate wiring) 103.

As shown in FIGS. 1 and 3, in the pMOS region 1A, a pair of drain regions 11 extending in the Y direction and adjacent to each other in the X direction on the main surface of the semiconductor substrate SB, that is, the upper surface of the epitaxial layer 3, and The source region 12 is formed. The drain region 11 and the source region 12 are separated from each other in the X direction, and an n-type epitaxial layer 3 is formed on the main surface of the semiconductor substrate SB between the drain region 11 and the source region 12 adjacent to each other in the X direction. Has been done. Each of the drain region 11 and the source region 12 is a p-type semiconductor region formed by introducing a p-type impurity (for example, Al (aluminum)) on the upper surface of the epitaxial layer 3.

A gate electrode 14 is formed directly above the upper surface of the epitaxial layer 3 between the drain region 11 and the source region 12 adjacent to each other in the X direction via a gate insulating film (not shown). The gate electrode 14 is made of, for example, polysilicon, Al (aluminum) or W (tungsten). The gate insulating film (not shown) is made of, for example, a silicon oxide film. The gate electrode 14 extends in the Y direction. Although the gate electrode 14 is not shown in FIG. 3, the gate electrode 14 is formed directly below the portion of the input terminal (gate wiring) 103 extending in the Y direction.

An n-type contact layer 13 is formed on the main surface of the semiconductor substrate SB so as to be in contact with the side surface of the source region 12 that does not face the drain region 11. The gate electrode 14 and the n-type contact layer 13 do not overlap in a plan view. The n-type contact layer 13 is an n-type semiconductor region formed by introducing n-type impurities (for example, N (nitrogen)) on the upper surface of the epitaxial layer 3, and the n-type impurity concentration of the n-type contact layer 13 is epitaxial. It is higher than the n-type impurity concentration of layer 3. The depths of the drain regions 5, 11, the source regions 6, 12 and the n-type contact layer 13 are equal to each other, and none of them reaches the interface between the epitaxial layer 3 and the SiC substrate 1. The n-type contact layer 13 has a role of fixing the potential of the epitaxial layer 3 and keeping the potential difference between the gate electrode 14 and the epitaxial layer 3 constant.

The drain region 11, the source region 12, and the gate electrode 14 formed in the pMOS region 1A constitute the pMOS 102. That is, the pMOS 102 is a so-called planar MOSFET. The upper surface of the epitaxial layer 3 adjacent to the gate electrode 14 via the gate insulating film (not shown) between the drain region 11 and the source region 12 adjacent to each other is a region (channel) in which a channel is formed during the operation of the pMOS 102. Area). That is, the pMOS 102 is a field effect transistor having a channel on the Si plane, which is the crystal plane of the main plane of the semiconductor substrate SB.

As shown in FIG. 3, the electrically connected contact plugs 15 of the source region 12 and the n-type contact layer 13 are connected to the electrode 105 to which the Vdd potential is applied. The contact plug 15 connected to the upper surface of the drain region 11 is electrically connected to the output electrode 104. The contact plug 15 connected to the upper surface of the gate electrode 10 is electrically connected to the input terminal (gate wiring) 103. The output electrode 104 electrically connected to the drain region 5 of the nMOS 101 and the drain region 11 of the pMOS 102 has a comb-like layout, and is electrically connected to the source region 6 of the nMOS 101 and the p-type contact layer 7. The electrode 106 connected to has a comb-like layout. That is, each of the output electrode 104 and the electrode 106 has a pattern extending in the Y direction and a plurality of comb-shaped patterns connected to the pattern and extending in the X direction. In the figure, only one of the plurality of comb-shaped patterns constituting the electrode 106 is shown. The comb-shaped pattern forming the output electrode 104 and the comb-shaped pattern forming the electrode 106 are arranged so as to be staggered.

The main feature of this embodiment is that the CMOS is composed of a planar type pMOS 102 and a trench gate type nMOS 101, the crystal plane on which the pMOS 102 channel is formed is the Si plane, and the nMOS 101 channel is formed. The crystal plane is the a-plane.

<Manufacturing method of silicon carbide semiconductor device>
Hereinafter, the method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 10. 4 to 10 are perspective views during the manufacturing process of CMOS, which is the silicon carbide semiconductor device of the first embodiment. 4 to 10 show the pMOS region 1A and the nMOS region 1B as in FIG. 1. Here, a SiC wafer having a Si surface as a main surface will be described in mind, but it goes without saying that the structure of the MOSFET is appropriately changed depending on the crystal plane. Further, a manufacturing process of a gate insulating film, an interlayer insulating film, a contact plug, an electrode and the like, which are not shown in FIG. 1, will also be described here.

^{First, as shown in FIG. 4, an n +} type SiC substrate 1 having a main surface and a back surface on the opposite side of the main surface is prepared. The SiC substrate 1 is a semiconductor substrate made of SiC (silicon carbide) and having a hexagonal crystal structure. The crystal plane of the main surface of the SiC substrate 1 is the Si surface. Subsequently, the epitaxial layer 3 is formed on the main surface of the SiC substrate 1 by using the epitaxial growth method. The epitaxial layer 3 has a hexagonal crystal structure, and the crystal plane of the main surface of the epitaxial layer 3 is a Si plane. Here, the epitaxial layer 3 can be formed at a desired impurity concentration by growing the epitaxial layer 3 while introducing an n-type impurity (for example, N (nitrogen)) into the epitaxial layer 3.

Next, as shown in FIG. 5, a p-type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 3 by using a photolithography technique and an ion implantation method. As a result, a p-type contact layer 7, a drain region 11, a source region 12, and an element separation layer (not shown), which are ^{p +} type semiconductor regions, are formed on the upper surface of the epitaxial layer 3. The p-type contact layer 7 reaches from the upper surface of the epitaxial layer 3 to an intermediate depth of the epitaxial layer 3 and is formed in the nMOS region 1B. The drain region 11 and the source region 12 reach from the upper surface of the epitaxial layer 3 to an intermediate depth of the epitaxial layer 3 and are formed in the pMOS region 1A. The drain region 11 and the source region 12 are separated from each other.

Next, a p-type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 3 using a photolithography technique and an ion implantation method. As a result, the p-type diffusion layer 4, which is a p-type semiconductor region, is formed on the upper surface of the epitaxial layer 3 in the nMOS region 1B. The p-type diffusion layer 4 has a lower p-type impurity concentration than the p-type contact layer 7, and is deeper than the p-type contact layer 7. However, the lower surface of the p-type diffusion layer 4 does not reach the interface between the epitaxial layer 3 and the SiC substrate 1. Here, the p-type diffusion layer 4 is formed at a position overlapping the p-type contact layer 7 and the region around the p-type contact layer 7 in a plan view.

Next, as shown in FIG. 6, an n-type impurity (for example, N (nitrogen)) is implanted into the upper surface of the epitaxial layer 3 by using a photolithography technique and an ion implantation method. As a result, the drain region 5, the source region 6, and the n-type contact layer 13, which are ^{n +} type semiconductor regions, are formed on the upper surface of the epitaxial layer 3. The drain region 5 and the source region 6 are formed in the nMOS region 1B, and the n-type contact layer 13 is formed in the pMOS region 1A. The drain region 5 and the source region 6 are formed so as to be separated from each other, and the source region 6 is formed adjacent to the p-type contact layer 7. The depths of the drain region 5 and the source region 6 are shallower than the depth of the p-type diffusion layer 4. The n-type contact layer 13 is formed at a position adjacent to the source region 12.

Next, as shown in FIG. 7, a plurality of grooves 8 are formed on the main surface of the p-type diffusion layer 4 in the nMOS region 1B by using a photolithography technique and an etching method. The groove 8 is formed in the p-type diffusion layer 4 in a plan view, and the bottom portion of the groove 8 does not reach the boundary between the lower surface of the p-type diffusion layer 4 and the epitaxial layer 3. Here, two or more grooves 8 are formed so as to sandwich the drain region 5, the source region 6, and the p-type contact layer 7 arranged in the Y direction in the X direction. The drain region 5, the source region 6 and the p-type contact layer 7 are exposed on one side surface of the groove 8 extending in the Y direction. The crystal plane of the side surface of the groove 8 where the drain region 5, the source region 6 and the p-type contact layer 7 are exposed, that is, the surface extending in the Y direction is the a-plane.

Next, as shown in FIG. 8, the inside of the groove 8 is formed by forming a relatively thin insulating film 22 and a conductive film in order on the epitaxial layer 3 by using, for example, a CVD (Chemical Vapor Deposition) method. Fully embed. The insulating film 22 is made of, for example, a silicon oxide film, and the conductive film is made of, for example, polysilicon, Al (aluminum), W (tungsten), or the like.

Subsequently, the conductive film is processed by using a photolithography technique and an etching method to expose a part of the upper surface of the insulating film 22. As a result, the gate electrodes 10 and 14 made of the conductive film are formed. The gate electrode 10 is formed inside each of the plurality of grooves 8 of the nMOS region 1B, and the gate electrode 14 is an insulating film on the epitaxial layer 3 between the drain region 11 and the source region 12 in the pMOS region 1A. It is formed via 22. The gate electrode 10, the drain region 5, and the source region 6 constitute the nMOS 101. The gate electrode 14, the drain region 11, and the source region 12 constitute the pMOS 102.

Here, the insulating film 22 embedded in the groove 8 and covering the side surface and the bottom surface of the gate electrode 10 constitutes the gate insulating film 9. The thickness of the gate insulating film 9 in contact with the side surface of the groove 8 and the thickness of the gate insulating film 9 in contact with the bottom surface of the groove 8 are equal to each other.

When each of the gate electrodes 10 and 14 is formed of different materials, for example, after forming the insulating film 22 and the gate electrode 10, a conductive film is formed on each of the insulating film 22 and the gate electrode 10, and then a conductive film is formed. The gate electrode 14 is formed by processing the conductive film.

When each of the gate electrodes 10 and 14 is formed of a semiconductor film, here, both the conductive types of the gate electrodes 10 and 14 are aligned to the n-type or the p-type. As a result, the manufacturing cost of the silicon carbide semiconductor device can be reduced as compared with the case where the gate electrodes 10 and 14 are formed of separate conductive semiconductor films. Examples of the method of introducing impurities into the semiconductor film include a method of introducing impurities into the semiconductor film at the time of film formation by the CVD method, and an ion implantation method of the semiconductor film after the film formation of the semiconductor film. There is a method of introducing impurities using. The n-type impurity introduced into the semiconductor film includes, for example, P (phosphorus), and the p-type impurity introduced into the semiconductor film includes, for example, B (boron).

Next, as shown in FIG. 9, for example, a CVD method is used to form an interlayer insulating film 19 on each of the epitaxial layer 3, the insulating film 22, and the gate electrodes 10 and 14. The interlayer insulating film 19 is made of, for example, a silicon oxide film. Here, the interlayer insulating film 19 covers the side surface and the upper surface of the gate electrode 14, the upper surface of the gate electrode 10, and the upper surface of the insulating film 22. Subsequently, the interlayer insulating film 19 is penetrated through the interlayer insulating film 19 and the insulating film 22 by using a photolithography technique and an etching method to form a plurality of connection holes that expose the upper surface of the epitaxial layer 3. At the bottom of each connection hole, source regions 6 (see FIG. 7), 12, drain regions 5, 11, p-type contact layers 7 (see FIG. 7) or n-type contact layers 13 are an interlayer insulating film 19 and an insulating film 22. Exposed from a laminated film consisting of. By processing the insulating film 22 by this step, a gate insulating film 23 made of the insulating film 22 is formed directly under the gate electrode 14.

FIG. 9 does not show the connection holes opened directly above the gate electrodes 10 and 14, respectively. Those connection holes are formed in a region (not shown). The source region 12 and the n-type contact layer 13 are exposed at the bottom of the same connection hole. Further, the source region 6 (see FIG. 7) and the p-type contact layer 7 (see FIG. 7) are exposed at the bottom of the same connection hole.

Next, as shown in FIG. 10, a metal film is formed on the epitaxial layer 3 including the inside of each connection hole and on the interlayer insulating film 19 by using, for example, a sputtering method. The metal film is made of, for example, Al (aluminum), and completely embeds the inside of each of the plurality of connection holes. Subsequently, the metal film on the interlayer insulating film 19 is processed by using a photolithography technique and an etching method to expose a part of the upper surface of the interlayer insulating film 19. By this processing step, the metal film is separated into a plurality of electrodes to form a plurality of electrodes composed of the metal film. That is, the electrode 105 to which the Vdd potential is applied, the electrode 106 to which the Vss potential is applied, and the output electrode 104 are formed.

The electrode 105 is connected to the n-type contact layer 13 and the source region 12 via a contact plug made of the metal film in the connection hole. The electrode 106 is connected to the p-type contact layer 7 (see FIG. 7) and the source region 6 (see FIG. 7) via a contact plug made of the metal film in the connection hole. The output electrode 104 is connected to the drain regions 5 and 11 via a contact plug. Subsequently, for example, a sputtering method is used to form the back surface electrode 2 that covers the back surface of the SiC substrate 1. The back surface electrode 2 is, for example, a conductive film containing Au (gold), and is, for example, an electrode to which a Vdd potential is applied. The nMOS 101 and pMOS 102 to which the drains are connected to each other constitute CMOS.

By the above steps, CMOS, which is the silicon carbide semiconductor device of the present embodiment, can be formed.

<Effect of this embodiment>
Hereinafter, the effect of the present embodiment will be described with reference to FIG. 25 as a comparative example. FIG. 25 is a cross-sectional view showing a silicon carbide semiconductor device as a comparative example.

As a material for a semiconductor substrate used in a semiconductor device, it is conceivable to use Si (silicon). However, industrial equipment installed near machines that generate high heat, such as automobile engines, aircraft turbine engines, and boilers that generate high temperatures themselves, are exposed to high temperatures that cannot drive semiconductor devices that use Si substrates. Therefore, it is difficult to use a Si substrate for such a semiconductor device. Further, if a cooling device for cooling a semiconductor device used in a high temperature environment is provided, it hinders the reduction in size, weight and cost of the device.

Further, it is conceivable to install an information processing device that cannot withstand high temperatures in a place far away from a device that generates high heat. However, even if a minute output signal is output from the highly heat-resistant sensor, there is a problem that a sufficient signal-to-noise ratio cannot be secured because the current path is long. For this reason, complicated noise processing is required, which also hinders reduction in size, weight, and cost. In order to reduce the influence of noise at low cost, so-called edge computing, which processes the output signal in the immediate vicinity of the sensor even in a high temperature environment, is effective, and the highly heat-resistant integrated device LSI (Large Scale) that supports it is effective. Creation of Integration) is indispensable.

On the other hand, as a device that can be used in a high temperature environment, there is a silicon carbide semiconductor element using a substrate made of SiC (silicon carbide), and as a material for a substrate of a silicon carbide semiconductor device used in a high temperature environment, 4H -SiC is suitable. On the other hand, 4H-SiC has a lower channel mobility than Si. As a countermeasure, it is conceivable to form a silicon carbide semiconductor device as shown in FIG. 25 as a comparative example.

As shown in FIG. 25, the silicon carbide semiconductor device of the comparative example includes nMOS107 in the vicinity of the main surface of the semiconductor substrate SB including the SiC substrate 1 and the epitaxial layer 3 on the SiC substrate 1. ^{A pair of p-} type SiC regions 321 separated from each other are formed on the upper surface of the epitaxial layer 3, ^{and n +} type SiC regions 322 and p ⁺ type ^{adjacent to each other are formed on the upper surface of each p-} type SiC region 321. The SiC region 323 is formed. Further, from the opposite ends of the pair of p ^- type SiC regions 321 to the ends of the n ⁺ -type SiC regions 322, ^{the upper surface of each p-} type SiC region 321 has a channel region (defect reduction layer). ) 324 is formed. A BN pair structure insulating film 325 in contact with the upper surface is formed on the upper surface of the channel region 324.

The channel region 324 is a region in which C (carbon) defects are reduced by introducing C (carbon) on the upper surface of the epitaxial layer 3. The BN pair structure insulating film 325 is a film formed by diffusing N (nitrogen) on the upper surface of the channel region 324. In the BN pair structure insulating film 325, ^{B (boron) in the p-} type SiC region 321 attracts the N (nitrogen), and a stable BN pair is formed.

A gate electrode 340 is formed on the upper surface of the epitaxial layer 3 between each of the pair of p ^{-type SiC regions 321 via a gate insulating film 330.} The gate insulating film 330 and the gate electrode 340 ^{cover the BN pair structure insulating film 325 on the upper surface of each of the pair of p-} type SiC regions 321, the channel region 324, and a part of the n ⁺ -type SiC region 322. .. A source electrode 350 is connected to the upper surfaces of ^{the n +} type SiC region 322 and the p ⁺ type SiC region 323 formed on the upper surface of one of the p ^- type SiC regions 321 of the pair of p ^{-type SiC regions 321.} A source electrode 350 is connected to the upper surfaces of ^{the n +} -type SiC region 322 and the p ⁺ -type SiC region 323 formed on the upper surface of the other p ^{-type SiC region 321.}

Here, for the purpose of improving the mobility (channel mobility) of the nMOS 107, a channel region 324 in which C is introduced is provided. Further, for the purpose of stabilizing the threshold voltage of the nMOS 107, a BN pair structure insulating film 325 is formed by N diffusion between the channel region 324 and the gate insulating film 330 made of an oxide film or the like. ..

However, in the MOSFET of the comparative example, improvement of the mobility of pMOS is not considered, and there is a problem that the performance of CMOS in which nMOS and pMOS are combined cannot always be improved.

Here, the channel mobility, which indicates the ease of current flow in a transistor or the like, differs depending on the crystal plane of the hexagonal crystal, and also changes depending on the carrier (electron or hole). This is because there is a difference between the proportion of defects that obstruct the flow of electrons and the proportion of defects that obstruct the flow of holes, depending on the crystal plane. The mobility has a correlation with the interface defect. For example, in the nMOS having an electron as a carrier, it can be said that it is preferable that a channel is formed on the a-plane ^{in which the interface defect in the vicinity of the conduction band is 1 × 10 12} cm ^{2 eV or less.} However, in pMOS having holes as carriers, the interface defect on the a-plane is 3 × 10 ^{12 to} 5 × 10 ¹² cm ² eV, which is large. Therefore, when the pMOS channel is formed on the a-plane, the mobility is increased. Difficult to improve. On the other hand, when the pMOS channel is formed on the Si surface, the interface defect near the valence band ^{is as low as 5 × 10 11} cm ² eV, and an improvement in mobility can be expected.

In this embodiment, when nMOS and pMOS are formed on a SiC substrate made of hexagonal crystals, the mobility of both nMOS and pMOS is improved by selecting the crystal plane of each MOSFET channel. .. That is, here, in the pMOS having holes as carriers, by setting the channel to the Si plane or the C plane, the mobility is improved as compared with the case where the channel is formed on another crystal plane. In the nMOS having electrons as carriers, attention is paid to the fact that the mobility is improved by setting the channel to the a-plane as compared with the case where the channel is formed on another crystal plane.

Therefore, as shown in FIG. 1, among the MOSFETs constituting the CMOS, by forming the pMOS 102 as a planar type MOSFET, the channel (channel region) is formed on the main surface of the semiconductor substrate SB which is the Si surface. There is. Further, among the MOSFETs constituting the CMOS, by forming nMOS101 as a trench gate type MOSFET, the channel (channel region) is formed on the a-plane perpendicular to the main surface of the semiconductor substrate SB which is the Si-plane. There is. As a result, the mobility of the pMOS 102 can be improved and the mobility of the nMOS 101 can be improved at the same time, instead of improving the mobility of only the nMOS as in the comparative example. Therefore, it is possible to improve the performance of the silicon carbide semiconductor device of the present embodiment including the CMOS composed of nMOS101 and pMOS102.

In the present embodiment, the case where the crystal plane on which the channel of pMOS 102 is formed is the Si plane is described, but the same effect can be obtained when the crystal plane on which the channel of pMOS 102 is formed is the C plane. Can be obtained.

Further, in the present embodiment, the case where the crystal plane on which the channel of nMOS 101 is formed is the a-plane is described. On the other hand, when the channel is formed on the m-plane, the mobility of the nMOS 101 is inferior to that when the channel is formed on the a-plane, but the nMOS channel is formed on the crystal planes other than the a-plane and the m-plane. The mobility can be improved as compared with the case where it is formed. In other words, the mobility can be improved by forming the nMOS 101 having a channel on the a-plane or the m-plane, and in particular, the mobility can be remarkably improved in the nMOS 101 having a channel on the a-plane. Since the a-plane and the m-plane are planes perpendicular to the Si-plane and the C-plane, the groove 8 is formed on the main plane of the semiconductor substrate SB in which the crystal plane of the main plane is the Si-plane or the C-plane. The surface or m surface can be exposed on the side surface of the groove 8.

Hereinafter, modifications and other embodiments of this embodiment will be described. In any of the embodiments and modifications, the pMOS in which the channel is formed on the Si plane and the channel are formed on the a plane. By forming the nMOS, the mobility of the pMOS 102 can be improved and the mobility of the nMOS 101 can be improved at the same time.

<Modification example 1>
FIG. 11 shows a plan view of a silicon carbide semiconductor device which is a modification 1 of the first embodiment. In the trench gate type nMOS of the present embodiment, it is conceivable to form a p-type contact layer adjacent to the source region and sandwich the p-type contact layer between two source regions. In this case, the source region width of the nMOS is considered. Therefore, it becomes difficult to miniaturize the silicon carbide semiconductor device. The source region width referred to here is the case where a plurality of channel regions sandwiched between the source region and the drain region are provided in the direction in which the source region and the drain region are lined up, that is, in the extending direction (Y direction) of the trench gate electrode. The distance between both ends of the source region in the direction, and refers to the distance between the boundaries between the channel region and the source region, which are both ends of the source region. Therefore, the width of the source region when the p-type contact layer is sandwiched between the two source regions is the end of each of the two source regions opposite to the end adjacent to the p-type contact layer. Refers to the distance between.

Therefore, in this modification, FIG. 11 shows a layout in which the source region width of the nMOS can be shortened. As shown in FIG. 11, an annular p-type contact layer 7 is formed so as to surround the plurality of grooves 8 in a plan view. As a result, it is not necessary to form the p-type contact layer 7 at a position adjacent to the source region 6, so that the width of the source region in the Y direction can be shortened. Further, by forming the p-type contact layer 7 so as to surround the groove 8, the p-type contact layer 7 can also function as an element separation layer.

<Modification 2>
FIG. 12 shows a plan view of the silicon carbide semiconductor device which is the second modification of the first embodiment. In the trench gate type nMOS of the present embodiment, in order to reduce the width of the source region, it is conceivable to form a p-type contact layer surrounding a plurality of trench gate electrodes in a plan view. However, in this case, since the distance between the channel formed between the source region and the drain region and the p-type contact layer is relatively large, the potential of the p-type diffusion layer in the vicinity of the channel may not be stable. That is, there is a possibility that the potential difference between the p-type diffusion layer and the trench gate electrode becomes large.

Therefore, FIG. 12 shows a layout in which the width of the source region of the nMOS 101 can be shortened and the potential of the p-type diffusion layer 4 can be made more stable. Here, the groove 8 is not surrounded by the p-type contact layer 7 in a plan view, and the p-type contact layer 7 is formed in a region adjacent to the groove 8 in the X direction via the source region 6. That is, in the X direction, two source regions 6 and a p-type contact layer 7 sandwiched between the two source regions 6 are arranged between adjacent grooves 8. The p-type contact layer 7 is in contact with the source region 6 between the p-type contact layer 7 and the groove 8.

In this modification, as compared with the case where the p-type contact layer 7 is not formed between the adjacent grooves 8 and the p-type contact layer 7 is formed so as to surround each groove 8 in a plan view, the p-type diffusion layer is formed. Since the in-plane variation of the potential of 4 can be suppressed, the threshold voltage of nMOS 101 can be stabilized.

<Modification example 3>
FIG. 13 shows a perspective view of a silicon carbide semiconductor device which is a modification 3 of the first embodiment.

As shown in FIG. 13, in this modification, the drain region 5, the source region 6 and the n-type contact layer 13 are deeper than the drain region 11, the source region 12 and the p-type contact layer 7, respectively, and the gate electrode 10 of the nMOS 101 is formed. It is formed at a shallower depth. By forming the drain region 5 and the source region 6 deeply in this way, the width of the region where the drain region 5 and the source region 6 face each other, that is, the channel width increases, so that the depths of the drain region 5 and the source region 6 are increased. Can reduce the channel resistance of the nMOS 101 as compared to the case where is equivalent to the drain region 11 and the source region 12.

Here, since the n-type contact layer 13 is formed in the same ion implantation step as the drain region 5 and the source region 6, it is formed as deep as the drain region 5 and the source region 6.

<Modification example 4>
FIG. 14 shows a perspective view of a silicon carbide semiconductor device which is a modification 4 of the first embodiment. The structure of this modification is different from the structure shown in FIG. 1 only in a part of the thickness of the gate insulating film 9, and the other structures are the same as the structure shown in FIG.

As shown in FIG. 14, in the CMOS of the present modification, the thickness of the gate insulating film 9 formed in contact with the bottom surface of the groove 8 is larger than the thickness of the gate insulating film 9 formed in contact with the side surface of the groove 8. It is characterized by its large size. Due to this feature, the bottom surface of the groove 8 is inverted as compared with the case where the thickness of the gate insulating film 9 in contact with the bottom surface of the groove 8 is as thin as the thickness of the gate insulating film 9 in contact with the side surface of the groove 8. Layers are less likely to occur. As a result, the threshold voltage of the nMOS 101 on the bottom surface of the groove 8 can be made larger than the threshold voltage of the nMOS 101 on the side surface of the groove 8. That is, the influence of the current flowing on the bottom surface of the groove 8 on the current flowing through the nMOS 101 can be reduced.

In the trench gate type nMOS 101, the crystal plane in which the channel is formed on the side surface of the groove 8 and the crystal plane in which the channel is formed on the bottom surface of the groove 8 are different. Therefore, when the thickness of the gate insulating film 9 covering each of the side surface and the bottom surface of the groove 8 is the same, a current flows through each of the two different crystal planes. For example, when the crystal plane on the side surface of the groove 8 of the nMOS 101 is the a plane, the crystal plane on the bottom surface of the groove 8 is the Si plane or the C plane. In this case, for the nMOS 101, the bottom surface has a larger interface defect than the side surface of the groove 8. The interface defect is a factor that is difficult to control due to the manufacturing conditions or the state of the substrate, and if the size of the interface defect varies, there arises a problem that the temperature dependence of the nMOS 101 deviates from the design value.

In this modification, by thickening the gate insulating film 9 that covers the bottom surface of the groove 8, the channel current flowing through the bottom surface of the groove 8 having a large interface defect can be reduced, so that the characteristics of the nMOS 101 are the side surface of the groove 8. It depends on the state of. This stabilizes the temperature dependence of the device.

When forming the gate insulating film 9 shown in FIG. 14, after forming the groove 8 (see FIG. 7), a thin silicon nitride film (insulation) that covers the side surface and the bottom surface of the groove 8 and does not completely embed the groove 8. Membrane) is formed. Next, by performing anisotropic etching, the silicon nitride film in contact with the bottom surface of the groove 8 is removed while leaving the silicon nitride film in contact with the side surface of the groove 8, and the bottom surface is exposed. Next, for example, an oxidation method is used to cover the bottom surface of the groove 8 to form a silicon oxide film (insulating film) having a relatively large first film thickness.

Next, the silicon nitride film covering the side surface of the groove 8 is removed to expose the side surface. After that, as described with reference to FIG. 8, the side surface of the groove 8 and the main surface of the semiconductor substrate SB are covered to form an insulating film 22 having a second film thickness and gate electrodes 10 and 14. As a result, the gate insulating film 9 (see FIG. 14) composed of the insulating film 22 in contact with the side surface of the groove 8 and the silicon nitride film in contact with the bottom surface of the groove 8 can be formed. The second film thickness is smaller than the first film thickness. If necessary, the silicon oxide film on the main surface of the semiconductor substrate SB, that is, above the groove 8, is removed.

<Modification 5>
FIG. 15 shows a perspective view of a silicon carbide semiconductor device which is a modification 5 of the first embodiment. The structure of this modification is different from the structure shown in FIG. 1 in that the p-type semiconductor region 20 is formed in the semiconductor substrate SB near the bottom of the groove 8, and the other structures are the structures shown in FIG. Is similar to.

As shown in FIG. 15, a p-type semiconductor region 20 is formed in the epitaxial layer 3 so as to cover the bottom surface of the groove 8. Further, a part of the p-type semiconductor region 20 also covers a part of the side surface of the groove 8 continuous with the bottom surface of the groove 8, that is, the side surface of the groove 8 near the bottom surface of the groove 8. Although the p-type semiconductor region 20 is formed near the lower end of the side surface of the groove 8, most of the side surface of the groove 8 is composed of the p-type diffusion layer 4. The p-type semiconductor region 20 is formed from the inside of the p-type diffusion layer 4 to the inside of the epitaxial layer 3 below the p-type diffusion layer 4. The p-type impurity concentration in the p-type semiconductor region 20 is higher than the p-type impurity concentration in the p-type diffusion layer 4. In other words, the p-type impurity concentration on the bottom surface of the groove 8 is higher than the p-type impurity concentration on the side surface of the groove 8.

In this modification, the p-type semiconductor region 20 is formed in the vicinity of the bottom of the groove 8 as a conductive type high-concentration impurity region different from the conductive type (n type) of the channel. In other words, a conductive p-type semiconductor region 20 different from the conductive type (n type) of the drain region 5 and the source region 6 of the nMOS 101 is formed in the vicinity of the bottom of the groove 8. As a result, in the nMOS 101, the threshold voltage at the bottom surface of the groove 8 can be made larger than the threshold voltage at the side surface of the groove 8 in the same manner as in the modification 4. Therefore, since the influence of the bottom surface of the groove 8 on the characteristics of the nMOS 101 can be reduced, the characteristics of the nMOS 101 can be stabilized.

<Modification 6>
FIG. 16 shows a perspective view of CMOS, which is a silicon carbide semiconductor device according to a modification 6 of the first embodiment. Compared to the structure shown in FIG. 15, the structure of this modification is a region between the grooves 8 adjacent to each other in the X direction, and is an epitaxial layer between the drain region 5 and the source region 6 adjacent to each other in the Y direction. The difference is that the p-type semiconductor region 24 covering the upper surface of No. 3 is formed, and the other structures are the same as those shown in FIG.

The depth of the p-type semiconductor region 24 is shallower than the depth of each of the drain region 5 and the source region 6. Therefore, the p-type semiconductor region 24 is formed near the upper end of the side surface of the groove 8, and the p-type semiconductor region 20 is formed near the lower end of the side surface of the groove 8, but most of the side surface of the groove 8 is formed. Is composed of a p-type diffusion layer 4. The concentration of p-type impurities in the p-type semiconductor region 24 is higher than the concentration of p-type impurities in the p-type diffusion layer 4. In other words, the concentration of p-type impurities on the upper surface of the epitaxial layer 3 at the location where the p-type semiconductor region 24 is formed is higher than the concentration of p-type impurities on the side surface of the groove 8 under the p-type semiconductor region 24.

Here, the p-type semiconductor region 24 is formed on the upper surface of the epitaxial layer 3 between the drain region 5 and the source region 6. As a result, in the nMOS 101, the current flowing through the upper surface (main surface) of the epitaxial layer 3 which is the Si surface can be reduced, so that the characteristics of the nMOS 101 can be further stabilized.

(Embodiment 2)
The CMOS of the second embodiment will be described with reference to FIGS. 17 and 18. FIG. 17 is a perspective view showing the silicon carbide semiconductor device of the present embodiment, and FIG. 18 is a plan view showing the silicon carbide semiconductor device of the present embodiment. The structures shown in FIGS. 17 and 18 have the same structure as that of the first embodiment, except that an element separation region having a structure similar to that of the groove 8 and the gate electrode 10 is formed on the outer periphery of the nMOS 101. doing.

As shown in FIGS. 17 and 18, in the CMOS of the present embodiment, the potential of the trench gate electrode (conductor portion) 21 in the outermost groove 8 among the plurality of grooves 8 is set to the p-type diffusion layer 4. It is characterized by being electrically connected. That is, an annular groove 8 is formed so as to surround the plurality of grooves 8 arranged in the X direction, the gate electrode 10 inside them, and the drain region 5 and the source region 6 in a plan view, and the annular groove 8 is formed. Inside, a trench gate electrode 21 is formed via a gate insulating film 9. The trench gate electrode 21 is a conductor portion formed in the process of forming the gate electrode 10, and the material of the trench gate electrode 21 is the same as that of the gate electrode 10.

The trench gate electrode 21 is electrically connected to the p-type contact layer 7 and the p-type diffusion layer 4 via the contact plug 15 and the electrode 106. That is, the trench gate electrode 21 in the outermost groove 8 among the plurality of grooves 8 arranged in the X direction has a gate in the groove 8 other than the outermost groove 8 among the plurality of grooves 8 arranged in the X direction. A potential different from that of the electrode 10 is applied. Here, among the plurality of grooves 8 arranged in the X direction, the p-type contact layer 7 is formed on a part of the upper surface of the p-type diffusion layer 4 between the most extreme groove 8 and the groove 8 adjacent to the groove 8. Is formed. The p-type contact layer 7 has a role of reducing the connection resistance between the p-type diffusion layer 4 and the contact plug 15, and a role of extracting a hole current.

With the above-described configuration, in the present embodiment, the CMOS latch-up operation can be suppressed without adding a manufacturing process.

Here, the latch-up operation and its countermeasures will be described. Bipolar transistors are parasitic on CMOS whose elements are not separated by an insulating film. For example, an npn transistor structure exists with a source region 6 as an emitter, a p-type diffusion layer 4 as a base, and an epitaxial layer 3 as a collector. Similarly, the pnp transistor is also parasitic, and when the product of the current amplification factors of these two transistors exceeds 1, latch-up occurs and a large current flows.

The false ignition of the parasitic npn transistor may start from the current flowing through the resistor of the p-type diffusion layer 4 sandwiched between the source region 6 and the epitaxial layer 3, and the voltage drop generated there causes the built-in voltage. If it exceeds, the parasitic element (parasitic npn transistor) is turned on, and the parasitic element becomes uncontrollable. In particular, in the semiconductor substrate SB using SiC, the sheet resistance of the p-type diffusion layer 4 is 100 to 300 kΩ / □, which is relatively high. Therefore, it is required to suppress the latch-up operation by reducing the current flowing through the p-type diffusion layer 4.

As shown in FIG. 17, when the trench gate electrode 21 electrically connected to the p-type diffusion layer 4 is formed in the annular groove 8 that surrounds the plurality of grooves 8 in a plan view, the p-type diffusion is formed from the epitaxial layer 3. The lateral current flowing through the layer 4 becomes difficult to flow. As a result, the current flowing through the p-type diffusion layer 4 is reduced, so that the occurrence of latch-up can be prevented. Further, by setting the trench gate electrode 21 in the outermost groove 8 to have the same potential as the p-type diffusion layer 4, the outermost nMOS 101 among the plurality of nMOS 101 is always in the off state. As a result, the electron current flowing through the epitaxial layer 3 can be reduced, so that it is possible to prevent the parasitic bipolar transistor from being turned on.

Further, a p-type contact layer 7 for extracting a hole current is provided between the groove 8 located on the outermost side in the X direction and the groove 8 located on the second outermost side, thereby latching up. The operation is prevented. The p-type contact layer 7 is formed not only on a part of the upper surface of the p-type diffusion layer 4 adjacent to the outermost groove 8 but also on all the upper surfaces of the p-type diffusion layer 4 adjacent to the outermost groove 8. You may. That is, an annular p-type contact layer 7 may be formed along the outermost groove 8 so as to surround all the grooves 8 located inside the outermost groove 8 in a plan view. This makes it easy to make the entire p-type diffusion layer 4 have the same potential as the trench gate electrode 21, so that it is possible to prevent the parasitic bipolar transistor from being turned on more stably.

(Embodiment 3)
FIG. 19 shows a perspective view of CMOS, which is the silicon carbide semiconductor device of the third embodiment. The structure of the present embodiment is different from the structure shown in FIG. 1 in that the silicon nitride film 16 covering the side surface and the bottom surface of the groove 8 is formed, and the other structures are the same as the structure shown in FIG. is there. That is, the nitriding treatment is performed only at the interface between the gate insulating film 9 of the nMOS 101 and the p-type diffusion layer 4, whereby the silicon nitride film 16 is formed.

Such a silicon nitride film 16 is formed in an atmosphere of a mixed gas of _{N 2} (nitrogen) and O ₂ (oxygen) after the process of forming the gate insulating film 9 (see FIG. 8) and before the process of forming the gate electrode 10. It can be formed by subjecting the semiconductor substrate SB to, for example, heat treatment at 1200 to 1300 ° C. The heat treatment is performed in a state where the surface of the groove 8 is exposed and a hard mask (insulating film) covering the main surface of the semiconductor substrate SB is formed, whereby the main surface of the semiconductor substrate SB is nitrided in the pMOS region 1A. Prevent it. After the nitriding treatment, the hard mask is removed. Further, in this modification, after the gate electrode 10 is formed, the gate electrode 14 is formed by a conductive film different from the conductive film constituting the gate electrode 10.

In the nMOS 101, by nitriding the surface of the channel region in contact with the gate insulating film 9, it is possible to obtain the effect of reducing the number of defects on the surface, that is, defects that obstruct the flow of electrons. However, if the surface of the channel region of the pMOS 102 is nitrided, the mobility of the pMOS 102 may decrease.

Therefore, here, the surface of the channel region in contact with the gate insulating film (not shown) of the pMOS 102 is not nitrided, but the surface of the channel region in contact with the gate insulating film 9 of the nMOS 101 is nitrided. Therefore, the mobility of the nMOS 101 can be improved without lowering the mobility of the pMOS 102. Therefore, the performance of CMOS can be further improved.

(Embodiment 4)
FIG. 20 shows a perspective view of CMOS, which is the silicon carbide semiconductor device of the fourth embodiment.

The overall structure of the CMOS of the present embodiment is the same as the structure shown in FIG. 1, but in the present embodiment, the work function of the gate electrode 17 in the groove 8 of the nMOS 101 is the work function of the gate electrode 14 of the pMOS 102. Smaller.

In a silicon carbide semiconductor device, since the band gap of SiC used for the semiconductor substrate is large, the threshold voltage of nMOS tends to be high, and the threshold voltage of pMOS tends to be low. Here, the gate electrode 17 is made of polysilicon, which is an n-type semiconductor into which P (phosphorus), which is an n-type impurity, is introduced, or Al (aluminum) or W (tungsten). As a result, the work function of the gate electrode 17 is lower than that in the case where the gate electrode 17 is made of a p-type semiconductor film. Therefore, the threshold voltage of nMOS 101 can be lowered.

Further, the gate electrode 18 is made of p-type semiconductor polysilicon in which B (boron), which is a p-type impurity, is introduced. As a result, the work function of the gate electrode 18 is higher than that when the gate electrode 18 is composed of an n-type semiconductor film, an Al (aluminum) film, or a W (tungsten) film. Specifically, the threshold voltage of the gate electrode 18 is a negative value, and by forming the gate electrode 18 with a p-type semiconductor film, the threshold voltage of the gate electrode 18 approaches 0V. Therefore, the threshold voltage of the pMOS 102 can be increased.

When the gate electrodes 17 and 18 are formed of different conductive semiconductor films, the gate electrodes 10 and 14 are each of a separate conductive type in the process of forming the gate electrodes 10 and 14 described with reference to FIG. Impurities may be introduced.

In the present embodiment, the difference between the threshold voltages of nMOS 101 and pMOS 102 can be reduced by lowering the threshold voltage of nMOS 101 and increasing the threshold voltage of pMOS 102. That is, since the threshold voltages of nMOS 101 and pMOS 102 can be optimized, the performance of the silicon carbide semiconductor device of the present embodiment can be further improved.

Although the invention made by the present inventors has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. is there.

For example, in the first to fourth embodiments, the nMOS is formed by a trench structure and the pMOS is formed by a planar structure. However, depending on the plane orientation of the wafer to be used, the nMOS is formed as a planar type MOS and the pMOS is formed by a trench gate type. It may be formed as MOS. In that case, the shapes of the nMOS and the pMOS described in the first to fourth embodiments are exchanged. That is, for example, when a silicon carbide semiconductor device is formed using a wafer in which the crystal plane of the main surface is the a-plane, a planar nMOS having a channel on the main surface is formed, and a groove formed on the main surface is formed. A pMOS having a channel on the Si plane or the C plane which is a side surface of the above is formed.

Further, in the first to fourth embodiments, the case where the conductive type of the semiconductor substrate is n-type has been described, but the conductive type may be p-type. In that case, although not described in this embodiment, an n-type well is formed on the main surface of the semiconductor substrate in the region where the pMOS channel is formed.

Further, the layouts shown in FIGS. 3, 11 and 12 are examples. For example, the layouts of FIGS. 3 and 11 may be combined with each other, or the layouts of FIGS. 11 and 12 may be combined with each other. ..

1 SiC substrate 3 epitaxial layer 8 grooves 10, 14, 17, 18 Gate electrodes 101, 107 nMOS
102 pMOS
SB semiconductor substrate

Claims (14)

A semiconductor substrate containing silicon carbide and having a hexagonal crystal structure,
Complementary field-effect transistors composed of n-type field-effect transistors and p-type field-effect transistors formed in the vicinity of the main surface of the semiconductor substrate, respectively.
Have,
The n-type field effect transistor includes a first channel region formed on the (11-20) plane or the (0-110) plane of the crystal planes of the semiconductor substrate.
The p-type field effect transistor, of the crystal face of the semiconductor substrate, e Bei a second channel region formed in (000-1) plane or the (0001) plane,
The n-type field effect transistor is formed on the side surface of the groove and the first gate electrode formed in the groove formed on the main surface of the semiconductor substrate via the first gate insulating film, and is separated from each other. It is composed of a first source region and a first drain region.
The p-type field effect transistor is formed on the main surface of the semiconductor substrate and the second gate electrode formed on the main surface of the semiconductor substrate via the second gate insulating film, and is separated from each other. It is composed of a second source region and a second drain region.
A silicon carbide semiconductor device in which the first drain region and the second drain region are electrically connected to each other, and the first gate electrode and the second gate electrode are electrically connected to each other. .. In the silicon carbide semiconductor device according to claim 1,
The n-type field effect transistor is a silicon carbide semiconductor device including the first channel region formed on the (11-20) plane of the crystal planes of the semiconductor substrate. In the silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device in which the first film thickness of the first gate insulating film in contact with the bottom surface of the groove is larger than the second film thickness of the first gate insulating film in contact with the side surface of the groove. In the silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device in which the concentration of p-type impurities on the bottom surface of the groove is higher than the concentration of p-type impurities on the side surface of the groove. In the silicon carbide semiconductor device according to claim 1,
Two grooves are formed side by side in the first direction along the main surface of the semiconductor substrate.
The first source region and the first drain region arranged side by side in the second direction orthogonal to the first direction in the direction along the main surface of the semiconductor substrate between the two grooves. A silicon carbide semiconductor device in which the p-type impurity concentration on the main surface of the semiconductor substrate in between is higher than the p-type impurity concentration on the side surface of the groove. In the silicon carbide semiconductor device according to claim 1,
A plurality of the grooves are formed side by side in the first direction along the main surface of the semiconductor substrate.
The plurality of grooves are formed on the upper surface of the p-type semiconductor layer formed on the main surface of the semiconductor substrate.
A silicon carbide semiconductor device in which the first gate electrode formed in the outermost groove in the first direction is electrically connected to the p-type semiconductor layer. In the silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device further comprising a silicon nitride film formed between the groove and the first gate insulating film. In the silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device in which the work function of the first gate electrode is lower than the work function of the second gate electrode. A semiconductor substrate containing silicon carbide and having a hexagonal crystal structure,
Complementary field-effect transistors composed of n-type field-effect transistors and p-type field-effect transistors formed in the vicinity of the main surface of the semiconductor substrate, respectively.
Have,
The n-type field effect transistor includes a first channel region formed on the (11-20) plane or the (0-110) plane of the crystal planes of the semiconductor substrate.
The p-type field effect transistor includes a second channel region formed on the (000-1) plane or the (0001) plane of the crystal planes of the semiconductor substrate.
The n-type field effect transistor has the first channel region on the main surface of the semiconductor substrate, and the p-type field effect transistor has the first channel on the side surface of a groove formed on the main surface of the semiconductor substrate. A silicon carbide semiconductor device having a 2-channel region. (A) A step of preparing a semiconductor substrate containing silicon carbide and having a hexagonal crystal structure.
(B) A step of forming a first source region and a first drain region on the main surface of the semiconductor substrate so as to be separated from each other and arranged in the first direction.
(C) A step of forming a groove on the main surface of the first region of the semiconductor substrate so that the first source region and the first drain region are exposed on one side surface.
(D) A step of forming a second source region and a second drain region on the main surface of the second region of the semiconductor substrate so as to be separated from each other.
(E) A first gate electrode is formed in the groove via a first gate insulating film, and a second gate electrode is formed on the main surface of the semiconductor substrate in the second region via a second gate insulating film. The process of forming,
Have,
The first gate electrode, the first source region, and the first drain region form an n-type field effect transistor.
The second gate electrode, the second source region, and the second drain region form a p-type field effect transistor.
The main surface of the semiconductor substrate is the (000-1) plane or the (0001) plane of the crystal planes of the semiconductor substrate, and the side surface of the groove is (11) of the crystal planes of the semiconductor substrate. A method for manufacturing a silicon carbide semiconductor device, which is a -20) plane or a (0-110) plane. In the method for manufacturing a silicon carbide semiconductor device according to claim 10.
A method for manufacturing a silicon carbide semiconductor device, wherein the side surface of the groove is the (11-20) plane of the crystal planes of the semiconductor substrate. In the method for manufacturing a silicon carbide semiconductor device according to claim 10.
The step (e) is
(E1) A step of forming a first insulating film that covers the side surface of the groove and exposes the bottom surface of the groove.
(E2) After the step (e1), a step of covering the bottom surface of the groove to form a second insulating film having a first film thickness.
(E3) A step of exposing the side surface of the groove by removing the first insulating film after the step (e2).
(E4) After the step (e3), the side surface of the groove and the main surface of the semiconductor substrate are covered to form a third insulating film having a second film thickness smaller than the first film thickness. The first gate insulating film including the first insulating film and the second insulating film covering the side surface of the groove, and the second gate including the third insulating film covering the main surface of the semiconductor substrate. The process of forming an insulating film,
(E5) A step of forming the first gate electrode in the groove and the second gate electrode on the second gate insulating film.
A method for manufacturing a silicon carbide semiconductor device, including. In the method for manufacturing a silicon carbide semiconductor device according to claim 10.
(C1) After the step (c) and before the step (e), by introducing a p-type impurity into the bottom surface of the groove, the p-type impurity concentration on the bottom surface of the groove can be adjusted to the side surface of the groove. A method for manufacturing a silicon carbide semiconductor device, further comprising a step of increasing the concentration of p-type impurities in the above. In the method for manufacturing a silicon carbide semiconductor device according to claim 10.
The step (e) is
(E6) A step of forming the first gate insulating film and the second gate insulating film,
(E7) After the step (e6), a step of forming a hard mask that covers the main surface of the semiconductor substrate and exposes the surface of the groove.
(E8) After the step (e7), the interface between the first gate insulating film and the surface of the groove is nitrided to form a silicon nitride film between the first gate insulating film and the surface of the groove. The process of forming,
(E9) After the step (e8), the step of removing the hard mask and subsequently forming the first gate electrode in the groove and the second gate electrode on the second gate insulating film.
A method for manufacturing a silicon carbide semiconductor device, including.

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