TW201906084A - Silicon carbide semiconductor device and manufacturing method thereof for improving performance of both nMOS and pMOS serving as a CMOS of a silicon carbide semiconductor device - Google Patents

Abstract

The subject of the present invention is to improve performance of both nMOS and pMOS that serve as a CMOS of a silicon carbide semiconductor device. According to the silicon carbide semiconductor device of the present invention, in a crystal plane of a semiconductor substrate SB having a hexagonal crystal structure containing silicon carbide, a channel is provided on a Si plane or a C plane where the mobility of holes is relatively high, so as to form the pMOS 102 having holes as majority carriers . Furthermore, on the crystal plane of the semiconductor substrate SB, a channel is provided on the a-plane or m-plane having relatively high electron mobility, so as to form the nMOS 101 having electrons as majority carriers.

Description

Tantalum carbide semiconductor device and method of manufacturing same

The present invention relates to a tantalum carbide semiconductor device and a method of fabricating the same, and more particularly to a CMOS (Complementary Metal-Oxide-Semiconductor Field Effect).

At present, most of the manufactured industrial products are made of a semiconductor element using germanium (hereinafter referred to as Si) as a material, and the performance is greatly improved with the development of Si. On the other hand, a general-purpose Si device cannot be applied to a product used in a high-temperature environment, and if a cooling device is provided as a countermeasure, it is difficult to reduce the size, weight, and cost of the product. Moreover, even if the sensor with high heat resistance outputs a small signal, since the information processing device that cannot withstand high temperature is placed away from the machine where the sensor is installed, the signal-to-noise ratio cannot be sufficiently ensured. problem. On the other hand, as a device that can operate at a high temperature, there is a semiconductor device having a substrate containing niobium carbide (hereinafter sometimes referred to as SiC). As long as it is a silicon carbide semiconductor device using SiC, it can be used as the information processing device or the like in a high temperature environment. SiC has a high-temperature type (α type) having a hexagonal crystal structure and a low temperature type (β type) having a cubic crystal structure. Α-type SiC has a wider band gap than β-type SiC, and is suitable as 4H-SiC of α-type SiC in a high temperature environment. On the other hand, the channel mobility of 4H-SiC is known to be relatively low. For example, in order to improve the mobility of 4H-SiC, a defect reduction layer is provided by introducing C (carbon) into a region where a channel is formed, for example, in the patent document 1 (JP-A-2014-143248). . In addition, in order to stabilize the threshold voltage, a BN pair structure formed by diffusion of N (nitrogen) is formed between the channel region and the gate insulating film made of an oxide film or the like. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2014-143248

[Problems to be Solved by the Invention] However, the MOSFET described in Patent Document 1 does not consider a p-type MOSFET (hereinafter referred to as pMOS), and may not necessarily improve the combined n-type MOSFET (hereinafter referred to as nMOS) and pMOS. The problem of the performance of CMOS. That is, the channel mobility is also changed according to the interface state of SiC and the gate insulating film (the presence or absence of nitriding treatment, etc.), but the interface processing for increasing the mobility of electrons does not necessarily contribute to the improvement of the mobility of the hole, and the key is The mobility of carriers of both nMOS and pMOS is increased. The above and other objects and novel features of the present invention will be apparent from [Technical means for solving the problem] Hereinafter, an outline of a representative embodiment of the embodiment disclosed in the present application will be briefly described. A silicon carbide semiconductor device according to a representative embodiment of the present invention includes a semiconductor substrate including tantalum carbide and a hexagonal crystal structure, and nNOS having an a-plane or an m-plane of the semiconductor substrate as a channel region; The pMOS has a Si surface or a C surface of the above semiconductor substrate as a channel region. [Effect of the Invention] According to a representative embodiment of the present invention, the performance of the tantalum carbide semiconductor device can be improved. In particular, the channel mobility of each of nMOS and pMOS formed on the tantalum carbide semiconductor substrate can be improved.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the drawings, the same reference numerals will be given to the components having the same functions, and the description thereof will not be repeated. Further, in the embodiments, the description of the same or the same portions will not be repeated in principle unless otherwise required. Further, in the drawings for explaining the embodiments, in order to facilitate understanding of the configuration, hatching may be employed even in a plan view, a perspective view, or the like. Again, the symbol " ^- "and" ⁺ "" indicates the relative concentration of the impurity of the n-type or p-type conductivity type. For example, in the case of an n-type impurity, the impurity concentration is in accordance with "n". ^- ",""n","n ⁺ The order becomes higher. (Embodiment 1) <Structure of Tantalum Carbide Semiconductor Device> The structure of the tantalum carbide semiconductor device of the present embodiment will be described below with reference to Figs. 1 to 3 . 1 is a perspective view showing a tantalum carbide semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a complementary field effect transistor of the tantalum carbide semiconductor device of the present embodiment, which is shown in FIG. A plan view showing a complementary field effect transistor as the tantalum carbide semiconductor device of the present embodiment. In FIG. 1, the insulating film and the wiring including the gate insulating film and the interlayer insulating film on the SiC substrate are omitted. In Fig. 1, a pMOS region 1A is shown on the left side of the figure, and an nMOS region 1B is shown on the right side of the figure. The pMOS region 1A and the nMOS region 1B are regions which are arranged in the direction along the main surface of the semiconductor substrate. In FIG. 3, the p-type diffusion layer 4 is hatched. As shown in FIG. 1, the tantalum carbide semiconductor device of the present embodiment includes a semiconductor substrate SB including a SiC substrate 1 composed of a hexagonal crystal structure and an epitaxial layer formed on the SiC substrate 1 ( The semiconductor layer 3 is formed with nMOS 101 and pMOS 102 in the vicinity of the upper surface of the semiconductor substrate SB. The nMOS 101 and the pMOS 102 constitute a CMOS which is a complementary field effect transistor having a MOS structure. It is considered that the complementary field effect transistor of the present embodiment is mounted on a semiconductor device or an electric power module or an inverter together with an IGBT (Insulated Gate Bipolar Transistor) or the like. As shown in FIG. 2, the CMOS has a structure in which the nMOS 101 and the pMOS 102 are complementarily connected, and the nMOS 101 and the pMOS 102 are connected in series between the electrode 105 to which the Vdd potential is applied and the electrode 106 to which the Vss potential (ground potential) is applied. That is, the drain electrodes of the nMOS 101 and the pMOS 102 are connected to each other. The drain electrodes are connected to an output terminal (output electrode) 104, and the gate electrodes of each of the nMOS 101 and the pMOS 102 are connected to one input terminal 103. The source electrode of the nMOS 101 is connected to the electrode 106, and the source electrode of the pMOS 102 is connected to the electrode 105. The input terminal 103 and the output terminal 104 and the CMOS formed between the terminals constitute a NOT circuit (NOT circuit). As shown in FIG. 1, the SiC substrate 1 has a (000-1) plane which is a Si surface in a hexagonal crystal plane as a main surface, and has a C surface, that is, a (0001) plane, which is a back surface of the opposite side of the main surface. N-type semiconductor substrate. Similarly, the epitaxial layer 3 containing SiC and composed of a hexagonal crystal structure has a Si surface in the plane of the hexagonal system as a main surface, and the lower surface of the opposite side of the main surface of the epitaxial layer 3 and SiC The main faces of the substrate 1 are in contact. Here, various surfaces of the hexagonal crystal structure will be described with reference to FIGS. 21 to 24 . 21 to 24 are perspective views schematically showing a lattice model of a hexagonal system. In the lattice model shown in Figs. 21 to 24, a part of the crystal faces are hatched. Further, the C (carbon) atom is represented by a black circle, and the Si (germanium) atom is represented by a white circle. In Figs. 21 to 24, the horizontal axes show the axes of a1, a2, and a3 located in the same horizontal plane, and the vertical axis shows the direction perpendicular to the axes of a1, a2, and a3. axis. Each of the axes of a1, a2, a3, and c extends from the same reference point. The angles formed by the axes of a1, a2, and a3 are 120 degrees in plan view. The face of the hexagonal crystal lattice model is represented by four indices (face indices) of (a1, a2, a3, c). The "2" in the following surface index refers to 1/2, and "-" refers to the opposite direction of the axis. For example, in the (1-102) plane, a1=1, a2=-1, a3=0, and c=2. A compound semiconductor of SiC-based Si (cerium) and C (carbon) is composed of a covalent bond of Group IV. As shown in FIG. 21, the crystal structure is a basic tetrahedron having Si atoms or C atoms as vertices as a basic element, and is laminated in the c-axis direction. In 4H-SiC, the surface on which the Si (矽) is exposed on the outermost surface is referred to as a (000-1) plane or a Si plane, and the surface on which C (carbon) is exposed is referred to as a (0001) plane or a C plane. FIG. 21 shows a (0001) plane (C plane) 201 and a (000-1) plane (Si plane) 202. The C face 201 and the Si face 202 correspond to the upper or lower surface of the hexagonal crystal shown in Fig. 21 . The (0-110) plane perpendicular to the C-plane 201 (see FIG. 21) and corresponding to the side surface of the hexagonal crystal is referred to as an m-plane, and is similar to the C-plane 201 (see FIG. 21) and is equivalent to a hexagonal The (11-20) face of the side of the crystal is called the a face. In Fig. 22, (11-20) plane (a plane) 203 and (0-110) plane (m plane) 204 are shown. Further, there are an S-surface 205 (see FIG. 23) which is an (10-11) plane in the oblique direction with respect to the C-plane 201 (see FIG. 21), or an oblique direction (1-102) with respect to the C-plane 201 (refer to FIG. 21). The surface is the r surface 206 (see Fig. 24). In a tantalum carbide semiconductor device using a SiC substrate, a wafer having a Si surface or a C surface as a main surface is more likely to have a larger diameter than a wafer having a crystal plane other than the Si surface and the C surface. Therefore, in the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed on the SiC substrate, it is conceivable to use the Si surface or the C surface as the main surface or the a surface or the m plane perpendicular to the main surface of the substrate. In the tantalum carbide semiconductor device of the present embodiment, a semiconductor substrate SB (see FIG. 1) including 4H-SiC described with reference to FIGS. 21 to 24 is used. 21 shows a hexagonal crystal whose upper surface is a C surface 201 and whose lower surface is a Si surface 202. However, the upper surface of the semiconductor substrate SB (see FIG. 1) composed of hexagonal crystals is a Si surface, and the lower surface is a C surface. . As shown in FIG. 1, the tantalum carbide semiconductor device of the present embodiment includes a semiconductor substrate SB including an n-type SiC substrate 1 and an n-type epitaxial layer 3. The semiconductor substrate SB has a hexagonal crystal lattice structure shown in FIGS. 21 to 24 . The SiC substrate 1 and the epitaxial layer 3 have a structure in which, for example, N (nitrogen) is introduced as an n-type impurity into a semiconductor layer containing SiC. The n-type impurity concentration of the SiC substrate 1 is higher than the n-type impurity concentration of the epitaxial layer 3. The back surface of the semiconductor substrate SB, that is, the back surface of the SiC substrate 1 is covered by the back surface electrode 2. The back surface electrode 2 that is in contact with the back surface of the semiconductor substrate SB is made of, for example, a conductor containing Au (gold), for example, an electrode to which a Vdd potential is applied. In the nMOS region 1B, a p-type diffusion layer (p-type semiconductor layer) 4 is formed on a portion of the main surface of the semiconductor substrate SB, that is, a portion of the upper surface of the epitaxial layer 3. The lower surface of the p-type diffusion layer 4 does not reach the interface between the SiC substrate 1 and the epitaxial layer 3, and reaches the depth of the epitaxial layer 3 midway. A plurality of grooves 8 extending in the Y direction are formed side by side in the X direction on the upper surface of the p-type diffusion layer 4. The depth of the groove 8 is shallower than the depth of the p-type diffusion layer 4. Further, only two grooves 8 are shown in Fig. 1, but more grooves 8 may be formed in parallel in the X direction. The X direction is along the direction of the main surface of the semiconductor substrate SB. The Y direction is along the direction of the main surface of the semiconductor substrate SB and is orthogonal to the X direction. The side surface of the groove 8 is a surface perpendicular to the Si surface which is the main surface of the semiconductor substrate SB, and is an a surface of the semiconductor substrate SB. That is, the crystal face of the side surface of the groove 8 extending in the Y direction includes the a face of the epitaxial layer 3 of SiC. In other words, the Y direction is along the a-plane and the m-plane of the semiconductor substrate SB composed of the hexagonal crystal whose main surface is the Si surface. As shown in FIGS. 1 and 3, the gate electrode 10 is completely embedded in the trench 8 via the gate insulating film 9. The gate insulating film 9 is made of, for example, a hafnium oxide film and covers the side surface and the bottom surface of the trench 8. The gate electrode 10 includes, for example, polycrystalline germanium, Al (aluminum), or W (tungsten). A drain region 5, a source region 6, and a p-type contact layer 7 are sequentially formed on the upper surface of the p-type diffusion layer 4 between the adjacent trenches 8 in the X direction. Each of the drain region 5 and the source region 6 is an n-type semiconductor region, and is formed by introducing an n-type impurity (for example, N (nitrogen)) to the main surface of the semiconductor substrate SB. The p-type diffusion layer 4 and the p-type contact layer 7 are p-type semiconductor regions and are formed by introducing a p-type impurity (for example, Al (aluminum)) onto the main surface of the semiconductor substrate SB. The n-type impurity concentration of each of the drain region 5 and the source region 6 is higher than the n-type impurity concentration of the epitaxial layer 3. Further, the p-type impurity concentration of the p-type diffusion layer 4 is higher than the p-type impurity concentration of the p-type contact layer 7. The p-type contact layer 7 has a function of fixing the potential of the p-type diffusion layer 4 and maintaining a potential difference between the gate electrode 10 and the p-type diffusion layer 4. The drain region 5 and the source region 6 are spaced apart from each other in the Y direction, and a p-type diffusion layer 4 is formed on the main surface of the semiconductor substrate SB in the region between the drain region 5 and the source region 6. The ends of the drain region 5, the source region 6, and the p-type contact layer 7 in the X direction are terminated by the sides of the grooves 8 adjacent to each other. That is, both ends of the drain region 5, the source region 6, and the p-type contact layer 7 in the X direction are in contact with the side faces of the gate insulating film 9. In other words, the drain region 5, the source region 6, and the p-type contact layer 7 are formed on the side faces of the trench 8, respectively. Similarly, both ends of the p-type diffusion layer 4 in the Y direction in the X direction are terminated by the sides of the adjacent grooves 8 and with the gate insulating film 9 The sides are connected. In the Y direction, the source region 6 and the p-type contact layer 7 are in contact with each other. As shown in FIG. 3, the p-type contact layer 7 is sandwiched by the two source regions 6 in the Y direction. Here, the drain region 5, the p-type diffusion layer 4, the source region 6, the p-type contact layer 7, the source region 6, the p-type diffusion layer 4, and the drain region 5 are sequentially formed in the Y direction. The nMOS 101 is composed of a gate electrode 10, a drain region 5, and a source region 6 in the trench 8. That is, the nMOS 101 is a so-called trench gate type MOSFET. Between the mutually adjacent drain regions 5 and the source regions 6, the side surface of the p-type diffusion layer 4 which is adjacent to the gate electrode 10 via the gate insulating film 9 is formed in the region where the nMOS 101 operates to form a channel ( Channel area). That is, the nMOS 101 is a field effect transistor having a channel on the side surface of the semiconductor substrate SB, that is, the side surface of the groove 8 instead of the main surface (Si surface) of the semiconductor substrate SB. The side surface of the groove 8 extending in the Y direction is an a surface perpendicular to the main surface of the semiconductor substrate SB. Further, between the drain region 5 and the source region 6, the current during the operation of the nMOS 101 mainly flows on the side surface of the trench 8 extending in the Y direction, that is, the side surface of the p-type diffusion layer 4, even if 汲In the p-type diffusion layer 4 between the pole region 5 and the source region 6, the current flowing in the region between the adjacent grooves 8 in the X direction and away from the side surface of the groove 8 is also very small. Further, a plurality of contact plugs (conductive connecting portions) 15 are formed on the semiconductor substrate SB. Each of the contact plugs 15 is electrically connected to an electrode (wiring, terminal) formed on the contact plug 15 or the like. The input terminal 103, the output electrode (output terminal) 104, and the electrodes 105 and 106 are all formed on the contact plug 15. The contact plug 15 disposed across the upper surface of each of the source region 6 and the p-type contact layer 7 and electrically connected to the source region 6 and the p-type contact layer 7 is connected to the electrode 106 to which the Vss potential is applied. . A contact plug 15 connected to the upper surface of the drain region 5 is electrically connected to the output electrode 104. The contact plug 15 connected to the upper surface of the gate electrode 10 is electrically connected to the input terminal (gate wiring) 103. As shown in FIG. 1 and FIG. 3, in the pMOS region 1A, one surface of the main surface of the semiconductor substrate SB, that is, the upper surface of the epitaxial layer 3, which is adjacent to each other in the Y direction and adjacent to each other in the X direction is formed. The drain region 11 and the source region 12. The drain region 11 and the source region 12 are spaced apart from each other in the X direction, and an n-type epitaxial layer is formed on the main surface of the semiconductor substrate SB between the drain region 11 and the source region 12 adjacent in the X direction. Layer 3. The drain region 11 and the source region 12 are p-type semiconductor regions formed by introducing a p-type impurity (for example, Al (aluminum)) onto the upper surface of the epitaxial layer 3, respectively. A gate electrode 14 is formed via a gate insulating film (not shown) directly above the upper surface of the epitaxial layer 3 between the drain region 11 and the source region 12 adjacent in the X direction. The gate electrode 14 contains, for example, polysilicon, Al (aluminum) or W (tungsten). The gate insulating film (not shown) is made of, for example, a hafnium oxide film. The gate electrode 14 extends in the Y direction. Further, although the gate electrode 14 is not illustrated in FIG. 3, the gate electrode 14 is formed directly under the portion of the input terminal (gate wiring) 103 extending in the Y direction. An n-type contact layer 13 is formed on the main surface of the semiconductor substrate SB so as to be in contact with the side surface of the source region 12 and not facing the side surface of the drain region 11. The gate electrode 14 and the n-type contact layer 13 do not overlap in plan view. The n-type contact layer 13 is an n-type semiconductor region formed by introducing an n-type impurity (for example, N (nitrogen)) to the upper surface of the epitaxial layer 3, and the n-type impurity concentration of the n-type contact layer 13 is higher than that of the epitaxial layer 3. N-type impurity concentration. The drain regions 5, 11, the source regions 6, 12, and the n-type contact layer 13 have the same depth, and do not reach the interface between the epitaxial layer 3 and the SiC substrate 1. The n-type contact layer 13 has a function of fixing the potential of the epitaxial layer 3 and maintaining the potential difference between the gate electrode 14 and the epitaxial layer 3 constant. The drain region 11, the source region 12, and the gate electrode 14 formed in the pMOS region 1A constitute the pMOS 102. That is, the pMOS 102 is a so-called planar MOSFET. Between the mutually adjacent drain regions 11 and the source regions 12, a gate insulating film (not shown) is interposed and a surface of the epitaxial layer 3 adjacent to the gate electrode 14 is formed by the action of the pMOS 102. The area of the channel (channel area). In other words, the pMOS 102 is a field effect transistor having a channel on the Si surface which is a crystal plane of the main surface of the semiconductor substrate SB. As shown in FIG. 3, a contact plug 15 electrically connected to the source region 12 and the n-type contact layer 13, respectively, is connected to the electrode 105 to which the Vdd potential is applied. A contact plug 15 connected to the upper surface of the drain region 11 is electrically connected to the output electrode 104. A contact plug 15 connected to the upper surface of the gate electrode 10 is electrically connected to the input terminal (gate wiring) 103. The output electrode 104 electrically connected to the drain region 5 of the nMOS 101 and the drain region 11 of the pMOS 102 has a comb-like layout, and the electrode 106 electrically connected to the source region 6 of the nMOS 101 and the p-type contact layer 7 has a comb. Toothed layout. That is, the output electrode 104 and the electrode 106 each have a pattern extending in the Y direction and a plurality of patterns of comb-tooth shapes connected to the pattern and extending in the X direction. Further, only one of a plurality of patterns constituting the comb teeth of the electrode 106 is shown in the drawing. The pattern of the comb-tooth shape constituting the output electrode 104 and the pattern of the comb-tooth shape constituting the electrode 106 are arranged in a staggered manner. The main feature of the present embodiment is that the planar pMOS 102 and the trench gate type nMOS 101 constitute a CMOS, and the crystal plane of the pMOS 102 forming the channel is a Si surface, and the crystal surface of the nMOS 101 forming the channel is an a surface. <Manufacturing Method of Tantalum Nitride Semiconductor Device> Hereinafter, a method of manufacturing the niobium carbide semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 10 . 4 to 10 are perspective views of the manufacturing process of the CMOS of the niobium carbide semiconductor device of the first embodiment. In FIGS. 4 to 10, the pMOS region 1A and the nMOS region 1B are shown in the same manner as in FIG. Here, a description will be given of a SiC wafer having a Si surface as a main surface. However, it is needless to say that the structure of the MOSFET can be appropriately changed depending on the crystal plane. Here, the manufacturing steps of the gate insulating film, the interlayer insulating film, the contact plug, the electrode, and the like, which are not shown in FIG. 1, will be described. First, as shown in FIG. 4, the back surface having the opposite sides of the main surface and the main surface is prepared. ⁺ Type SiC substrate 1. The SiC substrate 1 is a semiconductor substrate containing SiC (cerium carbide) and having a hexagonal crystal structure. The crystal face of the main surface of the SiC substrate 1 is a Si surface. Then, the epitaxial layer 3 is formed on the main surface of the SiC substrate 1 by an epitaxial growth method. The epitaxial layer 3 has a hexagonal crystal structure, and the crystal face of the main surface of the epitaxial layer 3 is a Si surface. Here, the epitaxial layer 3 is grown by introducing an n-type impurity (for example, N (nitrogen)) toward the epitaxial layer 3, whereby the epitaxial layer 3 can be formed with a desired impurity concentration. Next, as shown in FIG. 5, a p-type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 3 by photolithography and ion implantation. Thereby, the upper surface of the epitaxial layer 3 is formed as p ⁺ The p-type contact layer 7, the drain region 11, the source region 12, and the element isolation layer (not shown) of the semiconductor region. The p-type contact layer 7 reaches the depth from the upper surface of the epitaxial layer 3 to the middle of the epitaxial layer 3, and is formed in the nMOS region 1B. The drain region 11 and the source region 12 reach the depth from the upper surface of the epitaxial layer 3 to the middle of the epitaxial layer 3, and are formed in the pMOS region 1A. The drain region 11 and the source region 12 are spaced apart from each other. Next, a p-type impurity such as Al (aluminum) is implanted into the upper surface of the epitaxial layer 3 by photolithography and ion implantation. Thereby, a p-type diffusion layer 4 as a p-type semiconductor region is formed on the upper surface of the epitaxial layer 3 of the nMOS region 1B. The p-type impurity layer 4 has a p-type impurity concentration lower than that of the p-type contact layer 7, and has a deeper depth than the p-type contact layer 7. However, the lower surface of the p-type diffusion layer 4 does not reach the interface between the epitaxial layer 3 and the SiC substrate 1. Here, the p-type diffusion layer 4 is formed at a position overlapping the p-type contact layer 7 and the region around it in plan view. Next, as shown in FIG. 6, an n-type impurity (for example, N (nitrogen)) is implanted into the upper surface of the epitaxial layer 3 by photolithography and ion implantation. Thereby, the surface of the epitaxial layer 3 is formed as n ⁺ The drain region 5, the source region 6, and the n-type contact layer 13 of the semiconductor region. The drain region 5 and the source region 6 are formed in the nMOS region 1B, and the n-type contact layer 13 is formed in the pMOS region 1A. The drain region 5 and the source region 6 are formed to be spaced apart from each other, and the source region 6 is formed adjacent to the p-type contact layer 7. The depth of the drain region 5 and the source region 6 is shallower than the depth of the p-type diffusion layer 4. The n-type contact layer 13 is formed at a position adjacent to the source region 12. Next, as shown in FIG. 7, a plurality of grooves 8 are formed on the main surface of the p-type diffusion layer 4 of the nMOS region 1B by photolithography and etching. The trench 8 is formed in the p-type diffusion layer 4 in a plan view, and the bottom of the trench 8 does not reach the boundary between the lower surface of the p-type diffusion layer 4 and the epitaxial layer 3. Here, two or more grooves 8 are formed so as to sandwich the drain region 5, the source region 6, and the p-type contact layer 7 arranged in the Y direction in the X direction. The drain region 5, the source region 6, and the p-type contact layer 7 are exposed in one of the side surfaces of the trench 8 extending in the Y direction. The crystal surface which is the side surface of the groove 8 and exposes the surface of the drain region 5, the source region 6, and the p-type contact layer 7, that is, the surface extending in the Y direction, is an a surface. Next, as shown in FIG. 8, on the epitaxial layer 3, for example, a relatively thin insulating film 22 and a conductive film are sequentially formed by a CVD (Chemical Vapor Deposition) method, whereby the groove is formed. Completely landfilled within 8. The insulating film 22 is made of, for example, a hafnium oxide film, and the conductive film contains, for example, polycrystalline germanium, Al (aluminum), or W (tungsten). Then, the conductive film is processed by photolithography and etching to expose the upper surface of one portion of the insulating film 22. Thereby, the gate electrodes 10, 14 including the conductive film are formed. The gate electrode 10 is formed inside each of the plurality of slots 8 of the nMOS region 1B, and the gate electrode 14 is formed in the pMOS region 1A, and the edge film 22 is isolated to form a bump between the drain region 11 and the source region 12. On the crystal layer 3. The gate electrode 10, the drain region 5, and the source region 6 constitute an nMOS 101. The gate electrode 14, the drain region 11, and the source region 12 constitute a pMOS 102. Here, the insulating film 22 which is embedded in the groove 8 and covers the side surface and the bottom surface of the gate electrode 10 constitutes the gate insulating film 9. The thickness of the gate insulating film 9 which is in contact with the side of the trench 8 and the thickness of the gate insulating film 9 which is in contact with the bottom surface of the trench 8 are equal to each other. In the case where each of the gate electrodes 10 and 14 is formed of a different material, for example, after the insulating film 22 and the gate electrode 10 are formed, a conductive film is formed on each of the insulating film 22 and the gate electrode 10, The conductive film is then processed, whereby the gate electrode 14 is formed. In the case where each of the gate electrodes 10 and 14 is formed by a semiconductor film, here, the conductivity types of both of the gate electrodes 10 and 14 are made n-type or p-type. Thereby, the manufacturing cost of the tantalum carbide semiconductor device can be reduced as compared with the case where each of the gate electrodes 10 and 14 is formed of a semiconductor film of a different conductivity type. An example of a method of introducing an impurity into the semiconductor film is a method of introducing an impurity into the semiconductor film during film formation by a CVD method, and introducing an impurity into the semiconductor film by ion implantation after the film formation of the semiconductor film. The method. As the n-type impurity introduced into the semiconductor film, for example, P (phosphorus) is used, and as the p-type impurity introduced into the semiconductor film, for example, B (boron) is used. Next, as shown in FIG. 9, an interlayer insulating film 19 is formed on each of the epitaxial layer 3, the insulating film 22, and the gate electrodes 10 and 14 by, for example, a CVD method. The interlayer insulating film 19 is composed of, for example, a hafnium oxide film. Here, the side surface and the upper surface of the gate electrode 14, the upper surface of the gate electrode 10, and the upper surface of the insulating film 22 are covered by the interlayer insulating film 19. Then, the interlayer insulating film 19 is passed through the interlayer insulating film 19 and the insulating film 22 by using a photolithography technique and an etching method to form a plurality of connection holes exposing the upper surface of the epitaxial layer 3. At the bottom of each connection hole, the source region 6 (refer to FIG. 7), 12, the drain region 5, 11, the p-type contact layer 7 (refer to FIG. 7) or the n-type contact layer 13 self-contained interlayer insulating film 19 and insulation The laminated film of the film 22 is exposed. By insulating the insulating film 22 by this step, the gate insulating film 23 composed of the insulating film 22 is formed directly under the gate electrode 14. In FIG. 9, the connection holes which are open directly above each of the gate electrodes 10 and 14 are not shown. These connection holes are formed in a region not shown. The source region 12 and the n-type contact layer 13 are exposed at the bottom of the same connection hole. Further, the source region 6 (see FIG. 7) and the p-type contact layer 7 (see FIG. 7) are exposed at the bottom of the same connection hole. Next, as shown in FIG. 10, for example, a metal film is formed on the epitaxial layer 3 including the respective connection holes and on the interlayer insulating film 19 by sputtering. The metal film contains, for example, Al (aluminum), and is completely embedded inside each of the plurality of connection holes. Then, the metal film on the interlayer insulating film 19 is processed by photolithography and etching to partially expose one surface of the upper surface of the interlayer insulating film 19. The metal film is separated into a plurality of electrodes by the processing step to form a plurality of electrodes composed of the metal film. That is, the electrode 105 to which the Vdd potential is applied, the electrode 106 to which the Vss potential is applied, and the output electrode 104 are formed. The electrode 105 is connected to the n-type contact layer 13 and the source region 12 via a contact plug formed of the above-described metal film in the connection hole. The electrode 106 is connected to the p-type contact layer 7 (see FIG. 7) and the source region 6 (see FIG. 7) via a contact plug formed of the above-described metal film in the connection hole. The output electrode 104 is connected to the drain regions 5, 11 via contact plugs. Then, the back surface electrode 2 covering the back surface of the SiC substrate 1 is formed by, for example, a sputtering method. The back surface electrode 2 is, for example, a conductive film containing Au (gold), for example, an electrode to which a Vdd potential is applied. The nMOS 101 and the pMOS 102, which are mutually connected to each other, constitute a CMOS. By the above steps, the CMOS which is the tantalum carbide semiconductor device of the present embodiment can be formed. <Effects of the Present Embodiment> Hereinafter, the effects of the present embodiment will be described using FIG. 25 as a comparative example. Fig. 25 is a cross-sectional view showing a tantalum carbide semiconductor device of a comparative example. As a material for a semiconductor substrate of a semiconductor device, Si (yttrium) can be considered. However, it is difficult to expose to a high-temperature semiconductor device that cannot be driven by a semiconductor device that is installed in an engine unit of an automobile, a turbine engine of an aircraft, or a boiler that emits a high temperature. A Si substrate is used in such a semiconductor device. Moreover, when a cooling device for cooling a semiconductor device used in a high-temperature environment is provided, the device is prevented from being small, light, and low in cost. Further, it is considered to provide an information processing device that cannot withstand high temperatures in a place away from a machine that emits high heat. However, even if the self-heating sensor outputs a small output signal, the signal-to-noise ratio cannot be sufficiently ensured due to the long current path. Therefore, complicated noise processing is required, which also hinders small size, light weight, and low cost. In order to reduce the influence of noise at a low cost, it is effective to create a high-heat-resistant integrated device that maintains the edge calculation, LSI (Large), even in a high-temperature environment, by processing the output signal of the sensor in front of the so-called edge calculation. Scale Integration, a large-scale integrated circuit) is essential. In this case, as a device that can be used in a high-temperature environment, a tantalum carbide semiconductor element using a substrate containing SiC (tantalum carbide) is used as a material of a substrate of a tantalum carbide semiconductor device used in a high-temperature environment, and 4H-SiC is suitable. . On the other hand, the channel mobility of 4H-SiC is lower than that of Si. As a countermeasure against this, it is conceivable to form a niobium carbide semiconductor device as shown in FIG. 25 as a comparative example. As shown in FIG. 25, the tantalum carbide semiconductor device of the comparative example is provided with nMOS 107 in the vicinity of the main surface of the semiconductor substrate SB including the SiC substrate 1 and the epitaxial layer 3 thereon. Forming a pair of mutually separated pairs on the surface of the epitaxial layer 3 ^- Type SiC region 321, and each p ^- The upper surface of the SiC region 321 is formed adjacent to each other ⁺ Type SiC regions 322 and p ⁺ Type SiC region 323. Again, from a pair of p ^- The opposite ends of the respective SiC regions 321 are extended to n ⁺ The end of the SiC region 322, at each p ^- A channel region (defect reducing layer) 324 is formed on the upper surface of the SiC region 321 . A BN pair structural insulating film 325 that is in contact with the upper surface is formed on the upper surface of the channel region 324. The channel region 324 is a region in which C (carbon) defects are reduced by introducing C (carbon) to the upper surface of the epitaxial layer 3. Further, the BN pair structure insulating film 325 is a film formed by diffusing N (nitrogen) to the upper surface of the channel region 324. In the BN pair structure insulating film 325, p ^- B (boron) in the type SiC region 321 pulls the N (nitrogen) to form a stable BN pair. For a pair of p ^- On the upper surface of the epitaxial layer 3 between each of the SiC regions 321 , a gate electrode 340 is formed through the gate insulating film 330 . The gate insulating film 330 and the gate electrode 340 cover a pair of p ^- The BN pair of the upper surface of each of the SiC regions 321 is configured to form the insulating film 325, the channel regions 324, and n ⁺ A portion of a type SiC region 322. In a pair of p ^- One of the SiC regions 321 ^- n formed on the upper surface of the SiC region 321 ⁺ Type SiC regions 322 and p ⁺ The upper surface of the SiC region 323 is connected to the source electrode 350 at another p ^- n formed on the upper surface of the SiC region 321 ⁺ Type SiC regions 322 and p ⁺ The upper surface of the SiC region 323 is connected to the source electrode 350. Here, in order to improve the mobility (channel mobility) of the nMOS 107, a channel region 324 into which C is introduced is provided. Further, in order to stabilize the threshold voltage of the nMOS 107, a BN pair structure insulating film 325 is formed between the channel region 324 and the gate insulating film 330 made of an oxide film or the like by N diffusion. However, in the MOSFET of the comparative example, the improvement of the mobility of the pMOS is not considered, and there is a problem that the performance of the CMOS in which the nMOS and the pMOS are combined may not be improved. Here, the channel mobility indicating the flow difficulty of the current in the transistor or the like differs depending on the crystal plane of the hexagonal crystal, and also varies depending on the carrier (electron or hole). The reason for this is that, depending on the crystal plane, the ratio of the existence of the defects that hinder the flow of electrons is inferior to the ratio of the existence of the defects that hinder the flow of the holes. The mobility is related to interface defects. For example, nMOS with electrons as a carrier can be said to have an interface defect of 1×10 near the conduction band. ¹² Cm ² The a side below the eV forms a channel. However, in pMOS with a hole as a carrier, the interface defect of the a-plane is 3×10. ¹² ~5×10 ¹² Cm ² Since eV is large, it is difficult to increase the mobility when the channel of pMOS is formed on the a-plane. On the other hand, the interface defect near the valence band when the channel of the pMOS is formed on the Si surface is as low as 5 × 10 ¹¹ Cm ² eV, so you can expect the mobility to increase. In the present embodiment, when nMOS and pMOS are formed on a SiC substrate made of hexagonal crystals, the mobility of both nMOS and pMOS is improved by selecting the crystal plane of the channel of each MOSFET. In other words, in the pMOS in which the hole is a carrier, the channel is provided on the Si surface or the C surface, and the mobility is improved as compared with the case where the channel is formed on the other crystal plane. In the nMOS in which electrons are used as carriers, by setting the channel to the a-plane, the mobility is improved as compared with the case where the channel is formed on the other crystal faces. Therefore, as shown in FIG. 1, the pMOS 102 constituting the CMOS MOSFET is formed into a planar MOSFET, and a channel (channel region) is formed on the main surface of the semiconductor substrate SB which is the Si surface. Further, by forming the nMOS 101 in the CMOS MOSFET into a trench gate type MOSFET, a channel (channel region) is formed on the a plane perpendicular to the main surface of the semiconductor substrate SB which is the Si surface. As a result, the mobility of the nMOS is not increased as in the comparative example, and the mobility of the pMOS 102 and the mobility of the nMOS 101 can be simultaneously improved. Thereby, the performance of the tantalum carbide semiconductor device of the present embodiment including the CMOS composed of the nMOS 101 and the pMOS 102 can be improved. In the present embodiment, the case where the crystal plane of the formation channel of the pMOS 102 is a Si surface will be described. However, when the crystal plane of the pMOS 102 forming the channel is the C surface, the same effect can be obtained. Further, in the present embodiment, a case where the crystal plane of the formation channel of the nMOS 101 is the a surface will be described. On the other hand, when the channel is formed on the m-plane, the mobility of the nMOS 101 is different from that of the channel formed on the a-plane, but the phase of the nMOS is formed on the crystal plane other than the a-plane and the m-plane. Compared, it can increase the mobile rate. In other words, by forming the nMOS 101 having the a-plane or the m-plane with the channel, the mobility can be improved, and in particular, in the nMOS 101 having the channel on the a-plane, the mobility can be remarkably improved. Since the a surface and the m surface are perpendicular to the Si surface and the C surface, the groove can be formed on the main surface of the semiconductor substrate SB in which the crystal surface of the main surface is the Si surface or the C surface, so that the a surface or the m surface can be formed. It is exposed on the side of the groove 8. Hereinafter, variations and other embodiments of the present embodiment will be described. In any of the embodiments and variations, the pMOS formed on the Si surface and the nMOS formed on the a surface can be formed by the pMOS 102. The increase in the mobility rate and the increase in the mobility of the nMOS 101. <Variation 1> FIG. 11 is a plan view showing a tantalum carbide semiconductor device according to a first modification of the first embodiment. In the trench gate type nMOS of the present embodiment, it is considered that a p-type contact layer adjacent to the source region is formed, and a p-type contact layer is sandwiched between the two source regions, but in this case, the source of nMOS Since the width of the polar region is increased, it is difficult to achieve miniaturization of the tantalum carbide semiconductor device. Here, the width of the source region means that a plurality of channel regions sandwiched by the source region and the drain region are disposed in the direction in which the source region and the drain region are arranged, that is, in the extending direction (Y direction) of the trench gate electrode. In this case, the distance between the two end portions of the source region in the direction is the distance between the channel region and the source region at both ends of the source region. Therefore, the width of the source region when the p-type contact layer is sandwiched between the two source regions means that the end portions of the two source regions are opposite to the end portions adjacent to the p-type contact layer. The distance between the ends. Therefore, in the present modification, a layout capable of shortening the width of the source region of the nMOS is shown in FIG. As shown in FIG. 11, a ring-shaped p-type contact layer 7 is formed so as to surround a plurality of grooves 8 in plan view. Thereby, the p-type contact layer 7 does not need to be formed at a position adjacent to the source region 6, and therefore, the source region width in the Y direction can be shortened. Further, by forming the p-type contact layer 7 so as to surround the trench 8, the p-type contact layer 7 can function as an element isolation layer. <Variation 2> FIG. 12 is a plan view showing a tantalum carbide semiconductor device according to a second modification of the first embodiment. In the trench gate type nMOS of the present embodiment, in order to reduce the width of the source region, a p-type contact layer that surrounds a plurality of trench gate electrodes in a plan view is considered. However, in this case, the distance between the channel formed between the source region and the drain region and the p-type contact layer is relatively large, and therefore, the potential of the p-type diffusion layer near the channel may be unstable. That is, there is a difference in potential difference between the p-type diffusion layer and the trench gate electrode. Therefore, a layout in which the source region width of the nMOS 101 can be shortened and the potential of the p-type diffusion layer 4 can be made more stable is shown in FIG. Here, the groove 8 is not surrounded by the p-type contact layer 7 in plan view, and the p-type contact layer 7 is formed by interposing the source region 6 in a region adjacent to the groove 8 in the X direction. That is, in the X direction, two source regions 6 and the p-type contact layer 7 sandwiched by the source regions 6 are disposed between the adjacent grooves 8. The p-type contact layer 7 is in contact with the source region 6 between the p-type contact layer 7 and the trench 8. In the present modification, the p-type contact layer 7 is not formed between the adjacent grooves 8, and the p-type diffusion can be suppressed as compared with the case where the p-type contact layer 7 is formed so as to surround the grooves 8 in plan view. The in-plane variation of the potential of the layer 4 makes it possible to stabilize the threshold voltage of the nMOS 101. <Variation 3> A perspective view of a tantalum carbide semiconductor device according to a third modification of the first embodiment is shown in FIG. As shown in FIG. 13, in the present variation, the drain region 5 and the source are formed deeper than the drain region 11, the source region 12, and the p-type contact layer 7 and shallower than the gate electrode 10 of the nMOS 101. Each of the region 6 and the n-type contact layer 13. By forming the drain region 5 and the source region 6 deeper in this manner, the width of the region where the drain region 5 and the source region 6 face each other, that is, the channel width is increased, and thus, compared with 汲When the depths of the polar region 5 and the source region 6 are equal to those of the drain region 11 and the source region 12, the channel resistance of the nMOS 101 can be reduced. Here, since the n-type contact layer 13 is formed by the same ion implantation step as the drain region 5 and the source region 6, it is formed deeper in the same manner as the drain region 5 and the source region 6. <Variation 4> A perspective view of a tantalum carbide semiconductor device according to a fourth modification of the first embodiment is shown in FIG. The configuration of this modification is different from the configuration shown in Fig. 1 only in the thickness of one portion of the gate insulating film 9, and the other structures are the same as those shown in Fig. 1. As shown in FIG. 14, the CMOS of the present modification is characterized in that the gate insulating film 9 formed in contact with the bottom surface of the trench 8 is formed to be in contact with the side surface of the trench 8 to form the gate insulating film 9. Large thickness. According to this feature, the thickness of the gate insulating film 9 that is in contact with the bottom surface of the trench 8 is thinner than the thickness of the gate insulating film 9 that is in contact with the side of the trench 8, as compared with the case of the trench 8 It is difficult for the bottom surface to produce an inversion layer. Thereby, the threshold voltage of the nMOS 101 on the bottom surface of the trench 8 can be made larger than the threshold voltage of the nMOS 101 on the side of the trench 8. That is, it is possible to reduce the influence of the current flowing on the bottom surface of the groove 8 on the current flowing in the nMOS 101. In the trench gate type nMOS 101, the crystal face of the channel formed on the side of the groove 8 is different from the crystal face of the channel formed on the bottom surface of the groove 8. Therefore, when the thicknesses of the gate insulating films 9 of the respective side faces and the bottom faces of the trenches 8 are equal, the current flows on the two different crystal faces. For example, when the crystal surface of the side surface of the groove 8 of the nMOS 101 is the a surface, the crystal surface of the bottom surface of the groove 8 is a Si surface or a C surface. In this case, for the nMOS 101, the bottom surface of the groove 8 becomes a surface having a larger interface defect than the side surface. The interface defect is a factor that is difficult to control due to manufacturing conditions or the state of the substrate. If the size of the interface defect is not uniform, the temperature dependence of the nMOS 101 deviates from the design value. In the present variation, by increasing the thickness of the gate insulating film 9 covering the bottom surface of the trench 8, the channel current flowing on the bottom surface having a large interface defect in the surface of the trench 8 can be reduced, and therefore, the characteristics of the nMOS 101 depend on In the state of the side of the slot 8. Thereby, the temperature dependence of the device is stable. In the case where the gate insulating film 9 shown in FIG. 14 is formed, after the groove 8 (refer to FIG. 7) is formed, a thin tantalum nitride film covering the side surface and the bottom surface of the groove 8 and not completely filling the groove 8 is formed. (insulation film). Then, by performing anisotropic etching, the tantalum nitride film which is in contact with the bottom surface of the trench 8 is removed in the case where the tantalum nitride film which is in contact with the side surface of the trench 8 remains, and the bottom surface is exposed. Then, for example, a ruthenium oxide film (insulating film) covering the bottom surface of the groove 8 and having a relatively large first film thickness is formed by, for example, an oxidation method. Then, the tantalum nitride film covering the side surface of the groove 8 is removed to expose the side surface. Thereafter, as described with reference to FIG. 8, the insulating film 22 having the second film thickness and the gate electrodes 10 and 14 having the side faces of the trench 8 and the main surface of the semiconductor substrate SB are formed. Thereby, the gate insulating film 9 including the insulating film 22 that is in contact with the side surface of the trench 8 and the tantalum nitride film that is in contact with the bottom surface of the trench 8 can be formed (see FIG. 14). The second film thickness is smaller than the first film thickness. Further, the ruthenium oxide film on the main surface of the semiconductor substrate SB, that is, above the groove 8, is removed as needed. <Variation 5> A perspective view of a tantalum carbide semiconductor device according to a fifth modification of the first embodiment is shown in FIG. The configuration of this modification is different from the configuration shown in FIG. 1 in that a p-type semiconductor region 20 is formed in the semiconductor substrate SB near the bottom of the trench 8, and the other structure is the same as that shown in FIG. As shown in FIG. 15, a p-type semiconductor region 20 is formed in the epitaxial layer 3 so as to cover the bottom surface of the trench 8. Further, a portion of the p-type semiconductor region 20 also covers a portion of the side surface of the groove 8 continuous with the bottom surface of the groove 8, that is, the side surface of the groove 8 near the bottom surface of the groove 8. A p-type semiconductor region 20 is formed in the vicinity of the lower end of the side surface of the trench 8, but most of the side surface of the trench 8 is composed of the p-type diffusion layer 4. The p-type semiconductor region 20 is formed from the inside of the p-type diffusion layer 4 to the epitaxial layer 3 which is located below the p-type diffusion layer 4. The p-type impurity concentration of the p-type semiconductor region 20 is higher than the p-type impurity concentration of the p-type diffusion layer 4. In other words, the p-type impurity concentration of the bottom surface of the trench 8 is higher than the p-type impurity concentration of the side surface of the trench 8. In the present modification, the p-type semiconductor region 20 is formed in the vicinity of the bottom of the trench 8 as a high-concentration impurity region in which the conductivity type and the channel conductivity type (n-type) are different. In other words, a p-type semiconductor region 20 having a conductivity type different from the conductivity type (n-type) of the drain region 5 and the source region 6 of the nMOS 101 is formed in the vicinity of the bottom of the trench 8. Thereby, similarly to the above-described modification 4, in the nMOS 101, the threshold voltage of the bottom surface of the trench 8 can be made larger than the threshold voltage of the side surface of the trench 8. Therefore, the influence of the bottom surface of the trench 8 on the characteristics of the nMOS 101 can be reduced, so that the characteristics of the nMOS 101 can be stabilized. <Variation 6> A perspective view of a CMOS which is a silicon carbide semiconductor device according to a sixth modification of the first embodiment is shown in FIG. The configuration of this modification is different from the configuration shown in Fig. 15 in that a p-type semiconductor region 24 is formed, and other configurations are the same as those shown in Fig. 15, and the p-type semiconductor region 24 covers the phase in the X direction. The upper surface of the epitaxial layer 3 between the adjacent regions of the trenches 8 and the drain regions 5 and the source regions 6 adjacent to each other in the Y direction. The depth of the p-type semiconductor region 24 is shallower than the depth of each of the drain region 5 and the source region 6. Therefore, although the p-type semiconductor region 24 is formed near the upper end of the side surface of the trench 8, the p-type semiconductor region 20 is formed near the lower end of the side surface of the trench 8, but the majority of the side surface of the trench 8 is composed of the p-type diffusion layer 4. Composition. The p-type impurity concentration of the p-type semiconductor region 24 is higher than the p-type impurity concentration of the p-type diffusion layer 4. In other words, the p-type impurity concentration on the upper surface of the epitaxial layer 3 where the p-type semiconductor region 24 is formed is higher than the p-type impurity concentration on the side of the groove 8 below the p-type semiconductor region 24. Here, a p-type semiconductor region 24 is formed on the upper surface of the epitaxial layer 3 between the drain region 5 and the source region 6. Thereby, in the nMOS 101, the current flowing on the upper surface (main surface) of the epitaxial layer 3, which is the Si surface, can be reduced, so that the characteristics of the nMOS 101 can be further stabilized. (Embodiment 2) A CMOS according to Embodiment 2 will be described with reference to Figs. 17 and 18 . Fig. 17 is a perspective view showing a tantalum carbide semiconductor device according to the embodiment, and Fig. 18 is a plan view showing the tantalum carbide semiconductor device of the embodiment. The structure shown in Figs. 17 and 18 has the same structure as that of the above-described first embodiment except that an element isolation region having the same structure as that of the trench 8 and the gate electrode 10 is formed on the outer periphery of the nMOS 101. As shown in FIGS. 17 and 18, the CMOS of the present embodiment is characterized in that the potential of the trench gate electrode (conductor portion) 21 in the outermost peripheral groove 8 of the plurality of grooves 8 is p-type diffused. Layer 4 is electrically connected. That is, an annular groove 8 is formed in such a manner that a plurality of grooves 8 arranged in the X direction and their internal gate electrodes 10, the drain regions 5 and the source regions 6 are surrounded in plan view. A trench gate electrode 21 is formed in the trench 8 so as to be separated from the gate insulating film 9. The trench gate electrode 21 is a conductor portion formed by the step of forming the gate electrode 10. The material of the trench gate electrode 21 is the same as that of the gate electrode 10. The trench gate electrode 21 is electrically connected to the p-type contact layer 7 and the p-type diffusion layer 4 via the contact plug 15 and the electrode 106. That is, the groove gate electrode 21 in the outermost groove 8 among the plurality of grooves 8 arranged in the X direction is applied with the groove other than the outermost one of the plurality of grooves 8 arranged in the X direction. The gate electrode 10 in the trench 8 other than 8 has a different potential. Here, between the groove 8 of the most end portion of the plurality of grooves 8 arranged in the X direction and the groove 8 adjacent to the groove 8, a portion is formed on a portion of the upper surface of the p-type diffusion layer 4 Type contact layer 7. The p-type contact layer 7 has a function of lowering the connection resistance of the p-type diffusion layer 4 and the contact plug 15, and extracting a hole current. According to the above configuration, in the present embodiment, the latching operation of the CMOS can be suppressed without adding a manufacturing step. Here, the latching operation and its countermeasures will be described. A CMOS parasitic bipolar transistor that is not separated by an insulating film, for example, a source region 6 as an emitter, a p-type diffusion layer 4 as a base, and an epitaxial layer 3 as a collector, and npn exists. Crystal structure. Similarly, a pnp transistor is parasitic. If the product of the current gain of the two transistors exceeds 1, latch-up occurs and a large current flows. The breakthrough of the parasitic npn transistor is sometimes caused by the current flowing in the resistance of the p-type diffusion layer 4 sandwiched between the source region 6 and the epitaxial layer 3, and the resulting voltage When the drop exceeds the built-in voltage, the parasitic element (parasitic npn transistor) becomes conductive, and it becomes impossible to control the parasitic element. In particular, in the semiconductor substrate SB using SiC, the sheet resistance of the p-type diffusion layer 4 is relatively high at 100 to 300 kΩ/□. Therefore, it is desired to control the latching operation by reducing the current flowing in the p-type diffusion layer 4. As shown in FIG. 17, when the trench gate electrode 21 electrically connected to the p-type diffusion layer 4 is formed in the annular groove 8 surrounding the plurality of trenches 8 in plan view, the epitaxial layer 3 is transferred from the epitaxial layer 3 to the p. The current flowing in the lateral direction of the type diffusion layer 4 becomes difficult to flow. Thereby, the current flowing in the p-type diffusion layer 4 is reduced, so that the occurrence of latch-up can be prevented. Further, by setting the trench gate electrode 21 in the outermost peripheral groove 8 to the same potential as that of the p-type diffusion layer 4, the nMOS 101 of the outermost periphery of the plurality of nMOSs 101 is always turned off. Thereby, the electron current flowing to the epitaxial layer 3 can be reduced, so that the parasitic bipolar transistor can be prevented from being turned on. Further, a p-type contact layer 7 for extracting a hole current is provided between the groove 8 located at the outermost side in the X direction and the groove 8 located at the second position from the outer side, thereby preventing the latching operation. Furthermore, it is also possible to form a p-type contact not only on one surface of the upper surface of the p-type diffusion layer 4 adjacent to the outermost peripheral groove 8, but also on the entire upper surface of the p-type diffusion layer 4 adjacent to the outermost peripheral groove 8. Layer 7. That is, the annular p-type contact layer 7 may be formed along the outermost circumferential groove 8 so as to surround all the grooves 8 on the inner side of the outermost circumferential groove 8 in plan view. Thereby, the entire p-type diffusion layer 4 can be easily set to the same potential as the trench gate electrode 21, so that the parasitic bipolar transistor can be more stably prevented from being turned on. (Embodiment 3) FIG. 19 is a perspective view showing a CMOS of a silicon carbide semiconductor device according to the third embodiment. The structure of the present embodiment is different from the structure shown in Fig. 1 in that a tantalum nitride film 16 covering the side surface and the bottom surface of the groove 8 is formed, and other structures are the same as those shown in Fig. 1. That is, only the interface between the gate insulating film 9 of the nMOS 101 and the p-type diffusion layer 4 is nitrided, whereby the tantalum nitride film 16 is formed. Such a tantalum nitride film 16 can be formed by the step of forming the gate insulating film 9 (refer to FIG. 8) and before the step of forming the gate electrode 10, ₂ (nitrogen) and O ₂ The semiconductor substrate SB is formed by heat-treating at 1200 to 1300 ° C in an atmosphere of a mixed gas of (oxygen). This heat treatment is performed in a state in which a hard mask (insulating film) which covers the surface of the exposed trench 8 and covers the main surface of the semiconductor substrate SB is formed, thereby preventing the main surface of the semiconductor substrate SB from being nitrided in the pMOS region 1A. deal with. After the nitriding treatment, the hard mask is removed. Further, in the present modification, after the gate electrode 10 is formed, the gate electrode 14 is formed by a conductive film different from the electrode film constituting the gate electrode 10. In the nMOS 101, by nitriding the surface of the channel region in contact with the gate insulating film 9, it is possible to obtain an effect of reducing the number of defects of the surface, that is, the number of defects that hinder the flow of electrons. However, in the case where the surface of the channel region of the pMOS 102 is subjected to the nitriding treatment, the mobility of the pMOS 102 is lowered. Therefore, the surface of the channel region of the pMOS 102 that is in contact with the gate insulating film (not shown) is not nitrided, and the surface of the channel region of the nMOS 101 that is in contact with the gate insulating film 9 is nitrided. deal with. Therefore, the mobility of the nMOS 101 can be improved without lowering the mobility of the pMOS 102. Therefore, the performance of the CMOS can be further improved. (Embodiment 4) FIG. 20 is a perspective view showing a CMOS as a silicon carbide semiconductor device according to the fourth embodiment. The overall structure of the CMOS of the present embodiment is the same as that of the structure shown in Fig. 1. However, in the present embodiment, the work function of the gate electrode 17 in the trench 8 of the nMOS 101 is smaller than the work function of the gate electrode 14 of the pMOS 102. In the tantalum carbide semiconductor device, since the band gap of SiC used for the semiconductor substrate is large, the threshold voltage of the nMOS is likely to be high, and the threshold voltage of the pMOS is likely to be low. Here, the gate electrode 17 includes polycrystalline germanium as an n-type semiconductor to which P (phosphorus) as an n-type impurity is introduced, or Al (aluminum) or W (tungsten). Thereby, the work function of the gate electrode 17 becomes lower as compared with the case where the gate electrode 17 is composed of a p-type semiconductor film. Therefore, the threshold voltage of the nMOS 101 can be lowered. Further, the gate electrode 18 includes a p-type semiconductor polysilicon into which B (boron) as a p-type impurity is introduced. Thereby, the work function of the gate electrode 18 becomes higher as compared with the case where the gate electrode 18 is composed of an n-type semiconductor film, an Al (aluminum) film, or a W (tungsten) film. Specifically, the threshold voltage of the gate electrode 18 is a negative value, and since the gate electrode 18 is constituted by a p-type semiconductor film, the threshold voltage of the gate electrode 18 is close to 0 V. Therefore, the threshold voltage of the pMOS 102 can be increased. In the case where each of the gate electrodes 17 and 18 is formed of a semiconductor film of a different conductivity type, as long as the formation of the gate electrodes 10 and 14 described with reference to FIG. 8, the gate electrodes 10 and 14 are formed. Each of them can be introduced with impurities of different conductivity types. In the present embodiment, by lowering the threshold voltage of the nMOS 101 and increasing the threshold voltage of the pMOS 102, the difference between the threshold voltages of the nMOS 101 and the pMOS 102 can be reduced. In other words, since the threshold voltage of each of the nMOS 101 and the pMOS 102 can be optimized, the performance of the silicon carbide semiconductor device of the present embodiment can be further improved. The invention made by the inventors of the present invention has been specifically described based on the embodiments thereof, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. For example, in the above-described first to fourth embodiments, nMOS is formed in a trench structure, and pMOS is formed in a planar structure. However, nMOS may be formed as a planar MOS and pMOS may be formed as a trench depending on the plane orientation of the wafer to be used. Slot gate MOS. In this case, the shapes of the respective nMOS and pMOS described in the first to fourth embodiments are exchanged. In other words, for example, when a silicon carbide semiconductor device is formed using a wafer having a crystal plane of the principal surface as a surface, a planar nMOS having a channel on the main surface is formed, and is formed in a trench formed as the main surface. The Si or C side of the side has a pMOS of the channel. Further, in the above-described first to fourth embodiments, the case where the conductivity type of the semiconductor substrate is n-type will be described, but the conductivity type may be p-type. In this case, although not described in the present embodiment, an n-type well is formed on the main surface of the semiconductor substrate in the region where the via of the pMOS is formed. Moreover, the layout shown in FIG. 3, FIG. 11, and FIG. 12 is an example. For example, the layout of each of FIGS. 3 and 11 can be combined with each other, and the layout of each of FIGS. 11 and 12 can be combined.

1‧‧‧ SiC substrate

1A‧‧‧pMOS area

1B‧‧‧nMOS area

2‧‧‧Back electrode

3‧‧‧ epitaxial layer

4‧‧‧p type diffusion layer

5‧‧‧Bungee area

6‧‧‧ source area

7‧‧‧p-type contact layer

8‧‧‧ slots

9‧‧‧Gate insulation film

10‧‧‧gate electrode

11‧‧‧Bungee area

12‧‧‧ source area

13‧‧‧n type contact layer

14‧‧‧ gate electrode

15‧‧‧Contact layer plug

16‧‧‧ nitride film

17‧‧‧ gate electrode

18‧‧‧ gate electrode

19‧‧‧Interlayer insulating film

20‧‧‧p-type semiconductor region

21‧‧‧Groove gate electrode

22‧‧‧Insulation film

23‧‧‧Gate insulation film

24‧‧‧p-type semiconductor region

101‧‧‧nMOS

102‧‧‧pMOS

103‧‧‧Input terminal

104‧‧‧Output terminal

105‧‧‧Electrode

106‧‧‧Electrode

107‧‧‧nMOS

201‧‧‧C face

202‧‧‧Si face

203‧‧‧a

204‧‧‧m face

205‧‧‧S face

206‧‧‧r face

321‧‧‧p ^- type SiC region

322‧‧‧n ⁺ type SiC area

323‧‧‧p ⁺ type SiC region

324‧‧‧Channel area

325‧‧‧BN on structural insulation film

330‧‧‧gate insulating film

340‧‧‧gate electrode

350‧‧‧Source electrode

A1‧‧‧ horizontal axis

A2‧‧‧ horizontal axis

A3‧‧‧ horizontal axis

C‧‧‧vertical axis

SB‧‧‧Semiconductor substrate

Fig. 1 is a perspective view showing a tantalum carbide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a circuit diagram showing a tantalum carbide semiconductor device according to a first embodiment of the present invention. Fig. 3 is a plan view showing a tantalum carbide semiconductor device according to a first embodiment of the present invention. Fig. 4 is a perspective view showing a manufacturing step of the tantalum carbide semiconductor device according to the first embodiment of the present invention. Fig. 5 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 4. Fig. 6 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 5. Fig. 7 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 6. Fig. 8 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 7. Fig. 9 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 8. Fig. 10 is a perspective view showing the manufacturing steps of the tantalum carbide semiconductor device of Fig. 9. FIG. 11 is a plan view showing a tantalum carbide semiconductor device according to a first modification of the first embodiment of the present invention. FIG. 12 is a plan view showing a tantalum carbide semiconductor device according to a second modification of the first embodiment of the present invention. Fig. 13 is a perspective view showing a tantalum carbide semiconductor device according to a third modification of the first embodiment of the present invention. Fig. 14 is a perspective view showing a tantalum carbide semiconductor device according to a fourth modification of the first embodiment of the present invention. Fig. 15 is a perspective view showing a tantalum carbide semiconductor device according to a fifth modification of the first embodiment of the present invention. Fig. 16 is a perspective view showing a tantalum carbide semiconductor device according to a sixth modification of the first embodiment of the present invention. Fig. 17 is a perspective view showing a tantalum carbide semiconductor device according to a second embodiment of the present invention. Fig. 18 is a plan view showing a tantalum carbide semiconductor device according to a second embodiment of the present invention. Fig. 19 is a perspective view showing a tantalum carbide semiconductor device according to a third embodiment of the present invention. Fig. 20 is a perspective view showing a tantalum carbide semiconductor device according to a fourth embodiment of the present invention. Fig. 21 is a perspective view schematically showing a lattice model of a hexagonal system. Fig. 22 is a perspective view schematically showing a lattice model of a hexagonal system. Fig. 23 is a perspective view schematically showing a lattice model of a hexagonal system. Fig. 24 is a perspective view schematically showing a lattice model of a hexagonal system. Fig. 25 is a cross-sectional view showing a tantalum carbide semiconductor device as a comparative example.

Claims (15)

A tantalum carbide semiconductor device comprising: a semiconductor substrate containing tantalum carbide and having a hexagonal crystal structure; and a complementary field effect transistor formed of n-types respectively formed near a main surface of the semiconductor substrate The field effect transistor and the p-type field effect transistor are configured; and the n-type field effect transistor has a first channel formed on the (11-20) plane or the (0-110) plane of the crystal plane of the semiconductor substrate The p-type field effect transistor includes a second channel region formed on the (000-1) plane or the (0001) plane of the crystal plane of the semiconductor substrate. The silicon carbide semiconductor device according to claim 1, wherein the n-type field effect transistor includes the first channel region formed on a (11-20) plane of a crystal plane of the semiconductor substrate. The silicon carbide semiconductor device according to claim 1, wherein the n-type field effect transistor has the first channel region on the main surface of the semiconductor substrate, and the p-type field effect transistor is formed on the main surface of the semiconductor substrate The side of the groove has the second passage region described above. The silicon carbide semiconductor device according to claim 1, wherein the n-type field effect transistor system is composed of a first gate electrode, a first source region, and a first drain region, and the first gate electrode is separated from the first gate. a pole insulating film is formed in a groove formed in the main surface of the semiconductor substrate, and a first source region and a first drain region are formed on a side surface of the trench and are spaced apart from each other; and the p-type field effect transistor system is The second gate electrode is configured to be the second source region and the second drain region, and the second gate electrode is formed on the main surface of the semiconductor substrate via the second gate insulating film, and the second source region And the second drain region is formed on the main surface of the semiconductor substrate and spaced apart from each other; and the first drain region and the second drain region are electrically connected to each other, and the first gate electrode and the second gate are The pole electrodes are electrically connected to each other. The silicon carbide semiconductor device according to claim 4, wherein a first film thickness of said first gate insulating film that is in contact with a bottom surface of said groove is larger than a second thickness of said first gate insulating film that is in contact with a side surface of said groove Film thickness. A silicon carbide semiconductor device according to claim 4, wherein a p-type impurity concentration of a bottom surface of said groove is higher than a p-type impurity concentration of said side surface of said groove. The silicon carbide semiconductor device according to claim 4, wherein the grooves are formed in two in a first direction along the main surface of the semiconductor substrate, between the two grooves, along the main surface of the semiconductor substrate The p-type impurity concentration of the main surface of the semiconductor substrate between the first source region and the first drain region arranged in parallel in the second direction orthogonal to the first direction is higher than the groove The p-type impurity concentration of the above side surface. The silicon carbide semiconductor device according to claim 4, wherein the plurality of grooves are formed in a first direction along a first direction of the main surface of the semiconductor substrate; and the plurality of grooves are formed on the main surface of the semiconductor substrate. The upper surface of the semiconductor layer; and the first gate electrode formed in the outermost trench in the first direction is electrically connected to the p-type semiconductor layer. A silicon carbide semiconductor device according to claim 4, further comprising a tantalum nitride film formed between the trench and the first gate insulating film. A silicon carbide semiconductor device according to claim 4, wherein a work function of said first gate electrode is lower than a work function of said second gate electrode. A method for producing a niobium carbide semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate having a hexagonal crystal structure including niobium carbide; and (b) forming a first source region on a main surface of the semiconductor substrate; Formed in the first direction spaced apart from the first drain region; (c) forming the first source region and the first surface on one side surface of the first surface of the first region of the semiconductor substrate a trench in the drain region; (d) forming the second source region and the second drain region spaced apart from each other on the main surface of the second region of the semiconductor substrate; (e) interposing in the trench a first gate electrode is formed on the gate insulating film, and a second gate electrode is formed on the main surface of the semiconductor substrate in the second region via a second gate insulating film; and the first gate electrode and the first gate electrode The first source region and the first drain region constitute an n-type field effect transistor; the second gate electrode, the second source region, and the second drain region constitute a p-type field effect transistor; The main surface of the substrate is in the crystal plane of the semiconductor substrate In the (000-1) plane or the (0001) plane, the side surface of the groove is a (11-20) plane or a (0-110) plane in the crystal plane of the semiconductor substrate. The method of manufacturing a silicon carbide semiconductor device according to claim 11, wherein the side surface of the trench is a (11-20) plane in a crystal plane of the semiconductor substrate. The method of manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step (e) comprises the steps of: (e1) forming a first insulating film covering the side surface of the trench and exposing a bottom surface of the trench; (e2) After the step (e1), a second insulating film having a first film thickness covering the bottom surface of the groove is formed; (e3) after the step (e2), the groove is removed by removing the first insulating film (e4) after the step (e3), forming a second insulating film that covers the side surface of the groove and the main surface of the semiconductor substrate and has a second film thickness smaller than the first film thickness And forming the first gate insulating film including the first insulating film and the second insulating film covering the side surface of the trench; and the first insulating film including the second insulating film covering the main surface of the semiconductor substrate a gate insulating film; (e5) forming the first gate electrode in the trench and the second gate electrode on the second gate insulating film. The method of manufacturing a silicon carbide semiconductor device according to claim 11, further comprising the steps of: (c1) introducing a p-type impurity into a bottom surface of the trench after the step (c) and before the step (e); The p-type impurity concentration of the bottom surface of the trench is higher than the p-type impurity concentration of the side surface of the trench. The method of manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step (e) includes the steps of: (e6) forming the first gate insulating film and the second gate insulating film; (e7) the above (e6) After the step of forming a hard mask covering the main surface of the semiconductor substrate and exposing the surface of the trench; (e8) after the step (e7), by the surface of the first gate insulating film and the trench The interface is nitrided, and a tantalum nitride film is formed between the first gate insulating film and the surface of the trench; (e9) after the step (e8), the hard mask is removed, and then the above is formed The first gate electrode in the trench and the second gate electrode on the second gate insulating film.