JP2006310879A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with an SOI structure aiming at reducing substrate floating effect. <P>SOLUTION: Each transistor formation region of an SOI layer 3 is separated by a partial oxide film 31 in which a well region is formed at the lower layer. A p-type well region 11 is formed as the lower layer of the partial oxide film 31 that separates between NMOS transistors. An n-type well region 12 is formed as the lower layer of the partial oxide film 31 that separates between PMOS transistors. The p-type well region 11 and the n-type region 12 are formed and adjoined as lower layers of the partial oxide film 31 that separates between NMOS transistors and PMOS transistors. A body region is in contact with the adjoining well region 11. A wiring layer formed on an interlayer dielectric 4 is electrically connected with the body region through a body contact arranged in the interlayer dielectric 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an SOI structure.

  As shown in FIG. 102, in a conventional SOI structure semiconductor device comprising a silicon substrate 1, a buried oxide film 2 and an SOI (Silicon On Insulator) layer, a transistor formation region in the SOI layer 3 is completely formed by a complete oxide film 32. Was separated. For example, one unit of NMOS transistor formed in the NMOS transistor formation region is completely separated from other transistors by the complete oxide film 32. In the example of FIG. 102, the SOI layer 3 is covered with an interlayer insulating film 4.

  In FIG. 102, one unit of NMOS transistor, which is completely separated from other transistors by the complete oxide film 32, has a drain region 5, a source region 6, a channel formation region 7, and a channel formation region 7 formed in the SOI layer 3. And a gate electrode 9 formed on the gate oxide film 8. In addition, the wiring layer 22 formed on the interlayer insulating film 4 is electrically connected to the drain region 5 or the source region 6 through a contact 21 provided in the interlayer insulating film 4.

  As described above, since the conventional SOI structure semiconductor device is completely separated in the SOI layer in element (transistor) units, the PMOS and NMOS transistors are completely separated so that latch-up does not occur in principle. Presents.

  Therefore, in the case of manufacturing a semiconductor device having a CMOS transistor with an SOI structure, there is an advantage that the minimum separation width determined by the microfabrication technology can be used and the chip area can be reduced. However, carriers generated by impact ionization (holes in NMOS) accumulate in the channel formation region, which causes kinks, deteriorates the operating breakdown voltage, and the potential of the channel formation region is not stable. There are various problems caused by the floating effect of the substrate, such as the frequency dependence of.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain an SOI structure semiconductor device in which the substrate floating effect is reduced.

  According to a first aspect of the present invention, there is provided a semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer, and an SOI layer, and a plurality of elements provided in the SOI layer, each of which includes a predetermined element. A formation region, an element isolation region that is provided in the SOI layer and that isolates the plurality of element formation regions from each other, and a body region capable of fixing a potential from the outside. The region is formed so as to be in contact with the front surface or the back surface of at least one element formation region.

  3. The semiconductor device according to claim 2, wherein the body region is formed in an upper layer portion of the buried insulating layer and is in contact with a back surface of the at least one element forming region.

  4. The semiconductor device according to claim 3, wherein the body region is formed through the buried insulating layer and is in contact with a back surface of the at least one element formation region.

  5. The semiconductor device according to claim 4, wherein the body region is provided above the at least one element formation region and is in contact with a surface of the at least one element formation region.

  Since the body region of the semiconductor device according to the first aspect of the present invention is formed so as to be in contact with the front surface or the back surface of at least one of the plurality of element formation regions, the at least one element formation region Can be fixed by the body region.

  In the semiconductor device according to claim 2, since the body region is formed in an upper layer portion of the buried insulating layer below the SOI layer, an adverse effect on the element isolation characteristics by the element isolation region can be minimized.

  According to another aspect of the present invention, since the body region is formed through the buried insulating layer, the potential of the at least one element formation region can be fixed from the semiconductor substrate side via the body region.

  5. The semiconductor device according to claim 4, wherein the body region is provided above the at least one element forming region and is in contact with the surface of the at least one element forming region, so that the body region can be formed relatively easily.

<< Embodiment 1 >>
1 to 3 are diagrams showing the configuration of an SOI structure semiconductor device according to the first embodiment of the present invention. 1 and 2 are sectional views, and FIG. 3 is a plan view. The AA and BB sections in FIG. 3 are respectively FIG. 1 and FIG.

  As shown in these drawings, each transistor formation region of the SOI layer 3 in the SOI structure semiconductor device including the silicon substrate 1, the buried oxide film 2, and the SOI layer is formed by a partial oxide film 31 in which a well region is formed in a lower layer portion. To be separated. A p-type well region 11 is formed below the partial oxide film 31 separating the NMOS transistors, and an n-type well region 12 is formed below the partial oxide film 31 separating the PMOS transistors. The p-type well region 11 (NMOS transistor side) and the n-type well region 12 (PMOS transistor side) are formed below the partial oxide film 31 separating the PMOS transistors. The well region 11 is formed so as to surround the drain region 5 and the source region 6 of the NMOS transistor group, and the well region 12 is formed so as to surround the drain region 5 and the source region 6 of the PMOS transistor group. In the first embodiment, the SOI layer 3 is covered with the interlayer insulating film 4.

  In the first embodiment, one unit of MOS transistor separated from other transistors by the partial oxide film 31 includes a drain region 5, a source region 6, a channel formation region 7, and a channel formation region 7 formed in the SOI layer 3. The gate oxide film 8 is formed on the gate oxide film 8 and the gate electrode 9 is formed on the gate oxide film 8. In addition, the wiring layer 22 formed on the interlayer insulating film 4 is electrically connected to the drain region 5 or the source region 6 through a contact 21 provided in the interlayer insulating film 4.

  As shown in FIGS. 2 and 3, a body region 10 is formed between the well regions 11 in the SOI layer 3, and the body region 10 is in contact with the adjacent well region 11. The wiring layer 25 formed on the interlayer insulating film 4 is electrically connected to the body region 10 via the body contact 23 provided in the interlayer insulating film 4. Further, the wiring layer 26 formed on the interlayer insulating film 4 is electrically connected to the gate electrode 9 through the gate contact 24 provided in the interlayer insulating film 4.

  Thus, in the semiconductor device of the first embodiment, as shown in FIGS. 1 to 3, unlike the conventional configuration shown in FIG. 102, the partial oxide film 31 in the element isolation region reaches the lower part of the SOI layer 3. The well regions 11 and 12 into which impurities of the same conductivity type as the channel formation region of the transistor to be separated are introduced are provided below the partial oxide film 31.

  Therefore, the substrate potential of each transistor can be fixed through the wiring layer 25, the body contact 23, the high-concentration body region 10, and the well region 11. Similarly, the substrate potential of each transistor can be fixed via the body region on the PMOS transistor side.

Hereinafter, the details will be described with reference to FIGS. The thickness of the buried oxide film 2 is, for example, about 100 to 500 nm, and the thickness of the SOI layer 3 is about 30 to 200 nm. The channel formation region 7 is formed by introducing a first conductivity type impurity (p-type impurity for NMOS, n-type impurity for PMOS) of about 10 ¹⁷ to 10 ¹⁸ / cm ³ , for example. The drain region 5 and the source region 6 are adjacent to the channel forming region 7 and are introduced by introducing a second conductivity type impurity (for example, n-type impurity for NMOS and p-type impurity for PMOS) of about 10 ¹⁹ -10 ²¹ / cm ³ . It is formed.

  The partial oxide film 31 that separates adjacent transistors is formed by leaving the lower layer portion of the SOI layer 3 for, for example, about 10 to 100 nm for forming a well region. The upper surface height of the partial oxide film 31 is preferably the same as the surface height of the SOI layer 3 in terms of fine processing. However, when the SOI layer 3 is thin, the film thickness of the partial oxide film 31 necessary for element isolation can be taken. Since it is difficult, the element isolation performance is improved by raising the layer above the SOI layer 3.

Under the element isolation partial oxide film 31, well regions 11 and 12 having the same conductivity type as the channel formation region (for example, impurity concentrations of 10 ^{17 to} 5 · 10 ¹⁸ / cm ³ , the impurity concentration is the same as that of the channel formation region). The same or more, the higher the concentration, the more the punch-through can be prevented and the separation performance is improved).

Further, as shown in FIG. 2, the body region 10 is doped with impurities of the same conductivity type as that of the adjacent well region 11 and having a high concentration of 10 ¹⁹ to 10 ²¹ / cm ³ .

  In the body region 10 of FIG. 2, the body region 10 is formed from the upper surface to the lower surface of the SOI layer 3 and the body contact 23 is formed through the interlayer insulating film 4, but the body region is formed as shown in FIG. May be.

  In the example of FIG. 4, the body region 20 is formed only in the lower layer portion of the SOI layer 3 in accordance with the shape of the body contact 23, and the body contact 23 is formed through the interlayer insulating film 4 and the partial oxide film 31. Become. In this case, a well region 28 is formed under the partial oxide film 31 adjacent to the body region 20.

  However, when the structure of FIG. 4 is formed, it is desirable to perform high-concentration impurity implantation for forming the body region 20 after the contact opening.

  Here, in the element isolation of the same conductivity type, the well regions 11 and 12 need only be formed by introducing the same impurity as the conductivity type of the channel formation region. However, as shown in FIG. Further, in the separation, it is necessary to provide the p-type well region 11 in the NMOS adjacent portion and the n-type well region 12 in the PMOS adjacent portion.

  Such an SOI structure can be manufactured using the isolation method using a partial trench according to a second embodiment to be described later.

<< Embodiment 2 >>
<First aspect>
FIG. 5 is a cross-sectional view showing the structure of the first aspect of the SOI structure semiconductor device according to the second embodiment of the present invention.

  As shown in FIG. 5, in the second embodiment, transistor isolation inside the NMOS transistor and the PMOS transistor is performed by the partial oxide film 31 and the well region 11 (12) below it, while the PMOS transistor and the NMOS transistor are separated. Separation is performed by the complete oxide film 32. By adopting such a configuration, the separation width between the PMOS and NMOS can be reduced and latch-up can be prevented as compared with the structure of the first embodiment.

  In realizing the structure of FIG. 5, when the source region 6 and the drain region 5 are formed by ion implantation, the implanted ions pass through the partial oxide film 31, which is essentially the reverse of the drain region 5 and the source region 6. By introducing impurities for the drain region 5 and the source region 6 into the well region 11 (12) under the partial oxide film 31 that needs to be of the conductivity type, the separation characteristics of the partial oxide film 31 and the well region 11 are improved. There is a risk of damage.

<Second aspect>
In order to avoid this, it is preferable to form the drain region 5s and the source region 6s whose formation depth is sufficiently shallower than the film thickness of the SOI layer 3, as shown in the second mode shown in FIG. That is, the drain region 5 s and the source region 6 s are preferably formed shallower than the lower surface of the partial oxide film 31. As shown in FIG. 6, in order to form the drain region 5s and the source region 6s having a shallow formation depth, the source and drain regions 6s and 5s may be formed by low energy ion implantation.

  The formation depth of the drain region 5s and the source region 6s is a built-in state (a state when the bias voltage applied to the PN junction is 0 V), and a depletion layer from the source / drain reaches the buried oxide film 2. Ideally, it should be formed to a depth that satisfies this condition.

  This is because the source / drain depletion layer reaches the buried oxide film 2 in the built-in state, so that the partial oxide film can be reduced while reducing the junction capacitance between the source / drain region 6s / 5s and the well region 11 (12). This is because the isolation characteristics by the partial isolation region by the 31 and the well region 11 (12) can be improved.

<Third Aspect>
Here, as in the third mode of the second embodiment shown in FIG. 7, a part of the lower layer becomes the well region 29, but the oxide film 33 is used from the upper surface to the lower surface of the SOI layer 3 to form an NMOS transistor, It is also possible to completely separate the PMOS transistors. In the third mode, since the trench for the oxide film 33 is easily formed simultaneously with the trench for the partial oxide film 31, the layout is likely to be easier than the separation by the complete oxide film 32.

  Hereinafter, the complete separation by the oxide film 33 is the complete isolation region by the oxide film 33 in the penetrating portion that penetrates the SOI layer 3, the oxide film 33 in the non-penetrating portion that does not penetrate the SOI layer 3, and the SOI layer 3 therebelow. There are cases where it is called separation by a composite separation region in which a partial separation region by the well region 29 is continuously formed.

<Fourth aspect>
Further, as in the fourth mode shown in FIG. 55, the upper surfaces of the partial oxide film 31 for performing partial isolation independently and the oxide film 33 in the composite isolation region are formed so as to be uniform with no unevenness, thereby forming the gate electrode. There is an effect that patterning at the time of forming 9 is facilitated.

<Fifth aspect>
56 is a sectional view showing details of the structure of the oxide film 33 in the composite isolation region shown in FIG. As shown in the figure, the oxide film 33 is formed so that the central portion (penetrating portion) reaches the lower surface from the upper surface of the SOI layer 3, but the peripheral portion (non-penetrating portion) is formed without reaching the lower surface. A portion of the SOI layer 3 remaining below the peripheral portion of the oxide film 33 becomes the well region 29. In the oxide film 33 having such a structure, between the film thickness TB of the SOI layer 3 (well region 29) below the periphery of the oxide film 33 and the film thickness TA of the SOI layer 3 above the well region 29, TA > TB is formed so as to be established. That is, the film thickness of the well region 29 is set to be less than half of the film thickness (TA + TB) of the SOI layer 3.

  When formed so that TA> TB is satisfied as in the fifth aspect, the threshold voltage due to the separation of the oxide film 33 (threshold voltage when the oxide film 33 is regarded as a gate oxide film) is sufficiently increased, and a sufficiently high level is achieved. Can be obtained, and by sufficiently reducing the PN junction area between the drain / source region formed in contact with the well region 29 and the well region 29, generation of leakage current can be suppressed, and the PN junction capacitance can be reduced. By reducing it, high speed operation becomes possible.

<Sixth aspect>
FIG. 57 is a sectional view showing details of the structure of the oxide film 33 shown in FIG. As shown in the figure, between the complete isolation width WC, which is the formation width of the central portion of the oxide film 33 formed from the upper surface to the lower surface of the SOI layer 3, and the oxide film isolation width WD of the entire oxide film 33. And WC <WD / 2.

  By configuring as in the sixth aspect, a sufficient area of the well region 29 formed below the peripheral portion of the oxide film 33 can be secured, so that the transistor floating level is sufficiently suppressed through the well region 29. The substrate potential can be fixed, and as a result, the transistor can be stably operated.

  Further, by making the complete separation width WC the same in the chip, the separation shape management becomes easy. Further, since the elements can be electrically completely separated as long as the oxide film 33 can be patterned, the complete isolation width WC can be set to the minimum design width, and the chip area can be reduced to the minimum necessary, and the degree of integration can be greatly improved. Can be achieved.

<Others>
In the second embodiment, at least the NMOS transistor and the PMOS transistor are completely separated from each other. However, in the memory mixed logic circuit, the memory portion and the logic circuit portion are completely separated from each other for noise countermeasures. The structure to do is also considered.

  Further, instead of using the complete isolation region and the partial isolation region in combination, a method of performing plural types of partial isolation using oxide films having different formation depths is also conceivable. In this case, the well region under the deep oxide film can be used as a complete isolation region in a floating state without connecting a body contact material such as a body region to the well region.

<Production Method (Part 1) (First and Second Aspects)>
8 to 11 are cross-sectional views showing element isolation steps of the manufacturing method according to the first and second modes of the second embodiment. The method shown in FIGS. 8 to 11 is a method in which partial trench isolation and complete trench isolation are used in combination.

  First, as shown in FIG. 8, an SOI substrate made of a silicon substrate 1, a buried oxide film 2 and an SOI layer 3 formed by a SIMOX method for forming a buried oxide film 2 by oxygen ion implantation is used as a starting material. Normally, the SOI layer 3 has a thickness of 50 to 200 nm, and the buried oxide film 2 has a thickness of 100 to 400 nm.

  Then, as shown in FIG. 9, an oxide film 41 of about 20 nm and a nitride film 42 of about 200 nm are sequentially deposited on the SOI substrate, and then the isolation region is patterned using the patterned resist 43 as a mask. A plurality of partial trenches 44 are formed by etching the three multilayer films of the oxide film 41 and the SOI layer so that the lower layer portion of the SOI layer 3 remains. Since the plurality of partial trenches 44 are formed with a predetermined width and extending in a substantially vertical direction with respect to the silicon substrate 1, it is possible to perform element isolation while maintaining miniaturization without impairing the degree of integration. In this state, as shown in FIG. 12, a high-concentration well region 52 (corresponding to the well regions 11 and 12) is formed, so that the isolation breakdown voltage can be further increased by performing ion implantation.

  Next, as shown in FIG. 10, a resist 45 is formed so as to cover a part of the plurality of partial trenches 44, and the partial trenches 44 not covered with the resist 45 are further etched to thereby form an SOI layer. A complete trench 48 penetrating 3 is formed.

  Next, as shown in FIG. 11, an oxide film having a thickness of about 500 nm is deposited and polished to the middle of the nitride film 42 by a CMP process in the same manner as in normal trench isolation, and then the nitride film 42 and the oxide film 41 are formed. By performing the removal, it is possible to obtain a structure in which the partial oxide film 31 and the underlying SOI layer 3 (well region) and the complete oxide film 32 are selectively formed. As described above, by polishing the oxide film by the CMP process, the upper surfaces of the partial oxide film 31 and the complete oxide film 32 can be uniformly formed without unevenness. When the ion implantation shown in FIG. 12 is performed after the structure of FIG. 9 is obtained, a high concentration well region 52 is formed under the partial oxide film 31 as shown in FIG. The substrate potential can be fixed with high stability by the high concentration well region 52.

  Hereinafter, the SOI structure of the first embodiment shown in FIG. 5 or the SOI structure shown in FIG. 6 is formed by forming an NMOS transistor in the NMOS transistor formation region and forming a PMOS transistor in the PMOS transistor formation region by an existing method. The SOI structure of the second aspect can be obtained.

  Further, if the steps shown in FIG. 10 are omitted and the other steps are performed as described above, all become partial trenches 44. Therefore, the structure of the first embodiment shown in FIGS. A structure in which elements are separated by the partial oxide film 31 can be obtained.

<Production Method (Part 2) (First and Second Aspects)>
14 to 18 are cross-sectional views showing element isolation steps of the manufacturing method according to the first and second modes of the second embodiment. The method shown in FIGS. 14 to 18 is a method in which partial trench isolation and complete trench isolation are used in combination.

  First, as shown in FIG. 14, a stacked structure including a silicon substrate 1, a buried oxide film 2, and a silicon layer 50 is used as a starting material. At this time, the silicon layer 50 is made thinner than the film thickness of the finally obtained SOI layer 3.

  Then, as shown in FIG. 15, after an oxide film 41 and a nitride film 42 are sequentially deposited on the SOI substrate, a patterning process of the isolation region is performed using the patterned resist 46 as a mask, and the surface of the silicon layer 50 is exposed. Thus, the nitride film 42 and the oxide film 41 are etched to form a plurality of partial trenches 44.

  Next, as shown in FIG. 16, a resist 49 is formed so as to cover a part of the plurality of partial trenches 44, and the partial trenches 44 not covered with the resist 49 are further etched to form a silicon layer. A complete trench 48 penetrating 50 is formed.

  Next, as shown in FIG. 17, an oxide film is deposited and polished to the middle of the nitride film 42 by a CMP process in the same manner as in normal trench isolation, and then the nitride film 42 and the oxide film 41 are removed. As a result, it is possible to obtain a structure in which the partial oxide film 31 and the underlying silicon layer 50 (well region) and the complete oxide film 32 are selectively formed.

  Then, as shown in FIG. 18, an epitaxial silicon layer 51 is formed by epitaxial growth from the silicon layer 50, thereby obtaining the SOI layer 3 having good crystallinity composed of the silicon layer 50 and the epitaxial silicon layer 51.

  Hereinafter, the SOI structure of the first embodiment shown in FIG. 5 or the SOI structure shown in FIG. 6 is formed by forming an NMOS transistor in the NMOS transistor formation region and forming a PMOS transistor in the PMOS transistor formation region by an existing method. The SOI structure of the second aspect can be obtained.

<Production Method (Part 3) (Third Aspect)>
19 to 22 are sectional views showing an element isolation step in the manufacturing method according to the third aspect of the second embodiment. The method shown in FIGS. 19 to 22 is a method by forming partial trenches having different formation widths.

  First, as shown in FIG. 19, a relatively wide partial trench 44A and a relatively narrow partial trench 44B are formed. The partial trench 44A is for complete isolation, and the partial trench 44B is for partial isolation. At this time, the partial trenches 44A and 44B are formed so that a part of the lower layer of the SOI layer 3 remains.

  Next, as shown in FIG. 20, sidewalls are formed on the side surfaces of the partial trenches 44 </ b> A and 44 </ b> B with the oxide film 47 so that the bottom surface of the partial trench 44 </ b> B is closed but the bottom center portion of the partial trench 44 </ b> A is exposed. This utilizes the fact that the formation width of the partial trench 44B is narrower than the formation width of the partial trench 44A.

  Next, as shown in FIG. 21, by performing silicon etching on the SOI layer 3 using the oxide film 47 as a mask, the oxide film 47 is formed on the upper portion including the SOI layer 3 below the center of the bottom surface of the partial trench 44A. The SOI layer 3 that has not been removed is removed, and the surface of the buried oxide film 2 is exposed.

  Next, as shown in FIG. 22, an oxide film having a thickness of about 500 nm is deposited and polished to the middle of the nitride film 42 by a CMP process in the same manner as in normal trench isolation, and then the nitride film 42 and the oxide film 41 are formed. By performing the removal, a structure in which the partial oxide film 31 (and the underlying SOI layer 3) and the oxide film 33 (and the partially underlying SOI layer 3) are selectively formed can be obtained.

  Hereinafter, the SOI structure of the third mode of the second embodiment shown in FIG. 7 is formed by forming an NMOS transistor in the NMOS transistor formation region and forming a PMOS transistor in the PMOS transistor transistor formation region by an existing method. Obtainable.

<Production Method (Part 4) (Third Aspect)>
23 to 27 are sectional views showing an element isolation step in the manufacturing method of the third aspect of the second embodiment. The method shown in FIGS. 23 to 27 is a method by forming partial trenches having different formation widths.

  First, as shown in FIG. 23, an SOI substrate including a silicon substrate 1, a buried oxide film 2, and an SOI layer 3 is used as a starting material.

  Then, as shown in FIG. 24, a relatively wide partial trench 44A and a relatively narrow partial trench 44B are formed. The partial trench 44A is for complete isolation, and the partial trench 44B is for partial isolation. At this time, the partial trenches 44A and 44B are formed so that a part of the lower layer of the SOI layer 3 remains.

  Next, as shown in FIG. 25, the resist 49 is patterned so as to fill the entire inside of the partial trench 44B and cover the side wall of the partial trench 44A. Therefore, the central portion of the bottom surface of the partial trench 44A is reliably exposed.

  Thereafter, as shown in FIG. 26, by performing silicon etching on the SOI layer 3 using the resist 49 as a mask, the resist 49 including the SOI layer 3 below the center of the bottom surface of the partial trench 44A is not formed on the upper portion. The SOI layer 3 is removed, and the surface of the buried oxide film 2 is exposed.

  Next, as shown in FIG. 27, an oxide film is deposited and polished to the middle of the nitride film 42 by a CMP process in the same manner as in normal trench isolation, and then the nitride film 42 and the oxide film 41 are removed. Thus, it is possible to obtain a structure in which the partial oxide film 31 (and the underlying SOI layer 3) and the oxide film 33 (and the underlying SOI layer 3) are selectively formed.

<Production Method (Part 5) (Third Aspect)>
58 to 62 are sectional views showing an element isolation step in the manufacturing method of the third aspect of the second embodiment.

  First, as shown in FIG. 58, an SOI substrate including a silicon substrate 1, a buried oxide film 2, and an SOI layer 3 is used as a starting material.

  Then, as shown in FIG. 59, after an oxide film 41 and a nitride film 42 are sequentially deposited on the SOI substrate, a patterning process of the isolation region is performed using the patterned resist 213 as a mask, and the surface of the buried oxide film 2 is exposed. Thus, a plurality of trenches 214 are formed through the nitride film 42, the oxide film 41, and the SOI layer 3 by etching.

  Next, as shown in FIG. 60, a resist 215 is selectively formed on the remaining nitride film 42. At this time, the resist 215 is formed so that an area including each of the plurality of trenches 214 and wider than the formation width of the trenches 214 becomes an opening.

  Then, as shown in FIG. 61, by etching the nitride film 42 and the oxide film 41 and a part of the SOI layer 3 using the resist 215 as a mask, a partial trench 216 in which the SOI layer 3 remains in the lower layer, and a central portion A composite trench 217 including a through portion in which the lower layer penetrates the SOI layer 3 and a non-penetrated portion in which the SOI layer 3 remains in the other lower layer is simultaneously formed.

  Thereafter, as shown in FIG. 62, an oxide film is deposited by HDP (High Density Plasma) CVD or the like, polished to the middle of the nitride film 42 by a CMP process in the same manner as normal trench isolation, and then nitride film 42. By removing the oxide film 41, a structure in which the partial oxide film 31 (and the SOI layer 3 thereunder) and the oxide film 33 (and the SOI layer 3 below a part thereof) are selectively formed is obtained. be able to.

<Production Method (Part 6) (Third Aspect)>
As an extreme example of the manufacturing method, the partial isolation region is etched away so as to penetrate through the SOI layer 3 after the formation of the gate electrode of the transistor separated by partial isolation, or in the subsequent stage of the contact or wiring process. After that, it is also possible to change to a complete separation region by embedding an oxide film.

<Others>
In the manufacturing method of the second embodiment, as a trench isolation method, a stack of SiN / SiO ₂ is formed on the SOI layer and an oxide film for element isolation is embedded. However, other methods, SiN / SiO _{2 are used.} It goes without saying that the same effect can be obtained by using various methods such as, for example, by performing post-embedding oxidation by using a stack of SiN / poly-Si / SiO _{2 and} rounding the corners of the trench. Yes.

<< Embodiment 3 >>
<First aspect>
FIG. 28 is a cross sectional view showing the structure of the first mode of the SOI structure semiconductor device according to the third embodiment of the present invention.

  As shown in FIG. 28, integration is required (the partial oxide film 31 is slightly inferior to the complete oxide film 32 due to the formation of the well region in the lower layer), but the circuit (first step) is less affected by the substrate floating effect. 1) is formed in a completely isolated structure using the complete oxide film 32, and the partial oxide film 31 and its lower well are formed in the formation area of the circuit (second circuit) in which the influence of the substrate floating effect is a problem. A partial isolation structure using the region 11 (12) is used, and a separation between the formation regions of the first and second circuits is a complete isolation structure using the complete oxide film 32.

  In addition, as a first circuit example, there is a circuit of a memory cell portion such as SRAM or DRAM that requires a dense structure, and as a second circuit example, there is a circuit other than the memory cell portion.

  As shown in FIG. 28, examples of the first circuit include an internal circuit and a digital circuit. Examples of the second circuit circuit include an I / O buffer circuit, an analog circuit (PLL circuit, sense amplifier circuit). Etc. Further, as a second circuit example, there are a timing circuit, a dynamic circuit, and the like.

  As described above, in the first mode of the third embodiment, the partial separation by the partial oxide film 31 and the complete separation by the complete oxide film 32 are properly used in consideration of the influence of the substrate floating effect of the provided circuit. Thus, an element isolation structure in which the substrate floating effect is suppressed and the degree of integration is well balanced can be obtained.

  In the structure of FIG. 28, the partial oxide film 31 and the complete oxide film 32 (oxide film 33) are selectively formed by using the first to fourth methods of the manufacturing method of the second embodiment, thereby isolating elements. And can be obtained by forming a first circuit and a second circuit.

<Second aspect>
FIG. 29 is a cross sectional view showing the structure of the second mode of the SOI structure semiconductor device according to the third embodiment of the present invention. As shown in the figure, the thickness of the first circuit formation partial SOI layer 3B for complete isolation is made thinner than the thickness of the second circuit formation partial SOI layer 3A for partial isolation. Yes. Therefore, the film thickness of the complete oxide film 34, the drain region 5t, the source region 6t, and the channel formation region 7t formed in the partial SOI layer 3B is also reduced.

  In the second aspect, since the film thickness of the first partial SOI layer 3B for forming a circuit is formed smaller than the film thickness of the second partial SOI layer 3A for forming a circuit, even if the same trench etching conditions are used, A partial trench can be formed in the partial SOI layer 3A and a complete trench can be formed in the partial SOI layer 3B. Therefore, the manufacturing method can be simplified such that the step shown in FIG. 10 of the manufacturing method 1 can be omitted, and complete separation and partial separation can be performed on the partial SOI layer 3B and the partial SOI layer 3A, respectively.

  In addition, an SOI that forms a second circuit requiring a fixed substrate potential regardless of complete separation or partial separation, such as an I / O buffer circuit, an analog circuit (PLL, sense amplifier), a timing circuit, a dynamic circuit, and the like. It is preferable to increase the thickness of the layer, and the second aspect makes sense from this point of view as well. In particular, in the protection circuit, the temperature rise can be suppressed by the film thickness, which is effective.

<Third Aspect>
Further, as a third aspect of the third embodiment, the I / O circuit or RF circuit serving as a noise generation source is separated from other circuits by at least complete separation using the complete oxide film 32. Isolation is performed using the partial oxide film 31 to obtain an SOI structure semiconductor device in which the influence of the substrate floating effect is minimized while reducing the influence of the noise on the internal circuit and the analog circuit which is vulnerable to the noise. be able to.

<< Embodiment 4 >>
30 and 31 are cross-sectional views showing the structure of an SOI structure semiconductor device according to the fourth embodiment of the present invention. 30 and 31 correspond to the AA cross section and the BB cross section of FIG. 3 of the first embodiment, respectively.

  As shown in the figure, each transistor formation region of the SOI layer 3 in the SOI structure semiconductor device including the silicon substrate 1, the buried oxide film 2 and the SOI layer 3 is formed by a partial oxide film 71 in which a well region is formed in a lower layer portion. To be separated. A p-type polysilicon region 61 is formed below the partial oxide film 71 that separates the NMOS transistors, and an n-type polysilicon region 62 is formed below the partial oxide film 71 that separates the PMOS transistors. A p-type polysilicon region 61 (NMOS transistor side) and an n-type polysilicon region 62 (PMOS transistor side) are formed adjacent to each other under the partial oxide film 71 that separates the NMOS transistor and the PMOS transistor.

  As shown in FIG. 31, body region 10 is formed between polysilicon regions 61 in SOI layer 3, and body region 10 is in contact with adjacent polysilicon region 61. The wiring layer 25 formed on the interlayer insulating film 4 is electrically connected to the body region 10 via the body contact 23 provided in the interlayer insulating film 4.

  As described above, the semiconductor device of the fourth embodiment uses the polysilicon regions 61 and 62 formed under the partial oxide film 71 as well regions, and the potential is fixed via the body region 10. Therefore, the potential of the channel formation region 7 is stabilized, and the substrate floating effect can be reduced.

  As shown in FIG. 32, the transistor isolation inside the NMOS transistor and the PMOS transistor is performed by the partial oxide film 71 and the polysilicon region 61 (62) below it, while the separation between the PMOS transistor and the NMOS transistor is performed. Alternatively, the complete oxide film 32 may be used. With such a configuration, the separation width between the PMOS and NMOS can be reduced and latch-up can be prevented as compared with the structures of FIGS.

<Manufacturing method>
33 to 37 are cross-sectional views showing element isolation steps in the method of manufacturing a semiconductor device of the fourth embodiment.

  First, as shown in FIG. 33, an SOI substrate including a silicon substrate 1, a buried oxide film 2 and an SOI layer 3 is used as a starting material, and an oxide film 41 and a nitride film 42 are sequentially deposited on the SOI substrate, and then a patterned resist is formed. The isolation region is patterned using 43 as a mask, and a trench 53 is formed through the three multilayer films of the nitride film 42, the oxide film 41, and the SOI layer.

  34, after depositing a polysilicon layer 65 on the entire surface with good film thickness controllability, a resist 66 is formed so as to cover a part of the plurality of trenches 53 as shown in FIG. Then, the polysilicon layer 65 in the trench 53 not covered with the resist 66 is removed by etching, thereby forming a complete trench 48.

  Next, as shown in FIG. 36, an oxide film for filling the trench is deposited on the entire surface, and polished to the middle of the nitride film 42 by CMP processing in the same manner as in normal trench isolation. By removing the film 41, it is possible to obtain a structure in which the polysilicon region 67 and the oxide film 68 and the complete oxide film 32 remaining therein are selectively formed.

  Then, as shown in FIG. 37, by oxidizing the polysilicon region 67, a partial oxide film 71 composed of an oxide film 68 and a region where the polysilicon region 67 is oxidized, and a polysilicon region remaining without being oxidized. A partial separation structure with 61 (62) is completed.

  Since the degree of oxidation of the polysilicon region 67 is higher than that of the oxide film 70 formed on the SOI layer 3, a sufficient step is generated between the surface of the SOI layer 3 and the uppermost portion of the polysilicon region 61 (62). It is possible to prevent the gate electrode 9 and the polysilicon region 61 from being short-circuited due to an oxide film defect when forming the gate oxide film.

  Hereinafter, an SOI structure shown in FIG. 32 can be obtained by forming an NMOS transistor in the NMOS transistor formation region and forming a PMOS transistor in the PMOS transistor formation region by an existing method.

<< Embodiment 5 >>
<First aspect>
FIG. 38 is a cross sectional view showing the structure of the first aspect of the SOI structure semiconductor device according to the fifth embodiment of the present invention. As shown in the drawing, each transistor formation region of the SOI layer 3 in the SOI structure semiconductor device including the silicon substrate 1, the buried oxide film 2 and the SOI layer 3 is a low dielectric constant film (where a well region is formed in the lower layer). Insulating film 75 having a dielectric constant lower than that of a general insulating film such as buried oxide film 2). Then, as in the first embodiment shown in FIG. 1, the p-type well region 11 is formed under the low dielectric constant film 75 that separates the NMOS transistors, and the low dielectric constant film 75 that separates the PMOS transistors. An n-type well region 12 is formed in the lower layer, and a p-type well region and an n-type well region (not shown in FIG. 38) are formed under the low dielectric constant film 75 separating the NMOS transistor and the PMOS transistor. Is formed. The well region described above can be fixed in potential via a body region that is electrically connected, as in the first embodiment.

  In the case of the SOI structure, the thickness of the SOI layer 3 may be as thin as about 50 nm. At this time, the well region formed under the element isolation oxide film (partial oxide film 31 in FIG. 1) may be depleted or inverted, and a leakage current may flow between the transistors that should originally be isolated.

  However, in the first aspect of the fourth embodiment, since the low dielectric constant film 75 is used for element isolation, the capacitance can be kept sufficiently low even if the film thickness is thin, and the above-described leakage current generation is ensured. Can be avoided.

  As the low dielectric constant film 75, relative dielectric constant can be obtained by mixing fluorine in a silicon oxide film (relative dielectric constant of about 3.9 to 4) used for the buried oxide film 2 or the like or using an organic film. Is about 3.

<Second aspect>
FIG. 39 is a cross-sectional view showing a second mode of the fifth embodiment. As shown in the figure, element isolation is performed by a low dielectric constant film 76 and a silicon oxide film 78 formed on the bottom and side surfaces of the low dielectric constant film 76 instead of the low dielectric constant film 75 of FIG. . Other configurations are the same as those of the first mode shown in FIG.

  As described above, the silicon oxide film 78 is formed on the bottom and side surfaces of the low dielectric constant film 76 because defects and interface charges generated at the interface with silicon (drain region 5, source region 6, well regions 11, 12, etc.) are formed. This is to reliably suppress the occurrence of the above. The silicon oxide film 78 is formed using a thermal oxidation method or a CVD method.

<Third Aspect>
FIG. 40 is a cross-sectional view showing a third mode of the fifth embodiment. As shown in the figure, element isolation is performed by a low dielectric constant film 77 and a silicon oxide film 79 formed on the side surface of the low dielectric constant film 77 instead of the low dielectric constant film 75 of FIG. Other configurations are the same as those of the first mode shown in FIG.

  As described above, the silicon oxide film 79 is formed on the side surface of the low dielectric constant film 77 because defects or interfaces generated at the interface with the silicon (drain region 5 and source region 6) in the side surface direction where the channel forming region 7 exists. This is because the main purpose is to reliably suppress the generation of electric charges.

<< Embodiment 6 >>
<First aspect>
FIG. 41 is a cross sectional view showing the structure of the first mode in the SOI structure semiconductor device according to the sixth embodiment of the present invention.

  As shown in the figure, the elements are completely separated by an interlayer insulating film 4 (for convenience of explanation, a portion corresponding to the complete oxide film 32 is also shown by the interlayer insulating film 4), and a connection region 80 serving as a body region is buried. It is formed in the upper layer portion of the oxide film 2 and a part thereof is in contact with the back surface of the end portion of the SOI layer 3 (drain region 5 and channel forming region 7 in FIG. 41), thereby maintaining an electrical connection relationship. Note that the conductivity type of the connection region 80 is the same as that of the channel formation region 7. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  As described above, since the connection region 80 serving as the body region is provided not in the SOI layer 3 but in the upper layer portion of the buried oxide film 2 in the semiconductor device of the first aspect, at least the film of the SOI layer 3 between the gate electrode 9 is provided. A height difference greater than the thickness can be provided. As a result, it is possible to reliably avoid the problem that the gate electrode 9 and the connection region 80 are short-circuited during manufacturing.

<Second aspect>
FIG. 42 is a cross sectional view showing the structure of the second mode in the SOI structure semiconductor device according to the sixth embodiment of the present invention.

  As shown in the figure, the drain region 5 s and the source region 6 s are shallowly formed in the upper layer portion of the SOI layer 3. Other configurations are the same as those of the first mode shown in FIG.

  As described above, since the drain region 5s and the source region 6s are shallowly formed in the upper layer portion of the SOI layer 3 in the semiconductor device of the second aspect, the drain region 5s or the source region 6 and the connection region 80 have a contact relationship, and leak current is generated. It can be avoided reliably.

<Manufacturing method (concept)>
43 to 45 are sectional views conceptually showing the process of forming a polysilicon region to be the connection region 80.

  First, as shown in FIG. 43, the element formation region in which the trench isolation is performed by selectively removing the SOI layer 3 from the surface from the SOI structure including the silicon substrate 1, the buried oxide film 2, and the SOI layer 3. Form.

  Then, as shown in FIG. 44, wet etching is performed on the buried oxide film 2 using the SOI layer 3 as a mask, and the buried oxide film 2 on the lower surface of the end of the SOI layer 3 is removed, but the SOI layer 3 does not exist on the upper part. A hole 94 is formed by removing the upper layer portion of the buried oxide film 2.

  Then, as shown in FIG. 45, a polysilicon region 81 for the connection region 80 is formed by embedding polysilicon in the hole 94.

<Manufacturing method (1)>
46 to 48 are sectional views showing more specifically the first step of forming the polysilicon region to be the connection region 80.

  First, as shown in FIG. 46, a silicon oxide film 91 and a silicon nitride film 92 are deposited on the SOI layer 3 of the SOI substrate, and the SOI layer 3, the silicon oxide film 91 and the silicon nitride film 92 are patterned to perform trench isolation. After the process, a sidewall silicon nitride film 93 is formed on the side surfaces of the patterned SOI layer 3, silicon oxide film 91, and silicon nitride film 92.

  Then, as shown in FIG. 47, wet etching is performed on the buried oxide film 2 using the silicon nitride film 92 and the sidewall silicon nitride film 93 as a mask, and the buried oxide film 2 on the back surface of the end portion of the SOI layer 3 is removed. By removing the upper layer portion of the buried oxide film 2 exposed without the SOI layer 3 existing on the upper portion, the hole portion 94 is formed.

  Thereafter, as shown in FIG. 48, after a polysilicon layer is deposited on the entire surface, the polysilicon layer is etched back by dry etching, so that the polysilicon is embedded in the hole 94 and the polysilicon region 81 for the connection region 80 is formed. Form.

  Hereinafter, as in the process shown in FIG. 11, a plurality of element formation regions are insulated and isolated by a method such as embedding an oxide film in the trench, the potential of the connection region 80 can be fixed from the outside, and the plurality of element formation regions By forming a predetermined element for each, the structure shown in FIG. 41 or 42 is completed.

<Manufacturing method (2)>
49 to 51 are sectional views specifically showing the second step of forming the polysilicon region to be the connection region 80.

  First, as shown in FIG. 46, the SOI layer 3, the silicon oxide film 91, and the silicon nitride film 92 are patterned to perform trench isolation, and then the patterned SOI layer 3, silicon oxide film 91, and silicon nitride are patterned. A sidewall silicon nitride film 93 is formed on the side surface of the film 92.

  Then, as shown in FIG. 49, wet etching is performed on the buried oxide film 2 using the silicon nitride film 92 and the sidewall silicon nitride film 93 as a mask, and the buried oxide film 2 on the back surface of the end portion of the SOI layer 3 is removed. By removing the upper layer portion of the buried oxide film 2 where the SOI layer 3 does not exist above, the hole portion 94 is formed.

  Next, as shown in FIG. 50, an epitaxial growth layer 82 is formed under the sidewall silicon nitride film 93 by epitaxial growth from the exposed back surface of the SOI layer 3.

  Thereafter, as shown in FIG. 51, after a polysilicon layer is deposited on the entire surface, the polysilicon layer is etched back, thereby filling the hole 94 with polysilicon to form a polysilicon region 83 for the connection region 80. . As a result, a connection region 80 composed of the epitaxial growth layer 82 and the polysilicon region 83 can be formed.

  Thereafter, by isolating and isolating a plurality of element formation regions by a method such as embedding an oxide film in a trench, the connection region 80 can be externally fixed, and a predetermined element is formed in each of the plurality of element formation regions. The structure shown in FIG. 41 or 42 is completed.

  The structure of the second aspect is sufficient because the distance between the PN junction portion of the drain region 5 or the source region 6 and the channel formation region 7 and the polysilicon region 83 can be sufficiently increased because of the presence of the epitaxial growth layer 82. Electrical characteristics can be obtained.

<Third Aspect>
FIG. 52 is a cross-sectional view showing a third mode of the sixth embodiment. The structure shown in FIG. 41 is obtained by removing the silicon substrate 1 and the buried oxide film 2 by polishing from the structure shown in FIG. 41 (excluding the connection region 80, the body contact 23, the gate contact 24, and the wiring layers 22 and 25). After the reverse side is reversed, the silicon substrate 90 is bonded to the new back side, and the connection region 86 is formed on the front side. Therefore, an SOI structure including the silicon substrate 90, the interlayer insulating film 4, and the element formation regions (drain region 5, source region 6, channel formation region 7 and the like) is obtained.

  As a result, since the connection region 86 is formed on the surface in the third aspect, the manufacturing process becomes easy.

<Fourth aspect>
FIG. 53 is a cross-sectional view showing a fourth aspect of the sixth embodiment. As shown in the figure, a connection region 87 is formed through the buried oxide film 2. Other configurations are the same as those of the first mode shown in FIG.

  Thus, in the fourth aspect, since the connection region 87 is formed so as to penetrate the buried oxide film 2, the potential can be fixed from the silicon substrate 1 that is the support substrate. At this time, as shown in FIG. 54, the connection region 87 is formed by wet etching through the hole 89 formed in the upper layer portion of the buried oxide film 2 and by dry etching without penetrating the buried oxide film 2 laterally. If the connection region 87 is formed by embedding polysilicon or the like after providing the through-hole with the formed through-hole 88, the connection penetrating the buried oxide film 2 while suppressing the lateral spread when forming the through-hole is formed. Region 87 can be obtained.

<< Embodiment 7 >>
FIG. 63 is a plan view for explaining a design method of the complete isolation region of the SOI structure semiconductor device according to the seventh embodiment of the present invention. As shown in the figure, when a CMOS transistor is formed, a PMOS active region 101 and a PMOS body contact region 102 are selectively provided in a virtual n well region 104, and a P region (not shown) outside the virtual n well region 104 is shown. In general, the NMOS active region 111 and the NMOS body contact region 112 are selectively provided.

  On the other hand, when the NMOS and the PMOS are separated by the composite isolation region shown in the third mode (FIG. 7) of the second embodiment, the virtual n-well region 104 and the partial isolation region substantially coincide, and the partial isolation region A complete separation region is formed continuously.

  The layout configuration of a semiconductor device using such a composite isolation region is highly likely to be able to use accumulated past layout data.

  Therefore, the complete separation region can be automatically generated by executing the design method shown in the following (1) to (3).

  (1) Obtain past data of a CMOS device comprising a PMOS transistor formed in the well region and an NMOS transistor formed outside the well region.

  (2) First and second MOS transistor formation regions (PMOS active region 101, PMOS body contact region 102, NMOS active region 111, NMOS body contact region 112) are set based on past data.

  (3) A complete isolation region 105 is set in a region near the outer periphery of the n-well region 104, with the well region in the past data as a virtual n-well region 104.

  Since the virtual n-well region 104 is usually a region for distinguishing between the NMOS region and the PMOS region, the NMOS transistor and the PMOS transistor are effectively separated by setting a complete isolation region with the virtual n-well region 104 as a reference. can do.

  In the example of FIG. 63, the outer edge of the virtual n-well region 104 is oversized outside with a width W / 2 that is half the full separation width W, and the outer edge is undersized inside with a width W / 2. A complete separation region 105 is set.

  In this way, the complete isolation region can be automatically set based on the complete isolation width W in the vicinity of the outer periphery of the well region of the past data for manufacturing a normal CMOS transistor.

  Further, the partial isolation region 113 is formed continuously to the n well region 104 in a region other than the PMOS active region 101, the PMOS body contact region 102, the n well region 104, the NMOS active region 111, and the NMOS body contact region 112. By setting, it is possible to design a composite separation region including the complete separation region 105 and the partial separation region 113.

<< Embodiment 8 >>
<Latch-up phenomenon>
FIG. 64 is an explanatory diagram for explaining the latch-up phenomenon. As shown in the figure, in the CMOS structure in which the NMOS region 141 is adjacent to the PMOS region 131, the PMOS active region 133 and the n-well region 132 in the PMOS region 131 and the p-well region 142 in the NMOS region 141 are formed. A parasitic bipolar transistor T1 and a parasitic bipolar transistor T2 formed by the NMOS active region 143 and the p-well region 142 in the NMOS region 141 and the n-well region 132 in the PMOS region 131 are formed.

N ⁺ body contact region 135 is connected to the base of parasitic bipolar transistor T 1 through resistance component R 11 of n well region 132. Similarly, p ⁺ body contact region 145 is connected to the base of parasitic bipolar transistor T 2 via resistance component R 12 of p well region 142. N ⁺ body contact region 135 is set to power supply voltage Vcc, and p ⁺ body contact region 145 is set to ground level Vss. Note that gate electrodes 134 and 144 are formed in the central portions of the PMOS active region 133 and the NMOS active region 143, respectively.

  By forming the parasitic thyristor structure by these parasitic bipolar transistors T1 and T2, when the parasitic thyristor is turned on due to noise, a latch-up phenomenon occurs in which current continues to flow from the power supply voltage Vcc to the ground level Vss.

<First aspect>
In general, noise that causes a latch-up phenomenon often comes from an input / output terminal. Therefore, as shown in FIG. 65, a structure in which a region near the boundary between the input / output NMOS (transistor formation) region 106 and the input / output PMOS (transistor formation) region 116 is completely separated by a complete separation region 114 is desirable. The input / output NMOS region 106 and the input / output PMOS region 116 are partially separated from the peripheral region by a partial isolation region 107 and a partial isolation region 117, respectively.

  The input / output area means an area mainly forming an input / output buffer and a protection circuit. FIG. 66 is a circuit diagram showing an example of an input circuit. As shown in the figure, the external input terminal P1 that receives the input signal IN is connected to the input portion of the input buffer 122 via resistors R1 and R2, and the output portion of the input buffer 122 is connected to the internal input terminal P2, An internal signal S0 is output from the input terminal P2.

  The input protection circuit 121 includes a PMOS transistor Q1 and an NMOS transistor Q2. The PMOS transistor Q1 has a source and a gate connected to the power supply voltage Vcc, and a drain connected to a node N1 between the resistors R1 and R2. The source and gate of the NMOS transistor Q2 are grounded, and the drain is connected to the node N1.

  The input buffer 122 forms a CMOS inverter by the PMOS transistor Q11 and the NMOS transistor Q12, and the gates of the PMOS transistor Q11 and the NMOS transistor Q12 serve as an input section and the drain serves as an output section.

  In this circuit example, PMOS transistors Q 1 and Q 11 are formed in the input PMOS region 118, and NMOS transistors Q 2 and Q 12 are formed in the input NMOS region 108.

  FIG. 67 is a circuit diagram showing an example of an output circuit. As shown in the figure, the internal input terminal P3 that receives the internal signal S1 is connected to the input section of the output buffer 123, and a signal obtained from the output section of the output buffer 123 is output as an output signal OUT through the external output terminal P4. Is done.

  The output buffer 123 constitutes a CMOS inverter with the PMOS transistor Q13 and the NMOS transistor Q14, and the gates of the PMOS transistor Q13 and the NMOS transistor Q14 serve as an input section and the drain serves as an output section.

  The output protection circuit 124 includes a PMOS transistor Q3 and an NMOS transistor Q4. The source and gate of the PMOS transistor Q3 are connected to the power supply voltage Vcc, and the drain is connected to the external output terminal P4. The source and gate of the NMOS transistor Q4 are grounded, and the drain is connected to the external output terminal P4.

  In this circuit example, PMOS transistors Q3 and Q13 are formed in the output PMOS region 119, and NMOS transistors Q4 and Q14 are formed in the output NMOS region 109.

  As described above, in the first mode of the eighth embodiment, the complete isolation region 114 is formed at least in the region near the boundary between the input / output NMOS region 106 and the input / output PMOS region 116 where a latch-up phenomenon is likely to occur, and the complete separation is achieved. Thus, the latch-up phenomenon does not occur.

  In the first mode of the eighth embodiment, the complete isolation region 114 is not provided in the entire region between the NMOS region and the PMOS region, but only in the region near the boundary between the input / output NMOS region and the input / output PMOS region. By providing this, an increase in the circuit formation area can be minimized while effectively suppressing the latch-up phenomenon.

<Second aspect>
In addition, the complete separation between the input / output NMOS region 106 and the input / output PMOS region 116 is provided only in the region near the boundary between the input / output NMOS region 106 and the input / output PMOS region 116 as shown in FIG. As shown in the second embodiment, the complete isolation region 115 may be formed so as to completely surround the input / output NMOS region 106 and the input / output PMOS region 116.

  Further, in addition to the input / output NMOS region and the input / output PMOS region, it is conceivable to provide a complete isolation region between specific circuits such as between an analog circuit and a digital circuit.

<Third Aspect>
FIG. 69 is an explanatory view showing the third mode of the eighth embodiment. As shown in the figure, the input / output region (input / output PMOS region 116) is added between the NMOS region (input / output NMOS region 106, internal NMOS region 180) and PMOS region (input / output PMOS region 116, internal PMOS region 190). , The internal circuit region (internal NMOS region 180) is also completely separated by the complete isolation region 110.

  According to the third aspect, in addition to the effects of the first and second aspects, the influence of the input / output area that is easily affected by noise can be completely blocked from the internal circuit area.

<< Ninth Embodiment >>
<First aspect>
70 is a plan view showing a planar structure of a first mode of a semiconductor device having an SOI structure according to the ninth embodiment of the present invention, and FIG. 71 is a sectional view showing a sectional structure taken along the line AA of FIG. As shown in these drawings, an NMOS (transistor formation) region 126 and a PMOS (transistor formation) region 136 are provided adjacent to each other. An NMOS active region 128 having a plurality of gate electrodes 129 and a p ⁺ body region 130 are formed in the NMOS region 126, and the periphery of the NMOS active region 128 is surrounded by a partial isolation region 127.

Meanwhile, a PMOS active region 138 having a plurality of gate electrodes 139 and an n ⁺ body region 140 are formed in the PMOS region 136, and the periphery of the PMOS active region 138 is surrounded by the partial isolation region 137 and the complete isolation region 120. The complete isolation region 120 is provided at a portion where the gate electrode 139 protrudes from the PMOS active region 138 in the PMOS region 136 in the vicinity of the boundary between the NMOS region 126 and the PMOS region 136.

  Therefore, as shown in FIG. 71, the region near the boundary between the NMOS region 126 and the PMOS region 136 is separated from the periphery by the partial isolation region 127 formed by the oxide film 54 and the well region 169. The PMOS region 136 is separated from the surroundings by the complete isolation region 120 formed only by the oxide film 54.

  As described above, since the NMOS region 126 is not formed with a complete isolation region at all and the partial isolation region 127 is provided, the substrate potential of the NMOS transistor can be fixed without being insufficient through the well region 169 under the oxide film 54. Thus, the substrate floating effect of the NMOS transistor having a severe substrate floating effect can be effectively suppressed.

  Further, a PMOS transistor having a milder substrate floating effect than an NMOS transistor has no significant adverse effect even if a complete isolation region is formed in a part of the periphery, and the NMOS region 126 and the PMOS region 136 are insulated from each other by the complete isolation region 120. This arrangement is improved in area efficiency while being separated, and is effective when the layout has no margin.

<Second aspect>
72 is a plan view showing a planar structure of a second mode of the SOI structure semiconductor device according to the ninth embodiment of the present invention, and FIG. 73 is a sectional view showing a BB sectional structure of FIG. As shown in these drawings, an NMOS region 126 formed in a p ⁻ type well region 169 and a PMOS region 136 formed in an n ⁻ type well region 179 are provided adjacent to each other.

  An NMOS active region 128 having a plurality of gate electrodes 129 is formed in the NMOS region 126, and most of the periphery of the NMOS active region 128 is surrounded by a complete isolation region 125. Only the end of the gate electrode 129 on one side of the gate electrode 129 (opposite side of the PMOS region 136) is separated from the surroundings by the partial isolation region 127.

As shown in FIG. 73, a partial isolation region 127 is constituted by the oxide film 54 and the well region 169 formed below the oxide film 54. Note that the formation width of the partial isolation region 127 may be larger than the formation width of the gate electrode 129 (left side in FIG. 73) or smaller (right side in FIG. 73). A p ⁺ body region 130 is provided in the well region 169 near one side of the gate electrode 129.

Meanwhile, a PMOS active region 138 having a plurality of gate electrodes 139 is formed in the PMOS region 136, and most of the periphery of the PMOS active region 138 is surrounded by a complete isolation region 125. As with the NMOS region 126, only the end portion of the gate electrode 139 on one side of the gate electrode 139 (opposite side of the NMOS region 126) is separated from the surroundings by the partial isolation region 137. An n ⁺ body region 140 is provided in the well region 179 near one side of the gate electrode 139.

  Thus, in the second mode of the ninth embodiment, the end portion of the gate electrode is separated by the partial isolation region so that the channel formation region existing under the gate electrode and the well region of the partial isolation region are in contact with each other. By forming, the substrate potential of each transistor formation region can be fixed.

  The reason why most of the periphery of the NMOS region 126 and the PMOS region 136 is surrounded by the complete isolation region 125 is to reduce the PN junction area and to block the path where the latch-up phenomenon occurs.

<< Embodiment 10 >>
<First aspect>
FIG. 74 is a plan view showing the configuration of the first aspect of the SOI structure semiconductor device according to the tenth embodiment of the present invention. As shown in the figure, a plurality of gate electrodes 129 are formed in the NMOS active region 128, and a partial isolation region 127 is provided surrounding the NMOS active region 128. Further, a p ⁺ body region 146 is provided surrounding the partial isolation region 127. FIG. 101 is a cross-sectional view showing the EE cross-sectional structure of FIG.

  As shown in FIG. 101, the partial isolation region 127 is composed of an oxide film 54 and a well region 169, and this well region 169 is formed in contact with a channel formation region formed in the NMOS active region 128. The structure is susceptible to noise and latch-up.

However, in the first mode of the tenth embodiment, since p ⁺ body region 146 is formed surrounding partial isolation region 127, substrate fixing such as fixing p ⁺ body region 146 to the ground level is performed. Thus, the influence from other circuit portions can be suppressed, the substrate potential can be stabilized, and the resistance to noise and latch-up can be greatly improved.

The first aspect having such a configuration is suitable for a circuit block of a noise source, a circuit block that wants to block noise from the outside, and the like. In the case of the PMOS active region, the same effect can be obtained if the periphery of the partial isolation region is surrounded by an n ⁺ body region.

<Second aspect>
FIG. 75 is a plan view showing the configuration of the second mode of the SOI structure semiconductor device according to the tenth embodiment of the present invention. As shown in the figure, an input / output NMOS region 151 and an input / output PMOS region 152 are formed adjacent to each other.

In the input / output NMOS region 151, a plurality of gate electrodes 129 are formed in the NMOS active region 128, and a partial isolation region 127A is provided surrounding the NMOS active region 128. Further, a p ⁺ body region 146 is provided surrounding the periphery of the partial isolation region 127A. A partial isolation region 127 ^</ b ^{> B} is provided surrounding the p ⁺ body region 146.

In the input / output PMOS region 152, a plurality of gate electrodes 139 are formed in the PMOS active region 138, and the portion surrounding the periphery of the PMOS active region 138 is provided with a separation region 137A. Further, an n ⁺ body region 147 is provided so as to surround the partial isolation region 137A. A partial isolation region 137B is provided surrounding the n ⁺ body region 147.

  In general, since input / output circuits are often affected by surges and noise from outside the chip, it is particularly important to increase the latch-up phenomenon and noise resistance.

In the second mode of the tenth embodiment, the influence of surge is obtained by surrounding the partial isolation regions 127A and 137A of the input / output NMOS region 151 and the input / output PMOS region 152 with the p ⁺ body region 146 and the n ⁺ body region 147, respectively. Thus, the latch-up phenomenon that occurs when the potential of the well region rises can be suppressed.

  In the second aspect, the entire NMOS and PMOS active regions are covered with the body region. However, if at least the body region is provided in the vicinity of the boundary between the input / output NMOS region 151 and the input / output PMOS region 152, The latch-up phenomenon and noise resistance can be increased to some extent.

<< Embodiment 11 >>
<First aspect>
FIG. 76 is a plan view showing the configuration of the first mode of the SOI structure semiconductor device according to the eleventh embodiment of the present invention.

  As shown in the figure, a plurality of gate electrodes 129 are provided in the NMOS active region 128, a floating partial isolation region 149 is formed surrounding the NMOS active region 128, and a periphery of the floating partial isolation region 149 is surrounded. A complete isolation region 148 is formed.

  Floating partial isolation region 149 is formed in a two-layer structure of an oxide film and a well region as in the relationship between partial oxide film 31 and well region 11 in FIG. 55, for example, but the well region is not fixed in potential. , Always floating. Even if the well region of the floating partial isolation region 149 is in a floating state, carriers generated by impact ionization flow into the well region of the floating partial isolation region 149, so that potential increase can be minimized. In addition, since the electric charge generated by the cosmic rays can be dispersed in the well region of the floating partial isolation region 149, the soft error resistance can be improved.

  The configuration of the first aspect of the eleventh embodiment in which the floating partial isolation region 149 is provided in this way is effective when it is difficult to contact the body region with a high-density circuit such as SRAM.

  Although it is desirable to provide the complete isolation region 148 from the viewpoint of improving the latch-up resistance, it is not always necessary.

<Second aspect>
FIG. 77 is a plan view showing the configuration of the second mode of the SOI structure semiconductor device according to the eleventh embodiment of the present invention.

As shown in the figure, a floating p ⁺ body region 150 is provided in the floating partial isolation region 149. Other configurations are the same as those of the first mode shown in FIG.

The floating p ⁺ body region 150 is always in a floating state without being fixed in potential. Therefore, the well region of the floating partial isolation region 149 is also in a floating state.

  As in the second mode, even if the well region of the floating partial isolation region 149 is in a floating state, as in the first mode, the potential increase can be minimized and the soft error resistance can be improved. .

Further, the second aspect has an effect of increasing the suppression effect of the substrate floating effect as compared with the first aspect because the recombination of carriers is promoted by the presence of the floating p ⁺ body region 150.

<< Embodiment 12 >>
<First aspect>
78 is a plan view showing the configuration of the first mode of the SOI structure semiconductor device according to the twelfth embodiment of the present invention, and FIG. 79 is a CC cross-sectional view thereof.

As shown in these drawings, a p ⁺ -type body region 156 is provided adjacent to the source region 154 of the NMOS transistor including the drain region 153, the source region 154, and the gate electrode 155, and the source region 154 and the body region 156 are provided. Are both electrically connected to the aluminum wiring layer 160 by a contact 158.

  The drain region 153 is electrically connected to the aluminum wiring layer 159 through a contact 157, and a partial isolation region 161 is formed surrounding the drain region 153, the source region 154, and the body region 156.

As shown in FIG. 79, the partial isolation region 161 includes an oxide film 162 and a p ⁻ type well region 177. Further, a silicide layer 163 is formed over the upper surfaces of the source region 154 and the body region 156 to facilitate common connection between the source region 154 and the body region 156, and a contact 158 is formed on the silicide layer 163. Note that the region of the SOI layer 3 below the gate oxide film 178 of the gate electrode 155 becomes the channel formation region 170.

  In such a configuration, the potential of the well region 177 is fixed to the same potential as the source region 154 by fixing the source region 154 and the body region 156 to the ground level by the aluminum wiring layer 160, and the well region 177 is connected via the well region 177. The potential of the channel formation region 170 can be fixed.

  In the first aspect, as shown in FIGS. 78 and 79, the degree of integration can be improved because the source region 154 and the body region 156 can be formed adjacent to each other.

  The PMOS transistor can be similarly configured. However, the potential of the source region and the body region must be fixed at the power supply level.

<Second aspect>
FIG. 80 is a plan view showing the configuration of the second mode of the SOI structure semiconductor device according to the twelfth embodiment of the present invention, and FIG. 81 is a DD cross-sectional view thereof.

As shown in these drawings, a p ⁺ -type body region 164 is provided adjacent to the source region 154, and the source region 154 and the body region 164 are both electrically connected to the aluminum wiring layer 166 and the contact 165. At this time, the contact 165 is formed to cover the source region 154 and the body region 164. A partial isolation region 161 is formed surrounding the drain region 153, the source region 154, and the body region 164.

  As shown in FIG. 81, a silicide layer 167 is formed on the source region 154, and a contact 165 is formed on a part of the silicide layer 167 and on the upper body region 164. Other configurations are the same as those of the first mode shown in FIGS. 78 and 79.

  In such a configuration, the source region 154 and the body region 164 are fixed to the ground level by the aluminum wiring layer 166, thereby fixing the potential of the well region 177 to the same potential as the source region 154, and via the well region 177. The potential of the channel formation region 170 can be fixed.

  In the second mode, as shown in FIGS. 80 and 81, the degree of integration can be improved because the source region 154 and the body region 164 can be formed adjacent to each other.

<Third Aspect>
As shown in FIG. 82, the body region 164 is provided in a part of the portion that is adjacent to the partial isolation region 161 and becomes the normal source region 154, and the contact 165 is provided on the source region 154. The effect of.

  Furthermore, in the third mode, as shown in FIG. 82, the body region 164 can be formed to completely overlap in the region to be the source region 154, so that the degree of integration can be improved more than the first and second modes. Can do.

<< Thirteenth Embodiment >>
FIG. 83 is a cross sectional view showing a cross sectional structure of an SOI structure semiconductor device according to the thirteenth embodiment of the present invention. As shown in the figure, the partial isolation region for isolating the n ⁺ active regions 171 and 172 is composed of an oxide film 173 and well regions (p regions 174 and 175 and p ⁻ region 176) below the oxide film 173. Yes. As the n ⁺ active regions 171 and 172, for example, source and drain regions of transistors can be considered. The p regions 174 and 175 become peripheral regions of the well region adjacent to the n ⁺ active regions 171 and 172, and the p ⁻ region 176 It becomes the central region of the well region.

As described above, in the thirteenth embodiment, the impurity concentration of the p regions 174 and 175 adjacent to the n ⁺ active regions 171 and 172 is set higher than that of the p ⁻ region 176, thereby improving the punch-through resistance in the partial separation. ing.

As a manufacturing method, after forming a p ⁻ well region under the oxide film 173, boron and BF ₂ are implanted so as to reach the well region by oblique rotation implantation, as shown in FIG. 175 can be formed.

For example, boron (B) may be implanted at a dose of 4 × 10 ¹³ / cm ² at an implantation energy of 20 keV and an implantation angle of 45 degrees. Further, even when the implantation energy of B or BF ₂ is low (for example, the implantation energy of BF ₂ is 20 keV), the diffusion around the n ⁺ active regions 171 and 172 is caused by accelerated diffusion due to lattice defects generated during n ⁺ impurity implantation. It is also possible to provide the p regions 174 and 175 by forming a mold region.

<< Embodiment 14 >>
<First aspect>
FIG. 84 is a cross sectional view showing a cross sectional structure of a first mode of a semiconductor device having an SOI structure according to the fourteenth embodiment of the present invention. As shown in the figure, the NMOS is formed in the SOI layer 3 on the silicon substrate 1 and the buried oxide film 2 and includes a drain region 183, a source region 184, a gate oxide film 185, a gate electrode 186, and a channel formation region 187. The transistor is partially isolated by a partial isolation region composed of an oxide film 181 and a well region 182.

  At this time, as shown on the right side of FIG. 84, when the impurity concentration profile of the drain region 183 and the source region 184 and the impurity concentration profile of the well region 182 are compared, the impurity concentration peak of the well region 182 becomes the drain region 183 and The depth from the surface of the SOI layer 3 is set to be deeper than the impurity concentration peak of the source region 184.

  In the semiconductor device according to the first aspect having such a configuration, the drain region 183 and the source region 184 can be formed with thin impurity profiles in the PN junction portion between the drain region 183 and the source region 184 and the well region 182. PN junction breakdown voltage between the well region 182 and the well region 182 can be increased.

<Second aspect>
FIG. 85 is a cross sectional view showing a cross sectional structure of the second mode of the SOI structure semiconductor device according to the fourteenth embodiment of the present invention. As shown in the figure, it has the same structure as the first embodiment.

  At this time, as shown on the right side of FIG. 85, when the impurity profile of the well region 182 and the impurity profile of the channel formation region 187 are compared, the impurity peak of the well region 182 is higher than the impurity peak of the channel formation region 187. Set so that the depth from the surface is shallow. For example, if the well region 182 and the channel formation region 187 are simultaneously formed by implanting impurities with the upper surface of the oxide film 181 for partial isolation being above the surface of the SOI layer 3, the channel formation region 187 is automatically formed. The impurity profile becomes a peak at a position deeper than the well region 182.

  In the semiconductor device of the second aspect having such a configuration, the impurity concentration on the surface of the channel formation region 187 can be sufficiently lowered so that the threshold voltage does not become higher than a desired value.

<< Embodiment 15 >>
<First aspect>
FIG. 86 is a cross sectional view showing the structure of the first aspect of the SOI structure semiconductor device according to the fifteenth embodiment of the present invention. As shown in the drawing, n ⁺ active regions 191-193 in the SOI layer 3 on the silicon substrate 1 and the buried oxide film 2 is selectively formed, between n ⁺ active regions 191 and 192 separated by a complete isolation region 209 The n ⁺ active regions 192 and 193 are separated by a partial isolation region 219.

Complete isolation region 209 includes an oxide film 188 and well regions (p ⁻ well regions 194 and 195 and p well regions 196 and 197) formed under oxide film 188. The oxide film 188 can completely separate the n ⁺ active regions 191 and 192 by forming the complete insulating portion 229 in the center through the SOI layer 3. On the other hand, partial isolation region 219 is constituted by oxide film 189 and p ⁻ well region 198 below oxide film 189.

  In the well region under the oxide film 188, the impurity concentration of the p well regions 196 and 197 formed adjacent to the complete insulating portion 229 is set higher than those of the other regions 194 and 195.

  There is a high possibility that in the region near the completely insulating portion 229, electric charges are generated due to stress applied to the SOI layer 3 or that a punch-through state is likely to occur due to segregation of impurities to the oxide film.

  However, in the first mode of the fifteenth embodiment, since the p-well regions 196 and 197 having a relatively high impurity concentration are provided in the vicinity of the complete insulating portion 229, it is possible to suppress the possibility of the occurrence of the above-described problem. it can.

<Second aspect>
FIG. 87 is a plan view showing the structure of the second mode of the SOI structure semiconductor device according to the fifteenth embodiment of the present invention. As shown in the figure, the periphery of the NMOS transistor composed of the drain region 201, the source region 202, and the gate electrode 203 is surrounded by the partial isolation regions 204 to 207, and further, the periphery of the partial isolation regions 204 to 207 is surrounded by the complete isolation region 208. ing.

In the partial isolation regions 204 to 207, p-well regions 206 and 207 having a relatively high impurity concentration are formed in a region near the gate electrode 203, and other regions in contact with the drain region 201 and the source region 202 have a low impurity concentration. p ^— well regions 204 and 205 are formed.

In the second mode of the fifteenth embodiment having such a configuration, the p ^- well regions 204 and 205 can reduce the PN junction capacitance, and the p-well regions 206 and 207 can prevent punch-through.

<< Embodiment 16 >>
<First aspect>
FIG. 88 is a cross sectional view showing the structure of the first aspect of the SOI structure semiconductor device according to the sixteenth embodiment of the present invention. As shown in the figure, an oxide film 211 for a partial isolation region is formed in the SOI layer 3 on the silicon substrate 1 and the buried oxide film 2.

  In optimizing the separation shape, it is necessary to balance both the reduction of the separation width and the relaxation of stress applied to the SOI layer. In the shape of the oxide film for the partial isolation region, in order to reduce the isolation width, it is preferable that the curvature of the corner is as tight as possible (the radius of curvature is small), and that the surface in the depth direction is close to perpendicular. Conversely, in order to relieve stress, it is better to loosen the curvature of the corner (increase the curvature radius). The bird's beak is preferably made as small as possible to ensure an effective active region width.

  From such a point of view, the cross-sectional shape of the oxide film 211 of the first embodiment has a tight curvature of the shape FA (convex portion) of the bird's beak portion which is the corner portion of the surface in order to reduce the separation width, and stress is applied. In order to relax, the curvature of the shape FC at the corner of the bottom is set to be loose. In order to reduce the separation width, it is desirable that at least part of the shape FB of the surface in the depth direction be close to the vertical.

<Second aspect>
FIG. 89 is a cross sectional view showing the structure of the second mode of the SOI structure semiconductor device according to the sixteenth embodiment of the present invention. As shown in the drawing, an oxide film 212 for a complete isolation region is formed in the SOI layer 3 on the silicon substrate 1 and the buried oxide film 2.

  From the same viewpoint as the first embodiment, the second embodiment also has a cross-sectional shape of the oxide film 212 set to the same shape FA, FB, FC as that of the first embodiment, and is further separated from the completely insulated portion at the bottom. The separation width is reduced by setting the curvature of the shape FD of the step with the portion to be tighter than the shape FC.

<< Embodiment 17 >>
<First aspect>
FIG. 90 is a cross sectional view showing the structure of the first mode of the SOI structure semiconductor device according to the seventeenth embodiment of the present invention. The first mode implements the circuit shown in FIG. As shown in FIG. 91, the circuit configuration in which the gate electrode of the analog circuit transistor Q21 and one electrode of the analog circuit transistor Q22 are connected via a spiral inductor 199 is the circuit configuration of the first aspect.

  As shown in FIG. 90, the buried oxide film 2 is formed on the high resistance silicon substrate 200, and the analog circuit transistors Q21 and Q22 are formed in the SOI layer 3 on the buried oxide film 2.

  The analog circuit transistors Q21 and Q22 are both composed of a drain region 5, a source region 6, a channel formation region 7, a gate oxide film 8 and a gate electrode 9, and the analog circuit transistors Q21 and Q22 have a relatively large formation area. The analog circuit transistors Q21 and Q22 and other peripheral portions are completely separated by an oxide film 33 having a relatively small formation area. A well region 29 is formed in a part below the oxide films 210 and 33.

  An interlayer insulating film 4 is formed on the entire surface of the SOI layer 3 including the analog circuit transistors Q21 and Q22, and a first wiring layer 221 is selectively formed on the interlayer insulating film 4. Part of the first wiring layer 221 is electrically connected to the drain region 5 and the source region 6 of each of the analog circuit transistors Q21 and Q22 through the contact hole 244.

  An interlayer insulating film 220 is formed on the entire surface of the interlayer insulating film 4 including the first wiring layer 221, a second wiring 222 is selectively formed on the interlayer insulating film 220, and a spiral inductor is formed by part of the second wiring 222. 199 is formed. A part of the second wiring 222 is electrically connected to the corresponding first wiring layer 221 (221A) through the contact hole 254. The gate electrode 9 of the analog circuit transistor Q21 is connected to the first wiring layer 221A through a contact hole formed in the interlayer insulating film 4 in a region not shown.

  In the first aspect having such a configuration, a parasitic capacitance associated with the spiral inductor 199 is reduced by providing a complete insulating region including the oxide film 210 and the well region 29 below the spiral inductor 199. That is, when the isolation region under the spiral inductor 199 is formed by a partial isolation region between the oxide film and the well region, parasitic capacitance is generated between the well region and the spiral inductor 199, and the figure of merit Q (energy loss and store) The problem that the desired inductance performance cannot be obtained due to the occurrence of energy loss or the like is solved.

  In the first aspect, the high-resistance silicon substrate 200 is used as the base substrate of the SOI substrate, thereby reducing power loss and parasitic capacitance through eddy current and capacitance, and improving the figure of merit Q. be able to.

  Further, since the analog circuit dislikes external noise, the periphery of the analog circuit transistors Q21 and Q22 is completely separated by the oxide film 210 or the oxide film 33, and is electrically disconnected from the outside to improve performance.

  Although not shown in FIG. 90, if a partial isolation region is formed below the pad portion, a large parasitic capacitance is likely to occur as in the spiral inductor, and an electric loss is likely to occur. Therefore, the spiral inductor 199 is also formed below the pad portion. It is desirable to provide a complete separation region as well as below.

<Second aspect>
FIG. 92 is a cross sectional view showing the structure of the second mode of the SOI structure semiconductor device according to the seventeenth embodiment of the present invention. The second mode realizes the circuit shown in FIG. 91 as in the first mode.

  As shown in FIG. 92, the analog circuit transistors Q21 and Q22 are partially separated by an oxide film 218 having a relatively large area and a high resistance region 223 and a well region 224 below the oxide film 218, and the analog circuit transistors Q21 and Q22. And the other peripheral portion are partially separated by an oxide film 31 having a relatively small formation area and a well region 11 (12) therebelow.

  Most of the region under the oxide film 218 is formed by the high resistance region 223, and the well region 224 is formed only in a part of the peripheral portion. Other configurations are the same as those of the first mode shown in FIG.

  As in the second aspect, while performing partial isolation, most of the partial isolation region under the spiral inductor 199 is constituted by the oxide film 218 and the high resistance region 223, so that the parasitic capacitance associated with the spiral inductor 199 is reduced. It can be suppressed sufficiently.

As a method for forming the high resistance region 223, it is conceivable to manufacture the high resistance region 223 without introducing impurities. Alternatively, the high resistance region 223 can be formed by implanting silicon at a high concentration of, for example, about 1 × 10 ²⁰ / cm ² to make the lower region of the oxide film amorphous, and then polysilicon by heat treatment.

<< Embodiment 18 >>
FIG. 93 is a plan view showing the structure of the SOI structure semiconductor device according to the eighteenth embodiment of the present invention. As shown in the figure, the DT-MOS regions 225 and 226 are completely separated by a complete separation region 240. The DT-MOS is a MOS transistor that sets the gate electrode and the body region (channel formation region) to the same potential.

The DT-MOS regions 225 and 226 are each provided with an n ⁺ NMOS active region 232 and a p ⁺ body region 234 in a p-type well region 231 (partial isolation region 230). The NMOS active region 232 is connected via a contact 238. The gate electrode 233 provided at the center of the NMOS active region 232 is electrically connected to the wiring layer 237 via a contact 235 (gate contact), and the body region 234 is connected to the contact 236 (body It is electrically connected to the wiring layer 237 via a contact).

  The gate electrode 233 and the body region 234 are set to the same potential by the wiring layer 237, and the threshold voltage in the on state is lowered to improve the operation speed.

  Thus, in the eighteenth embodiment, the potential of the channel formation region can be fixed via the body region 234 and the well region 231, and the DT-MOS regions 225 and 226 are completely separated by the complete isolation region 240. Therefore, a DT-MOS with good performance can be formed relatively easily. The body contact and the gate contact may be simultaneously connected by a shared contact.

<< Embodiment 19 >>
94 is a cross sectional view showing the structure of an SOI structure semiconductor device according to the nineteenth embodiment of the present invention.

  As shown in the figure, in a transistor formation region 227 for forming a transistor having a relatively narrow gate width W, a MOS transistor including a drain region 245, a source region 246, a channel formation region 247, a gate oxide film 248, and a gate electrode 249 is provided. The MOS transistors are partially separated by the partial oxide film 31 and the well region 11 (12), and the surroundings are completely separated by the complete oxide film 32.

  An interlayer insulating film 4 is formed on the entire surface of the SOI layer 3 including the MOS transistor, and a wiring layer 242 is selectively formed on the interlayer insulating film 4. The wiring layer 242 is electrically connected to the drain region 245 and the source region 246 through the contact hole 241.

  On the other hand, in the transistor formation region 228 that forms a transistor having a relatively wide gate width W, a MOS transistor including a drain region 255, a source region 256, a channel formation region 257, a gate oxide film 258, and a gate electrode 259 is formed. The MOS transistors are partially separated by the partial oxide film 31 and the well region 11 (12), and the surroundings are completely separated by the complete oxide film 32.

  An interlayer insulating film 4 is formed on the entire surface of the SOI layer 3 including the MOS transistor, and a wiring layer 252 is selectively formed on the interlayer insulating film 4. The wiring layer 252 is electrically connected to the drain region 255 and the source region 256 through the contact hole 251.

  The formation depth of the drain region 245 and the source region 246 formed in the transistor formation region 227 with a narrow gate width W is set to a depth at which at least a part of the depletion layer 243 from the drain / source reaches the buried oxide film 2 in the build-in state. Therefore, the junction capacitance is reduced. The formation depth of the drain region 245 and the source region 246 may be set to a depth reaching the buried oxide film 2.

  On the other hand, the formation depth of the drain region 255 and the source region 256 formed in the transistor formation region 228 having a wide gate width W is set so that the depletion layer 253 from the drain / source in the built-in state does not reach the buried oxide film 2. Thus, the potential of the channel formation region 257 can be surely fixed.

  Note that the two types of drain / source regions formed in the transistor formation regions 227 and 228 change the implantation energy of impurities at the time of forming the source / drain or change the implantation amount of NUDC (Non Uniformly Doped Channel). Can be realized.

  In addition, after a source / drain region having a depth that does not allow the depletion layer to reach the buried oxide film 2 in the built-in state is formed, the formation depth is increased only with respect to the source / drain region on the transistor formation region 227 side. As described above, this can also be realized by performing additional implantation of impurities again.

<< Embodiment 20 >>
<First aspect>
FIG. 95 is a cross sectional view showing the structure of the first aspect of the SOI structure semiconductor device according to the twentieth embodiment of the present invention. As shown in the figure, n ⁺ regions 261 and 262 are selectively provided in the SOI layer 3 on the silicon substrate 1 and the buried oxide film 2, and the p ⁻ region 263 and the oxide film 264 are interposed between the n ⁺ regions 261 and 262. A partial separation region is provided. A field transistor including n ⁺ regions 261 and 262, a p ⁻ region 263, and an oxide film 264 is formed. The field transistor has a structure in which an oxide film is provided in place of the gate portion (gate oxide film, gate electrode) of the MOS transistor.

As described above, in the first embodiment, a field transistor is configured using a partial isolation region structure including the p ⁻ region 263 and the oxide film 264. Field transistors can be applied to protection circuit elements and the like.

  Since the structure of the gate portion of the field transistor of the twentieth embodiment is basically the same as that of the partial isolation region, the field transistor can be formed relatively easily by forming the gate portion simultaneously with the partial isolation region. it can.

  FIG. 96 is a circuit diagram showing an example of using field transistors in the input section of the circuit. As shown in the figure, one electrode of the field transistor Q31 is connected to the external input terminal P1, and the other electrode is grounded. A field transistor Q33 is provided between the power source and the ground. The other configuration is the same as the circuit configuration shown in FIG. 66, and a description thereof will be omitted.

  Thus, the field transistor Q31 provides a protection circuit between the external input terminal P1 and the ground level, and the field transistor Q33 provides a parasitic diode path between the power supply and the ground level.

  FIG. 97 is a circuit diagram showing an example of using field transistors in the output section of the circuit. As shown in the figure, one electrode of the field transistor Q32 is connected to the external output terminal P4, and the other electrode is grounded. A field transistor Q34 is provided between the power source and the ground. Other configurations are the same as the circuit configuration shown in FIG.

  Thus, the field transistor Q32 provides a protection between the external output terminal P4 and the ground level, and the field transistor Q34 provides a parasitic diode path between the power supply and the ground level.

  As shown in FIG. 95, the field transistor is preferably an NMOS-like structure because of its high discharge capability, but a PMOS-like structure may also be used. In this case, it is necessary to provide a field transistor between the power supply and the external input terminal P1 instead of the field transistors Q31 and Q32.

<Second aspect>
FIG. 98 is a cross sectional view showing the structure of the second aspect of the SOI structure semiconductor device according to the twentieth embodiment of the present invention. As shown in the figure, the periphery of the n ⁺ regions 261 and 262 is completely separated by a complete oxide film 265. The other configuration is the same as that of the first mode shown in FIG.

  In the second aspect, since the entire field transistor is surrounded by the complete oxide film 265, a great effect can be expected in noise blocking and the like. Further, when the field transistor is used as a protection circuit, it is possible to reliably prevent a parasitic path of current to other components.

<Third Aspect>
FIG. 99 is a plan view showing the configuration of the third mode of the SOI structure semiconductor device according to the twentieth embodiment of the present invention. A plurality of n ⁺ regions 261 and 262 are alternately arranged, the n ⁺ regions 261 and 262 are partially separated by the oxide film 264 and the p ⁻ region 263, and the entire periphery is completely separated by the complete oxide film 265.

The plurality of n ⁺ regions 261 are commonly connected to the connection terminal P11, and the plurality of n ⁺ regions 262 are commonly connected to the connection terminal P12. As described above, the discharge capacity can be increased by electrically connecting the plurality of n ⁺ regions 261 and 262 arranged in a comb structure in parallel.

<Others>
The source / drain regions (n ⁺ regions 261 and 262) of the field transistor may be formed to a depth at which the depletion layer reaches the buried oxide film 2 without reaching the buried oxide film 2.

<< Supplementary >>
In order to make the source / drain region reach the buried oxide film, the impurity / deep region is formed by increasing the impurity implantation depth sufficiently as a normal method, or the impurity peak having a deep impurity peak after the impurity implantation having a shallow impurity peak. Injection may be performed.

  However, in the above-described method, the impurity distribution has a peak at the shallow portion of the source / drain region as in the first embodiment of the fourteenth embodiment shown in FIG. Can not have.

  Therefore, by applying a method such as ion implantation with the implantation angle sufficiently close to 0 degrees and implantation energy sufficiently small, the impurity peak is located at a relatively shallow position of the SOI layer 3 as indicated by L1 in FIG. In addition, the tail profile due to the channeling phenomenon can be distributed so that the impurities penetrate the SOI layer 3 and reach the buried oxide film 2 as in the impurity distribution indicated by L2 in FIG.

1 is a cross-sectional view showing a first aspect of an SOI structure semiconductor device according to a first embodiment of the present invention; 2 is a cross-sectional view showing a first aspect of the first embodiment. FIG. FIG. 3 is a plan view of the first aspect of the first embodiment. FIG. 3 is a cross-sectional view showing a structure of a second aspect of the first embodiment. FIG. 6 is a cross-sectional view showing a first aspect of the second embodiment. FIG. 6 is a cross-sectional view showing a second aspect of the second embodiment. FIG. 10 is a cross-sectional view showing a third aspect of the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 1) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 1) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 1) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 1) in the second embodiment. It is sectional drawing which shows a high concentration well area | region formation process. It is sectional drawing which shows a high concentration well area | region formation process. FIG. 10 is a cross-sectional view showing an element isolation step (No. 2) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 2) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 2) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 2) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 2) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 3) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 3) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 3) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 3) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 4) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 4) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 4) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 4) in the second embodiment. FIG. 11 is a cross-sectional view showing an element isolation step (No. 4) in the second embodiment. FIG. 10 is a cross-sectional view showing a first aspect of the third embodiment. FIG. 10 is a cross-sectional view showing a second aspect of the third embodiment. FIG. 10 is a cross-sectional view showing an SOI structure of a fourth embodiment. FIG. 10 is a cross-sectional view showing an SOI structure of a fourth embodiment. FIG. 10 is a cross-sectional view showing another SOI structure of the fourth embodiment. FIG. 10 is a cross-sectional view showing an element isolation step in the fourth embodiment. FIG. 10 is a cross-sectional view showing an element isolation step in the fourth embodiment. FIG. 10 is a cross-sectional view showing an element isolation step in the fourth embodiment. FIG. 10 is a cross-sectional view showing an element isolation step in the fourth embodiment. FIG. 10 is a cross-sectional view showing an element isolation step in the fourth embodiment. FIG. 10 is a cross-sectional view showing a first aspect of the fifth embodiment. FIG. 10 is a cross-sectional view showing a second aspect of the fifth embodiment. FIG. 10 is a cross-sectional view showing a third aspect of the fifth embodiment. FIG. 10 is a cross-sectional view showing a first aspect of the sixth embodiment. It is sectional drawing which shows the 2nd aspect of Embodiment 6. FIG. It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 1). It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 1). It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 1). It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 2). It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 2). It is sectional drawing which shows the connection area | region formation process in the Embodiment 6 (the 2). FIG. 23 is a cross-sectional view showing a connection region forming step (No. 3) in the sixth embodiment. FIG. 23 is a cross-sectional view showing a connection region forming step (No. 3) in the sixth embodiment. FIG. 23 is a cross-sectional view showing a connection region forming step (No. 3) in the sixth embodiment. FIG. 10 is a cross-sectional view showing a third aspect of the sixth embodiment. FIG. 10 is a cross-sectional view showing a fourth aspect of the sixth embodiment. It is sectional drawing which shows the 5th aspect of Embodiment 6. FIG. 10 is a cross-sectional view showing a fourth aspect of the second embodiment. FIG. 10 is a cross-sectional view showing a fifth aspect of the second embodiment. FIG. 10 is a cross-sectional view showing a sixth aspect of the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 5) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 5) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 5) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 5) in the second embodiment. FIG. 10 is a cross-sectional view showing an element isolation step (No. 5) in the second embodiment. FIG. 20 is an explanatory diagram showing a complete separation region setting method according to a seventh embodiment. It is explanatory drawing for latchup phenomenon explanation. FIG. 20 is a cross sectional view showing a first aspect of the eighth embodiment. It is a circuit diagram which shows an example of an input circuit. It is a circuit diagram which shows an example of an output circuit. It is sectional drawing which shows the 2nd aspect of Embodiment 8. FIG. FIG. 38 is a plan view showing a third aspect of the eighth embodiment. FIG. 38 is a plan view showing a first aspect of the ninth embodiment. It is sectional drawing which shows the AA cross section of FIG. FIG. 38 is a plan view showing a second mode of the ninth embodiment. It is sectional drawing which shows the BB cross section of FIG. FIG. 38 is a plan view showing a first aspect of the tenth embodiment. FIG. 38 is a plan view showing a second mode of the tenth embodiment. FIG. 38 is a plan view showing a first aspect of the eleventh embodiment. FIG. 38 is a plan view showing a second mode of the eleventh embodiment. FIG. 38 is a plan view showing a first aspect of the twelfth embodiment. It is sectional drawing which shows CC cross section of FIG. FIG. 38 is a plan view showing a second aspect of the twelfth embodiment. It is sectional drawing which shows the DD cross section of FIG. FIG. 38 is a plan view showing a third aspect of the twelfth embodiment. FIG. 20 is a cross-sectional view showing a thirteenth embodiment. FIG. 38 is an explanatory diagram showing the characteristics of the first mode of the fourteenth embodiment. FIG. 38 is an explanatory diagram showing characteristics of the second mode of the fourteenth embodiment. FIG. 38 is a cross sectional view showing a first aspect of the fifteenth embodiment. FIG. 38 is a plan view showing a second mode of the fifteenth embodiment. FIG. 38 is a cross sectional view showing a first aspect of the sixteenth embodiment. FIG. 38 is a cross sectional view showing a second aspect of the sixteenth embodiment. FIG. 38 is a cross sectional view showing a first aspect of the seventeenth embodiment. FIG. 20 is a circuit diagram showing a circuit configuration according to the seventeenth embodiment. FIG. 38 is a cross sectional view showing a second aspect of the seventeenth embodiment. FIG. 38 is a plan view showing a DT-MOS according to an eighteenth embodiment. FIG. 20 is a cross-sectional view showing Embodiment 19; FIG. 38 is a cross sectional view showing a first aspect of the twentieth embodiment. FIG. 38 is a circuit diagram illustrating an example of application of the field transistor according to the twentieth embodiment to an input circuit. FIG. 38 is a circuit diagram showing an example of application of the field transistor of the twentieth embodiment to an output circuit. FIG. 38 is a cross sectional view showing a second aspect of the twentieth embodiment. FIG. 38 is a plan view showing a third aspect of the twentieth embodiment. It is explanatory drawing which shows the impurity distribution of a drain / source region. It is sectional drawing which shows the EE cross section of FIG. It is sectional drawing which shows the semiconductor device of the conventional SOI structure.

Explanation of symbols

1 silicon substrate, 2 buried oxide film, 3 SOI layer, 3A, 3B partial SOI layer, 4 interlayer insulation film, 5, 5s, 5t, 245, 255 drain region, 6, 6s, 6t, 246, 256 source region, 7 Channel formation region, 8 gate oxide film, 9 gate electrode, 10, 20, 146, 147, 156, 164 body region, 11 well region (p-type), 12, 28 well region (n-type), 31 partial oxide film, 32, complete oxide film, 33, 210-212, 218 oxide film, 44, 44A, 44B partial trench, 48 complete trench, 61, 62 polysilicon region, 75-77 low dielectric constant film, 78, 79 silicon oxide film, 80 , 86 to 89 Connection region 104 n-well region, 105, 110, 114, 115, 120 Complete isolation region, 107, 117, 127, 13 7,148 Partial isolation region, 149 Floating partial isolation region, 150 Floating p ⁺ body region, 182,224 Well region, 199 Spiral inductor, 200 High resistance silicon substrate, 223 High resistance region, Q21, Q22 Analog circuit transistor.

Claims (4)

A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer, and an SOI layer,
A plurality of element formation regions provided in the SOI layer and each having a predetermined element formed thereon;
An element isolation region that is provided in the SOI layer and that isolates the plurality of element formation regions from each other;
It has a body region that can fix the potential from the outside,
The body region is formed so as to be in contact with the front surface or the back surface of at least one of the plurality of device formation regions.
Semiconductor device. The body region is formed in an upper layer portion of the buried insulating layer and is in contact with a back surface of the at least one element formation region.
The semiconductor device according to claim 1. The body region is formed through the buried insulating layer and is in contact with the back surface of the at least one element formation region.
The semiconductor device according to claim 1. The body region is provided above the at least one element forming region and is in contact with the surface of the at least one element forming region.
The semiconductor device according to claim 1.

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