JPH11317506A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device, capable of recovering damages due to the difference in the level of element isolation structure and also impressable the entire memory cell region with a substrate bias. SOLUTION: This semiconductor device is provided with a peripheral circuit region element isolated by a field oxide film 15 which reaches an embedded oxide film 11, as well as a memory cell region element isolated by a field sealed element separation structure 31 on an SOI substrate 10. In this case, the upper side of the field oxide film 15 and the field sealed element isolation structure 31 can be made in almost the same hierachy by locating the surface of the peripheral circuit region on the higher layer than the surface of the memory cell region. In such a constitution, respective element active regions 30 in the peripheral circuit region are electrically independent, while single crystalline silicon semiconductor layers 12 range in the entire region of an element active region 32 in the memory cell region, so that the entire memory cell region may be impressed with the semiconductor bias.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of element isolation structures having different heights on the same substrate and a method of manufacturing the same, and more particularly, to an element isolation structure using a buried insulating film and a field shield element isolation structure. The present invention relates to a semiconductor device having both on the same substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, the LOCOS (selective oxidation) method has been mainly used to form an element isolation structure.
This separation method has a problem in that the area of an effective element active region is reduced due to a bird's peak, and the threshold voltage of a field effect transistor is higher than a desired value due to a narrow channel effect. In particular, application to miniaturized semiconductor devices has become difficult. For this reason, a field shield method has attracted attention as an element isolation method different from the selective oxidation method.

Generally, the field shield element isolation structure has a MOS structure in which a shield gate electrode made of a polycrystalline silicon film is formed on a silicon substrate via a shield gate oxide film. When the silicon substrate (or well region) is a P-type,
For example, it is always kept at a constant potential of, for example, 0 [V] by being grounded (GND) via a wiring. For example, it is kept at the power supply potential _Vcc [V]).

As a result, the formation of the channel of the parasitic MOS transistor on the surface of the silicon substrate immediately below the shield gate electrode is prevented, so that elements such as adjacent transistors can be electrically isolated. Further, according to the field shield element isolation method, since ion implantation for forming a channel stopper is not required unlike the LOCOS method, the narrow channel effect of the transistor can be reduced, and the junction capacitance can be reduced because the substrate concentration can be reduced. Therefore, there is an advantage that the speed of the transistor can be increased.

The field shield method is suitable for miniaturization of a semiconductor device because it has no problems such as a bird's beak and a narrow channel effect, and can obtain good element isolation characteristics even when applied to a fine semiconductor device. As reported (eg, IEDM-88, pp. 246-249 “Ful”
ly planarized 0.5 μm technology
technologies for 16M DRAM ").

[0006]

However, in the field shield method, a complementary metal oxide semiconductor (CMOS) is used.
In the case of forming wells having different potentials as in the case of an xide semiconductor structure, various difficulties arise.

For example, in a CMOS circuit, the P-well potential is usually fixed to the ground potential, and the N-well potential is usually fixed to the power supply voltage. Therefore, it is necessary to fix the shield gate for separating the N-type transistor element region on the P-well to the ground potential and to fix the shield gate for separating the P-type transistor element region on the N-well to the power supply voltage. Can not. For this reason, it is not possible to directly connect the shield gate for performing element isolation in the boundary region between the P well and the N well.

Therefore, an active area must be formed in the middle. As a result, the CMOS circuit
The gate of the N-type transistor and the gate of the P-type transistor cannot be directly formed using polysilicon as a material, and a wiring layer on the gate must be used.

Due to such structural restrictions, not only is a large area required, so that the circuit cannot be highly integrated, but also the reliability of the multilayer wiring structure must be pursued. Was an obstacle to doing so.

On the other hand, element isolation by the selective oxidation method is more suitable for CMOS circuits than element isolation by the field shield method.

When a logic LSI is provided as a memory cell region and its peripheral circuit region, such as a DRAM or an EEPROM, a negative voltage is applied to a control gate or a source / drain of a memory cell transistor to form a gate insulating film. A technique has been developed to increase the breakdown voltage of the memory cell and the like and improve the reliability of the memory cell. In this case, a substrate bias (back bias) is applied only to the memory cell region of the semiconductor substrate. To this end, it is necessary to form a so-called triple well structure to limit the region to which the substrate bias is applied. Is complicated.

Therefore, it has been considered to use both the selective oxidation method and the field shield method on the same semiconductor substrate.

However, in the element isolation region by the field shield method, it is necessary to sequentially stack a shield gate insulating film, a shield plate electrode, and a cap insulating film on the surface of the semiconductor substrate. Therefore, the total film thickness of these films is larger than the film thickness of the oxide film for element isolation (field oxide film) by the selective oxidation method, and the region using the selective oxidation method and the field shield method are used. The step with the area was large.

As a result, when forming the wiring on the semiconductor substrate, the step coverage of the wiring at the step between the region where the element isolation region is formed by the selective oxidation method and the region where the element separation region is formed by the field shield method is obtained. And the margin of depth of focus in lithography was small.

For this reason, when both the selective oxidation method and the field shield method are used on the same semiconductor substrate, wiring cannot be easily formed on the semiconductor substrate.
In addition, there has been a problem that the formed wiring is broken at a step portion, and it has been difficult to provide a highly reliable semiconductor device. For example, see JP-A-2-3257. or,
Japanese Patent Application Laid-Open No. 2-172253 discloses a technique in which a step is formed on a substrate surface by removing a field oxide film formed by a LOCOS method. It is not used to resolve the problem.

Accordingly, an object of the present invention is to use a so-called SOI substrate as a semiconductor substrate to achieve high integration and operation speed of semiconductor elements or circuit elements, to facilitate application of a substrate bias, and to achieve element isolation. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can further improve reliability by eliminating obstacles caused by differences in structure height.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having a semiconductor layer formed on a semiconductor substrate via an insulating layer, comprising: a first region having a first element active region defined by a first element isolation structure; and a separation electrode. A second region having a second device active region defined by a second device isolation structure, wherein a thickness of the semiconductor layer in the second device active region is equal to the first device active region. And a predetermined potential is applied to the entire area of the semiconductor layer connected to the second element active region.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device further includes an impurity diffusion layer formed in the semiconductor layer in the second region, and an electrode connected to the impurity diffusion layer. The voltage is applied from the electrode through the impurity diffusion layer.

In one embodiment of the semiconductor device according to the present invention, the impurity diffusion layer is formed near a boundary between the first region and the second region.

In one embodiment of the semiconductor device according to the present invention, a plurality of memory cells are formed in the second region.
A peripheral circuit is formed in the first region.

In one embodiment of the semiconductor device of the present invention, a logic circuit is formed in each of the first and second regions.

In one embodiment of the semiconductor device according to the present invention, the first region and the second region are separated by the first element isolation structure.

In one embodiment of the semiconductor device of the present invention, each of the first region and the second region is surrounded by the first element isolation structure.

In one embodiment of the semiconductor device of the present invention, the first element isolation structure comprises an insulating film.

In one embodiment of the semiconductor device according to the present invention, the first element isolation structure is made of an insulator filling a groove formed in the semiconductor layer.

In one embodiment of the semiconductor device of the present invention, the first element isolation structure is an element isolation structure including a conductive film formed in a groove formed in the semiconductor layer via an insulating film. is there.

In one embodiment of the semiconductor device of the present invention, the first element isolation structure and the second element isolation structure are in contact with each other at a portion adjacent to the first region and the second region. I have.

In one embodiment of the semiconductor device according to the present invention, the first element isolation structure has a tapered shape toward the second region in a portion adjacent to the first region and the second region. Is formed.

In one embodiment of the semiconductor device according to the present invention, a part of the second element isolation structure is continuous with the first element isolation structure.
Is superimposed on the semiconductor layer in the region of FIG.

In one embodiment of the semiconductor device of the present invention, the bottom region of the first element isolation structure is formed so as to be in contact with the insulating layer.

According to the method of manufacturing a semiconductor device of the present invention, a step portion is formed on a surface of a semiconductor layer provided on a semiconductor substrate with an insulating layer interposed therebetween, and the surface of the semiconductor layer becomes an upper layer with the step portion as a boundary. A method for manufacturing a semiconductor device configured on a semiconductor substrate having a first region located and a second region in which the surface of the semiconductor layer is located in a lower layer, the method comprising: A first step of forming a first element isolation structure to reach to form a first element active region; and, in the second region, a surface at substantially the same hierarchical level as a surface of the first element isolation structure. A second step of forming a located field shield element isolation structure; and a third step of forming an electrode connected to the semiconductor layer in the second region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the first element isolation structure is formed of an insulating film.

[0033]

In the present invention, the first element active region in the first region is an electrically independent region surrounded by the first element isolation structure and the insulating layer from the side surface to the lower surface. On the other hand, in the second device active region in the second region, device isolation is achieved by fixing the potential without structurally separating the semiconductor layer by the field shield device isolation structure. Therefore, a plurality of second element active regions are formed in the common semiconductor layer.

Therefore, a substrate bias can be applied to the entire region of the second element active region without applying an electric field to the first element active region. Therefore, in the electrically independent first element active region, it is possible to form a high-speed MOS transistor whose threshold value is set low. On the other hand, it is possible to form a low-speed MOS transistor in which the threshold is set high and the variation of the threshold is suppressed in the second element active region by the substrate bias.

At this time, for example, a region in which only MOS transistors of the same conductivity type are present in a relatively large region such as a DRAM memory cell region is separated by a field shield device isolation structure, and is separated as in a peripheral circuit region of the DRAM memory cell. It is effective to isolate the region where the CMOS circuit is formed with the first element isolation structure.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some specific embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS.
1 to 4 show manufacturing steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 5 is a plan view of FIG. 4A, and a cross-sectional view taken along line AA ′ of FIG.
Corresponding to In these figures, the area shown on the right side is a peripheral circuit formation area, and the area shown on the left side is a memory formation area. Further, a middle region surrounded by the element isolation structure in the right region and the left region is an element active region.

For example, a plurality of D
A RAM memory capacitor is formed, and a CMOS inverter is formed in a peripheral circuit formation region.
4 to 4 show only one access transistor of a DRAM memory capacitor in a memory cell formation region, and a CMO in a peripheral circuit formation region.
Only one MOS transistor of the S inverter is shown.

In the first embodiment, first, as shown in FIG. 1A, the surface of a single-crystal silicon semiconductor substrate 10 is subjected to a thermal oxidation treatment to form a buried oxide film 11 to a thickness of about 30 nm. Then, a single crystal silicon semiconductor substrate is bonded onto the buried oxide film 11, and the entire surface of the single crystal semiconductor substrate is polished or etched to adjust the film thickness to a predetermined value, thereby forming the single crystal silicon semiconductor layer 12.

Thereafter, the single crystal silicon semiconductor layer 12 in the memory cell formation region is thinned to a predetermined thickness by photolithography and subsequent dry etching. As a result, a step 12a is formed in the single crystal silicon semiconductor layer 12 between the memory cell formation region and the peripheral circuit formation region. As a result, the surface of the memory cell formation region is lower by about 200 nm than the surface of the peripheral circuit formation region.

After that, the single crystal silicon semiconductor layer 12
Injection energy about 60 keV, dose amount 1 × 10 ¹² c
Boron is ion-implanted under the condition of about m ⁻² . As a result, the single crystal silicon semiconductor layer 12 becomes a p-type semiconductor layer,
The SOI structure substrate 1 shown in FIG. 1A is completed.

Next, as shown in FIG. 1B, the surface of the single-crystal silicon semiconductor layer 12 is thermally oxidized, and a silicon oxide film 13 having a thickness of about 20 nm is formed on this surface as a pad oxide film. A silicon nitride film 14 having a thickness of about 150 nm is deposited on the silicon oxide film 13 by a CVD method.

Next, as shown in FIG. 1C, a portion to be an element active region in the peripheral circuit forming region and the entire memory cell forming region are covered with a photoresist (not shown). Using the silicon nitride film 14 as a mask
Is etched. That is, the silicon nitride film 14 in the region where the field oxide film is formed in the peripheral circuit formation region is removed.

Next, as shown in FIG. 1D, the single crystal silicon semiconductor layer 12 is selectively oxidized using the silicon nitride film 14 as an antioxidant film to form a silicon oxide film 15 having a thickness of about 400 nm in the field. It is formed as an oxide film. Here, the silicon oxide film 15 is not formed in a region covered with the silicon nitride film 14.

Then, the formed silicon oxide film 15 is formed.
Reaches the buried oxide film 11 of the underlying SOI structure substrate 1 and is integrated with the buried oxide film 11.

Next, as shown in FIG. 2A, the silicon nitride film 14 and the silicon oxide film 13 remaining in the memory cell formation region and the peripheral circuit formation region are removed.

Thus, in the peripheral circuit formation region, the silicon oxide film 15 and the buried oxide film 11 are connected to each other, and are insulated from the surrounding single crystal silicon semiconductor layer 12 and are electrically independent island-shaped element active regions. 30 is completed.

Here, SO 2 is obtained by the above-described bonding method.
Instead of forming the I-structure substrate 1, after forming a field oxide film on a semiconductor substrate having a step, oxygen ions are implanted by so-called SIMOX, for example, as disclosed in JP-A-7-201773. A buried oxide film may be formed so as to be connected to the oxide film to form a structure substantially the same as the structure shown in FIG.

Next, as shown in FIG. 2B, the surface of the single crystal silicon semiconductor layer 12 is thermally oxidized, and a silicon oxide film 17 having a thickness of about 50 nm is formed as a shield gate insulating film on this surface. I do.

Next, as shown in FIG.
A polycrystalline silicon film 18 of about 00 nm is deposited on the entire surface by a CVD method, and phosphorus is thermally diffused into the polycrystalline silicon film 18 to lower the resistance of the polycrystalline silicon film 18. Then, as a cap insulating film covering the polycrystalline silicon film 18, a silicon oxide film
It is deposited on the entire surface by the D method.

Thereafter, using the photoresist (not shown) on the silicon oxide film 21 as a mask, the silicon oxide film 2
1 and the polycrystalline silicon film 18 are etched into a pattern of an element isolation region by a field shield method. As a result, the silicon oxide film 21 and the polycrystalline silicon film 18 are removed from the entire peripheral circuit formation region and the portion of the memory cell formation region to be the element active region.

Next, as shown in FIG.
A silicon oxide film 22 of about 00 nm is deposited on the entire surface by the CVD method, and the silicon oxide films 22 and 17 are etched back by anisotropic dry etching to form a sidewall insulating film made of the silicon oxide film 22 on the polycrystalline silicon film 18. And on the side surface of the silicon oxide film 21. At this time, the silicon oxide film 17 is removed from the respective element active regions in the peripheral circuit formation region and the memory cell formation region. Thereby, in the memory cell formation region, the silicon oxide film 17 (shield gate insulating film), the polycrystalline silicon film 18 (shield plate electrode), the silicon oxide film 21 (cap oxide film), and the silicon oxide film (sidewall insulating film) 22 Is formed.

Here, the surface of the silicon oxide film 15 as the field oxide film is formed on the same layer level in the field shield element isolation structure 31 by the step 12a formed in the single crystal silicon semiconductor layer 12 in advance. Will be.

By setting the polycrystalline silicon film 18 of the field shield element isolation structure 31 to a predetermined potential, the potential of the underlying single crystal silicon semiconductor layer 12 can be fixed to perform element isolation. Thus, the element active region 32 is determined in the memory cell formation region. Further, an element active region 33 is defined at an end of the memory cell formation region. As described above, in the memory cell formation region, the element active region 3 is formed by the field shield device isolation structure 31.
In order to define 2, 33, element isolation is achieved without dividing the single crystal silicon semiconductor layer 12 in the memory cell formation region.

Therefore, when a predetermined voltage is applied to the single crystal silicon semiconductor layer 12 in the memory cell forming region, the single crystal silicon semiconductor layer 12 in the memory cell forming region
The electric field is formed in the entire region of the above.

On the other hand, in the peripheral circuit formation region, since the region from the side surface to the bottom surface of the element active region 30 is covered by the single crystal silicon semiconductor layer 12 and the silicon oxide film 15, the single crystal silicon in the memory cell formation region The electric field applied to the semiconductor layer 12 does not reach.

Next, as shown in FIG. 3C, the single-crystal silicon semiconductor layer 1 exposed by removing the silicon oxide film 17 is formed.
2 is thermally oxidized to form a silicon oxide film 23 having a thickness of about 15 nm as a gate insulating film on this surface.

Thereafter, a polycrystalline silicon film 24 having a thickness of about 200 nm is deposited on the entire surface by the CVD method, and phosphorus is thermally diffused into the polycrystalline silicon film 24 to lower the resistance of the polycrystalline silicon film 24. Then, the polycrystalline silicon film 24
Using the upper photoresist (not shown) as a mask, the polycrystalline silicon film 24 is etched into a gate electrode pattern.

Next, as shown in FIG. 4A, after forming a resist pattern 40 so as to cover the element active region 33, the polycrystalline silicon film 24, the silicon oxide films 15, 2
1, 22 and resist pattern 4 on element active region 33
Using 0 as a mask, arsenic is ion-implanted into the single-crystal silicon semiconductor layer 12 at an implantation energy of 60 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and a heat treatment is applied to the single-crystal silicon semiconductor on both sides of the polycrystalline silicon film 24. A pair of impurity diffusion layers 25 as source / drain are formed on the surface of the layer 12.

At this time, in the memory cell forming region,
Since the single crystal silicon semiconductor layer 12 is formed thin, the impurity diffusion layer 25 is formed so as to reach the insulating layer.

In the memory cell formation region, these gate insulating film 23, polycrystalline silicon film 24 (gate electrode) and impurity diffusion layer 25 constitute an access transistor of a DRAM memory capacitor.

Similarly, in the peripheral circuit formation region, the gate insulating film 23, the polycrystalline silicon film 24 (gate electrode), and the impurity diffusion layer 25 form, for example, one MOS transistor of a CMOS inverter. In the peripheral circuit formation region, since each element active region 30 is electrically independent, the formed MOS transistor is equivalent to a so-called mesa transistor.

Subsequently, after other regions are covered with a photoresist (not shown) so that only the element active regions 33 are exposed, ion implantation is performed. Here, the same conductivity type as that of the single crystal silicon semiconductor layer 12 of the SOI structure substrate 1, that is, p
The impurity of the mold is ion-implanted at a high concentration. Then, a p-type impurity diffusion layer 34 is formed in the single crystal silicon semiconductor layer 12 in the element active region 33 by performing a heat treatment.

FIG. 5 is a plan view of FIG. In FIG. 5, reference numeral 15 denotes a silicon oxide film serving as a field oxide film, and reference numeral 31 denotes a field shield element isolation structure. 24 is a gate electrode and 25 is a source electrode.
This is a drain diffusion layer. Reference numeral 34 denotes a p-type impurity diffusion layer.

As shown in FIG. 5, a plurality of element active regions 32 are formed in the memory cell forming region by the above-described steps. Then, an access transistor is formed in each element active region 32 in the memory cell formation region. Similarly, a plurality of element active regions 30 are formed in the peripheral circuit formation region.

Here, for example, the CMO
In the case of forming an S inverter, these adjacent element active regions 30 are formed in the opposite conductivity type in advance, and
In the step of ion implantation shown in (a), the impurity diffusion layer may be formed by performing ion implantation twice so that each element active region 30 has the opposite conductivity type.

Thereafter, a lower electrode, a dielectric film, and an upper electrode of a memory capacitor (not shown) are formed in the memory cell formation region. At this time, the impurity diffusion layer 2 on the left side of the element active region 32 in the memory cell formation region shown in FIG.
5 is connected to a lower electrode. Then, one unit of memory cell is configured by the access transistor and the memory capacitor including the lower electrode, the dielectric film, and the upper electrode.

Next, as shown in FIG. 4B, a silicon oxide film 26 as an interlayer insulating film is deposited on the entire surface by the CVD method.

Since the surface of the field shield element isolation structure 31 and the surface of the silicon oxide film 15 as the field oxide film are formed at substantially the same level, the surface of the silicon oxide film 26 formed thereon is also Are formed on substantially the same plane on the element isolation structure.

Then, contact holes 26 a and 26 b reaching the impurity diffusion layer 25 and the p-type impurity diffusion layer 34 are formed in the silicon oxide film 26. Then, an A1 film is deposited on the entire surface by sputtering, and the A1 film filling the contact hole 26a is formed.
One film is processed into a wiring pattern by a fine processing technique to form an Al wiring 27a. At the same time, an Al electrode 27b connected to the p-type impurity diffusion layer 34 is formed by patterning the Al film filling the contact hole 26b.

As shown in FIG. 4B, since the surface of silicon oxide film 26 is formed at substantially the same hierarchical position in the peripheral circuit region and the memory cell forming region, Al wiring 27 is formed.
a can also be formed horizontally. Accordingly, even when the Al wiring 27 is formed so as to straddle the memory cell formation region and the peripheral circuit formation region, the Al wiring 27 can be formed on a flat surface, thereby suppressing a problem such as disconnection of the Al wiring 27 due to a step. can do.

The Al electrode 27b in which the contact hole 26b is buried is used for applying a predetermined voltage to the single crystal silicon semiconductor layer 12 in the memory cell formation region. That is, since the element active region 32 is defined by the field shield element isolation structure 31 in the memory cell formation region as described above, the single crystal silicon semiconductor layer 12 is integrally formed over the entire memory cell formation region without being partitioned. Have been. Therefore, by applying a predetermined voltage to the Al electrode 27b, a constant electric field can be generated in all the element active regions 32 in the memory cell formation region.

This makes it possible to suppress the fluctuation of the threshold value of the transistor in the memory cell formation region and keep it constant, and it is possible to keep the threshold value high.

Thereafter, a silicon oxide film 28 as a second interlayer insulating film is deposited on the entire surface by a CVD method,
7a and the Al electrode 27b are buried to complete the semiconductor device according to the first embodiment.

In the first embodiment, the selective oxidation (LOCO
The silicon oxide film 15 having a thickness of about 400 nm formed by the S) method has a thickness of about 200 nm, which is half of the silicon oxide film 15 on the surface of the silicon substrate 11. Polycrystalline silicon film 18
And the total thickness of the silicon oxide films 17 and 21 is 350 nm
And the entire thickness of the silicon substrate 11
Are present on the surface.

Therefore, only by forming these element isolation regions on the surface of the SOI structure substrate 1 as in the conventional example described above, the region using the field shield method is better than the region using the selective oxidation method. Also increase by about 150 nm. However, in the first embodiment, as shown in FIG.
Since the surface of the region using the field shield method is lower than the surface of the region using the selective oxidation method by about 200 nm due to the step portion 12a, there is no space between these regions after the element isolation region is formed. There is no step of about 50 nm.

In the first embodiment, the region shown on the right side in FIGS. 1 to 4 is a peripheral circuit region, and the region shown on the left side is a memory cell region of a DRAM, for example. From the viewpoint of reducing the area of the isolation region, the element isolation region by the selective oxidation method is more suitable for the CMOS circuit formed in the peripheral circuit region than the element isolation region by the field shield method, and the element isolation region by the field shield method is selected. This is because it is more suitable for the memory cell region than the element isolation region by the oxidation method.

In the memory cell formation region,
By applying a predetermined voltage to the single-crystal silicon semiconductor layer 12 of the SOI structure substrate 1, a substrate bias can be applied over the entire area of the plurality of element active regions 12 in the memory cell formation region.

More specifically, by applying a substrate potential (substrate bias) of, for example, −2.0 V to the Al electrode 27 b, the single-crystal silicon semiconductor layer over the entire memory cell formation region through the p-type impurity diffusion layer 34. 12, it is possible to apply a substrate bias all at once.

Further, the substrate bias does not reach the electrically independent element active region 30 in the peripheral circuit formation region. Therefore, it is possible to provide a structure that does not adversely affect the threshold value of the MOS transistor in the peripheral circuit formation region without forming the triple well structure. Thus, it is possible to prevent the threshold value of the MOS transistor in the peripheral circuit formation region from being increased by the substrate bias effect. Therefore, it is possible to reliably apply a substrate bias to the memory cell formation region while maintaining a good drive current of the MOS transistor in the peripheral circuit formation region and enabling high-speed operation.

In the first embodiment, an example is shown in which a memory capacitor of a DRAM is formed in a memory cell formation region. However, a memory cell other than a memory capacitor of a DRAM may be formed. For example, a nonvolatile memory such as an EEPROM may be formed. Further, these volatile or non-volatile memories may be multivalued memories.
For example, a writing method and a reading method for a multi-level DRAM are described in Japanese Patent Application Laid-Open No. 60-239994. Further, the writing method and the reading method for the multi-value nonvolatile memory are described in JP-A-6-282992 and JP-A-7-201189.

The field shield element isolation structure 3
An element other than the memory cell may be formed in the region where the element isolation has been performed in 1. For example, by forming another peripheral circuit having a MOS transistor in the region shown as the memory cell formation region in the first embodiment, the MOS transistor in the region where element isolation is achieved by the silicon oxide film 15 and the field transistor It is possible to coexist by changing the threshold value of the MOS transistor in the region where the element isolation is performed by the shield element isolation structure 31.

As described above, when transistors having different operation speeds are formed, a high-speed transistor generally has to sacrifice a cut-off leak current margin to increase a drive current, but a low-speed transistor increases a cut-off leak current. Since it is not necessary to secure a drive current, it is necessary to secure a cutoff leak current margin even if the threshold value is increased.

Therefore, if a high-speed transistor is formed in a region where element isolation is achieved by the silicon oxide film 15 and a low-speed transistor is formed in a region where element isolation is achieved by the field shield element isolation structure 31, substrate bias is applied. The threshold value of the low-speed transistor can be kept sufficiently high, and the high-speed transistor can be set at a low threshold value without affecting the substrate bias to realize high-speed operation. In this case, when the low-speed transistor does not operate, it is possible to further increase the substrate potential, further increase the cutoff leak current margin, and reduce the current consumption.

Therefore, even if a triple well structure is not formed as in the prior art, transistors having different threshold values can be replaced by S
It can be mounted on the OI structure substrate 1.

Further, the semiconductor device of the first embodiment is
The OI structure substrate 1 has two regions having different surface heights. Therefore, even if an element having a high height is arranged in a region where the surface of the SOI structure substrate 1 is lower, a step on the surface of the interlayer insulating film on the element can be reduced in the entire region of the SOI structure substrate 1.

According to the first embodiment, the step between the first region where the element isolation region is formed by the selective oxidation method and the second region where the element isolation region is formed by the field shield method can be reduced. Therefore, wiring can be easily formed on the semiconductor substrate, and a highly reliable semiconductor device can be manufactured.

Further, since the first region is suitable for a CMOS circuit and the second region has an excellent element isolation capability, a memory cell region having a high degree of integration and a peripheral circuit region having a CMOS structure are required. In addition, the wiring can be easily formed on the semiconductor substrate, and the reliability is high.

Further, by arranging a high device in a region where the surface of the semiconductor substrate is lower, a step on the surface of the interlayer insulating film on the device can be reduced in the entire region of the semiconductor substrate. Wiring can be easily formed on the interlayer insulating film, and reliability can be improved.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 6 to 9 and FIG.

FIGS. 6 to 9 show the manufacturing steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG.
FIG. 9B is a plan view of FIG. 9B, and a cross-sectional view taken along line AA ′ of FIG. 10 corresponds to FIG. 9B. In these figures,
The area shown on the right is a peripheral circuit formation area, and the area shown on the left is a memory cell formation area. Further, a middle region surrounded by the element isolation structure in the right region and the left region is an element active region.

For example, a plurality of D
A RAM memory capacitor is formed, and a CMOS inverter is formed in a peripheral circuit formation region.
9 show only one access transistor of a DRAM memory capacitor in a memory cell formation region, and a CMO in a peripheral circuit formation region.
Only one MOS transistor of the S inverter is shown.

In the second embodiment, first, as shown in FIG. 6A, the surface of the single crystal silicon semiconductor substrate 200 is subjected to a thermal oxidation treatment to form a buried oxide film 201 of 30 nm.
A single-crystal silicon semiconductor substrate is attached on the buried oxide film 201, and the entire surface of the single-crystal semiconductor substrate is polished or etched to adjust the thickness to a predetermined value. A layer 202 is formed.

Thereafter, the single crystal silicon semiconductor layer 202
And an implantation energy of about 60 keV and a dose of 1 × 10
Ions are implanted at about / cm ¹² . Thus, the SOI structure substrate 2 shown in FIG. 6A is completed using the single crystal silicon semiconductor layer 202 as a p-type semiconductor layer.

Next, as shown in FIG. 6 (b), a film thickness of 200
A silicon oxide film 203 of about nm is formed on the single crystal silicon semiconductor layer 202. Further, the silicon nitride film 240
Is formed on the silicon oxide film 203. Then, the silicon nitride film 240 and the silicon oxide film 203 formed in the element isolation region are removed by etching using a photolithography technique and an etching technique.

Next, as shown in FIG. 6C, the single crystal silicon semiconductor layer 202 is removed by etching using the silicon nitride film 240 as a mask to form a groove B in the single crystal silicon semiconductor layer 202. . The single crystal silicon semiconductor layer 202 is etched so that the bottom of the groove B becomes the surface layer of the buried oxide film 201. Here, the groove B is
Formed around the element active region in the peripheral circuit formation region,
It becomes an element isolation region in a later step. The concave portion C will be a memory cell formation region in a later step.

Next, as shown in FIG. 6D, the SOI structure substrate 2 is subjected to thermal oxidation to form a silicon oxide film 204 as a thermal oxide film having a thickness of about 20 nm in the groove B.

Thereafter, a silicon oxide film 205 having a thickness of about 400 nm is formed on the entire surface (over) of the single crystal silicon substrate 202 by the CVD method.

Thus, the silicon oxide film 20 is formed in the groove B.
5, and the silicon oxide film 205 and the buried oxide film 201 become an integral insulating film. Thereafter, the silicon oxide film 205 is polished by using the CMP method, and the silicon oxide film 205 is left only in the groove B. In this polishing step, the silicon nitride film 240 and the silicon oxide film 203 are removed.

Next, as shown in FIG. 7A, a silicon oxide film 240 is formed on the entire surface of the single crystal silicon semiconductor layer 202 by a CVD method. Thereafter, the peripheral circuit formation region is covered with a photoresist film 206, and the silicon oxide film Y and the single crystal silicon substrate 202 in the memory cell formation region are sequentially etched to form the single crystal silicon semiconductor layer 202.
As a result, a concave portion C is formed. By this etching, the surface of the substrate 202 in the memory cell formation region is 200 nm thicker than the surface of the silicon single crystal semiconductor layer 202 in the peripheral circuit formation region.
About lower. After ashing the photoresist film 206, the silicon oxide film 241 is removed by wet etching.

As a result, as shown in FIG. 7B, a trench type element isolation structure composed of the silicon oxide film 205 is formed. In the peripheral circuit formation region, the silicon oxide film 205 and the buried oxide film 201 are connected to each other, and an island-shaped element active region 230 which is insulated from the surrounding single crystal silicon semiconductor layer 202 and electrically independent is completed.

Here, SO 2 is obtained by the above-described bonding method.
Instead of forming the I-structure substrate 2, after performing the above-described steps up to FIG. 7B using an ordinary silicon semiconductor substrate, a so-called so-called “JP-A-7-201773” is disclosed. Oxygen ions may be implanted by SIMOX to form a buried oxide film so as to be connected to the silicon oxide film 205, thereby forming a structure substantially the same as the structure shown in FIG. 7B.

Next, as shown in FIG. 7C, the surface of the single-crystal silicon semiconductor layer 202 is subjected to thermal oxidation so that
A shield gate insulating film 207 of about 0 nm is formed.
At this time, an insulating film is also formed on the exposed surface of the peripheral circuit formation region.

Next, as shown in FIG.
The polycrystalline silicon film 20 having a thickness of about 100 nm
8 (which will later become a field shield electrode) is formed, and phosphorus is thermally diffused therein to reduce the resistance. Next, a silicon oxide film 209 (to become a cap insulating film later) with a thickness of about 300 nm covering the polycrystalline silicon film 208 is formed by a CVD method.

Next, as shown in FIG. 8B, after a photoresist film (not shown) is formed on the silicon oxide film 209, the photoresist film (not shown) is formed in the element isolation region of the field shield element isolation method. Pattern into a shape. Using the patterned photoresist film (not shown) as a mask, the silicon oxide film 209 and the polycrystalline silicon film 208 are selectively etched away to form a field shield electrode 208 and a cap insulating film 209.

Next, as shown in FIG.
A silicon oxide film 210 of about 00 nm is deposited on the entire surface by a CVD method, and the silicon oxide film 210 is etched back by anisotropic etching, so that the side surfaces of the shield plate electrode 208 and the cap insulating film 209 are formed from the silicon oxide film. A side wall insulating film 210 is formed. At this time,
The shield gate insulating film 207 is removed from the element active regions in both the peripheral circuit formation region and the memory cell formation region. Through the above steps, the field shield element isolation structure 231 (comprising the shield gate insulating film 207, the shield plate electrode 208, the cap oxide film 209, and the side wall insulating film 210) is formed in the memory cell formation region.

Here, the surface of the field shield element isolation structure 231 and the portions of the single crystal silicon semiconductor layer 202 and the silicon oxide film 205 in the peripheral circuit formation region are formed by the concave portions C formed in the single crystal silicon semiconductor layer 202 in advance. The surfaces will be formed at approximately the same hierarchical level.

By setting the shield plate electrode 208 of the field shield element isolation structure 231 to a predetermined potential,
The element isolation can be performed by fixing the potential of the lower single-crystal silicon semiconductor layer 202. Thus, element active regions 232 and 233 are determined in the memory cell forming region. As described above, in the memory cell formation region, the element active regions 232 and 233 are defined by the field shield element isolation structure 231, so that the element isolation is performed without dividing the single crystal silicon semiconductor layer 202 in the memory cell formation region. Will be.

Therefore, when a predetermined voltage is applied to the single crystal silicon semiconductor layer 202 in the memory cell type region, the single crystal silicon semiconductor layer 2 in the memory cell type region
02, the electric field is formed in the entire region.

On the other hand, in the peripheral circuit formation region, the region from the side surface to the bottom surface of the element active region 230 is covered with the buried oxide film 202 and the silicon oxide film 205, so that the single crystal silicon semiconductor layer in the memory cell formation region is formed. The electric field applied to 202 does not extend.

Next, as shown in FIG. 9A, the surface of the exposed single-crystal silicon semiconductor layer 202 is subjected to thermal oxidation to form a gate insulating film 211 having a thickness of about 15 nm. Next, a film thickness of 200 is formed on the gate insulating film 211.
forming a polycrystalline silicon film of about nm by a CVD method,
The resistance is lowered by thermally diffusing the phosphorus into this. Next, a photoresist (not shown) having a predetermined pattern is provided on the polycrystalline silicon film, and the polycrystalline silicon film is etched into a predetermined pattern using the photoresist as a mask to form a gate electrode 212.
To form

Next, as shown in FIG. 9B, a resist pattern 242 is formed so as to cover the boundary region between the memory cell formation region and the peripheral circuit formation region and the element active region 233. After that, the gate electrode 212, the field element isolation structure 231 (the shield gate insulating film 207, the shield plate electrode 208, the cap oxide film 209, and the side wall insulating film 210), the silicon oxide film 205, and the resist pattern 242 are used as masks, for example, arsenic. A pair of impurity diffusion layers serving as source / drain diffusion layers are formed on the surface of the single crystal silicon semiconductor layer 202 on both sides of the gate electrode 212 by performing ion implantation at an implantation energy of 60 keV and a dose of 5 × 10 ¹⁵ cm ^−2. 213 are formed.

In the memory cell formation region, an access transistor of a DRAM memory cell capacitor is constituted by these gate insulating film 211, gate electrode 212 and impurity diffusion layer 213.

Similarly, also in the peripheral circuit formation region, the gate insulating film 211, the gate electrode 212, the impurity diffusion layer 2
13, for example, one MOS of a CMOS inverter
A transistor is configured. In the peripheral circuit formation region, since each element active region is electrically independent, the formed MOS transistor is equivalent to a so-called mesa transistor.

Subsequently, another region is covered with a photoresist (not shown) so that only the element active region 233 is exposed, and then ion implantation is performed. Here, the same conductivity type as that of the single crystal silicon semiconductor layer 202 of the SOI structure substrate 2, that is, p-type impurities is ion-implanted at a high concentration. And
By performing the heat treatment, the p-type impurity diffusion layer 2 is formed on the single crystal silicon semiconductor layer 202 in the element active region 233.
34 are formed.

FIG. 10 is a plan view of FIG. 9B. In FIG. 10, reference numeral 205 denotes a silicon oxide film having a trench element isolation structure, and 231 denotes a field shield element isolation structure. Reference numeral 212 is a gate electrode, and 213 is a source / drain diffusion layer. And
234 is a p-type impurity diffusion layer.

As shown in FIG. 10, a plurality of element active regions 232 are formed in the memory cell forming region by the above-described steps. Then, an access transistor is formed in each element active region 232 in the memory cell formation region. Similarly, a plurality of element active regions 230 are formed in the peripheral circuit formation region.

Here, for example, the CMO is
When forming an S inverter, these adjacent element active regions 230 are formed in advance of the reverse conductivity type, and
The impurity diffusion layer may be formed by performing the ion implantation shown in (b) in two steps, and performing ion implantation so that each element active region 230 has the opposite conductivity type.

Thereafter, for example, a lower electrode, a dielectric film, and an upper electrode of a memory capacitor (not shown) are formed in a memory cell formation region. At this time, the lower electrode is connected to the impurity diffusion layer 213 on the left side of the element active region 232 in the memory cell formation region shown in FIG. Then, one unit of memory cell is configured by the access transistor and the memory capacitor including the lower electrode, the dielectric film, and the upper electrode.

Next, as shown in FIG. 9C, a silicon oxide film 214 as an interlayer insulating film is deposited on the entire surface by the CVD method.

Since the surface of the field shield element isolation structure 231 and the surfaces of the single crystal silicon semiconductor layer 202 and the silicon oxide film 205 in the peripheral circuit formation region are formed at substantially the same level, the silicon formed thereover is formed. The surface of oxide film 214 is also formed on substantially the same plane.

Then, contact holes 226a and 226 reaching impurity diffusion layer 213 and p-type impurity diffusion layer 234 are formed.
b is opened in the silicon oxide film 214. Then, an A1 film is deposited on the entire surface by sputtering, and the contact hole 226 is formed.
a, 226b. Then, similarly to the first embodiment, the A1 film is processed into a wiring pattern by a fine processing technique, and an Al wiring 227a reaching the impurity diffusion layer 213 and an Al electrode 227b reaching the p-type impurity diffusion layer 234 are formed.

As shown in FIG. 9C, the surface of the silicon oxide film 214 is formed at substantially the same hierarchical position in the peripheral circuit region and the memory cell forming region.
27a can also be formed horizontally. Therefore, even when the Al wiring 227a is formed so as to straddle the memory cell formation region and the peripheral circuit formation region, the Al wiring 227a can be formed flat.
Problems such as disconnection of 7a can be suppressed.

A reaching the p-type impurity diffusion layer 234
The 1-electrode 227b is used for the purpose of applying a predetermined voltage to the single-crystal silicon semiconductor layer 202 in the memory cell formation region, as in the first embodiment. That is, as described above, in the memory cell formation region, the element active regions 231 and 231 are formed by the field shield element isolation structure 231.
32, the single crystal silicon semiconductor layer 202
Are formed integrally over the entire area of the memory cell formation region without being partitioned. Therefore, by applying a predetermined voltage to the Al electrode 227b reaching the p-type impurity diffusion layer 234, all the element active regions 2 in the memory cell formation region
32 can generate a constant electric field.

Thus, it is possible to suppress a change in the threshold value of the transistor in the memory cell formation region and to keep the threshold value high.

Thereafter, a silicon oxide film 216 as a second interlayer insulating film is formed on the silicon oxide film 214 by the CVD method, and the Al wiring 227a and the Al electrode 227b are formed.
Is embedded to complete the semiconductor device according to the second embodiment.

In the second embodiment, the region shown on the right side in FIGS. 6 to 9 is a peripheral circuit region, and the region shown on the left side is a memory cell region of a DRAM, for example. From the viewpoint of reducing the area of the CM, the device isolation region formed by the trench type device isolation structure is formed in the peripheral circuit region more than the device isolation region formed by the field shield method.
This is because it is suitable for the OS circuit, and the element isolation region by the field shield method is more suitable for the memory cell region than the element isolation region by the trench type element isolation structure.

Then, in the memory cell formation region,
By applying a predetermined voltage to the single-crystal silicon semiconductor layer 202 of the SOI structure substrate 2, a substrate bias can be applied to the entire region of the plurality of element active regions 232 in the memory cell formation region.

More specifically, p-type impurity diffusion layer 234
By applying a substrate potential (substrate bias) of, for example, −2.0 V to the Al electrode 227 b reaching the substrate electrode, the substrate bias is simultaneously applied to the single crystal silicon semiconductor layer 202 over the entire memory cell formation region through the p-type impurity diffusion layer 234. Can be applied.

Further, the substrate bias does not reach the electrically independent element active region 230 in the peripheral circuit formation region. Therefore, it is possible to provide a structure that does not adversely affect the threshold value of the MOS transistor in the peripheral circuit formation region without forming the triple well structure. Thus, it is possible to prevent the threshold value of the MOS transistor in the peripheral circuit formation region from being increased by the substrate bias effect. Therefore, it is possible to reliably apply a substrate bias to the memory cell formation region while maintaining a good drive current of the MOS transistor in the peripheral circuit formation region and enabling high-speed operation.

Further, the semiconductor device of the second embodiment is
The OI structure substrate 2 has two regions with different surface heights. Therefore, even if an element having a high height is arranged in a region where the surface of the SOI structure substrate 2 is lower, a step on the surface of the interlayer insulating film on the element can be reduced in the entire region of the SOI structure substrate 2.

According to the second embodiment, the first region where the element isolation region is formed by the trench type element isolation structure and the second region where the element isolation region is formed by the field shield method.
Since the step on the surface of the interlayer insulating film covering the region can be reduced, wiring can be easily formed on the semiconductor substrate, and a highly reliable semiconductor device can be manufactured.

Further, since the first region is suitable for a CMOS circuit and the second region has excellent element isolation capability, a memory cell region having a high degree of integration and a peripheral circuit region having a CMOS structure are required. In addition, the wiring can be easily formed on the semiconductor substrate, and the reliability is high.

By arranging a device having a high height in a region where the surface of the semiconductor substrate is lower, a step on the surface of the interlayer insulating film on the device can be reduced in the entire region of the semiconductor substrate. Wiring can be easily formed on the interlayer insulating film, and reliability can be improved.

According to the above manufacturing steps, the region for forming the field shield element isolation structure can be formed at a lower position than the region for forming the silicon oxide film for the buried insulating film element isolation. It is important to contribute.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS.

FIGS. 11 to 14 show manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG.
FIG. 5 is a plan view of FIG. 14B, and a cross-sectional view taken along the line AA ′ of FIG. 15 corresponds to FIG. In these figures, the area shown on the right side is a peripheral circuit formation area, and the area shown on the left side is a memory formation area. Further, a region surrounded by the device isolation structure in the right region and the left region is a device active region.

For example, a plurality of D
A RAM memory capacitor is formed, and a CMOS inverter is formed in a peripheral circuit formation region.
1 to 14 show only one DRAM memory capacitor access transistor in the memory cell formation region, and C in the peripheral circuit formation region.
Only one MOS transistor of the MOS inverter is shown.

In the third embodiment, first, FIG.
As shown in FIG. 5, the surface of the single crystal silicon semiconductor substrate portion 500 is subjected to a thermal oxidation treatment to reduce the buried oxide film 501 by 30 n.
m, a single-crystal silicon semiconductor substrate is bonded to the buried oxide film 501, and the entire surface of the single-crystal semiconductor substrate is polished or etched to adjust the thickness to a predetermined value. A semiconductor layer 502 is formed.

After that, the single crystal silicon semiconductor layer 502
And an implantation energy of about 60 keV and a dose of 1 × 10
Boron is ion-implanted under the condition of about cm ^-12 . Thus, the SOI structure substrate 5 shown in FIG. 11A is completed using the single crystal silicon semiconductor layer 502 as a p-type semiconductor layer.

Next, as shown in FIG. 11B, the surface of the single-crystal silicon semiconductor layer 502 is subjected to thermal oxidation to form a silicon oxide film 503 having a thickness of about 40 nm. Next, a silicon nitride film 517 is formed thereon by CVD method.
It is formed to a thickness of about 50 nm. Next, using the patterned photoresist (not shown) as a mask, the silicon oxide film 503 and the silicon nitride film 517 other than the element activation region in the peripheral circuit formation region are removed by etching. Of course, at this time, the silicon oxide film and the silicon nitride film in the memory cell formation region are all removed by etching.

Next, as shown in FIG. 11C, using the silicon oxide film 503 and the silicon nitride film 517 as a mask, the single crystal silicon semiconductor layer 502 is etched and removed by about 400 nm to form the single crystal silicon semiconductor layer 502. A groove B and a recess C are formed therein. Here, the groove B is formed around the element active region in the peripheral circuit formation region, and will be an element isolation region in a later step. In addition, the concave portion C is formed in a later step.
It becomes a memory cell formation region. Further, the groove portion B is continuously connected to the concave portion C at the boundary between the memory cell forming region and the peripheral circuit forming region, as is clear from the drawing.

Next, after covering with a photoresist (not shown) so that only the groove B is exposed, anisotropic etching is performed so that the groove B reaches the buried oxide film 501.
After that, the photoresist is removed.

Next, as shown in FIG. 11D, the exposed single crystal silicon semiconductor layer 502 is subjected to thermal oxidation to form a silicon oxide film 504 as a thermal oxide film having a thickness of about 20 nm.
To form

Next, as shown in FIG. 12A, a silicon oxide film 505 is formed to a thickness of about 600 nm on the entire surface of the single crystal silicon semiconductor layer 502 by a CVD method.

Thus, the silicon oxide film 50 is formed in the groove B.
5, the silicon oxide film 505 and the buried oxide film 501 become an integral insulating film.

Next, as shown in FIG. 12B, the silicon nitride film 517 is formed by chemical mechanical polishing (CMP).
The silicon oxide film 505 is polished and removed until is exposed.

Next, as shown in FIG. 12C, the peripheral circuit forming region is covered with a photoresist film 506, and wet etching is performed. This wet etching is performed using hydrofluoric acid until the single crystal silicon semiconductor layer 502 in the memory cell formation region is exposed. Then, the silicon oxide film 505 is etched in a forward tapered shape at the boundary between the memory cell formation region and the peripheral circuit formation region, as shown in FIG. Next, the photoresist film 506 is removed, and the silicon nitride film 5 is formed using hot phosphoric acid.
Then, the silicon oxide film 503 is etched away using hydrofluoric acid.

As a result, as shown in FIG.
A trench-type element isolation structure composed of the silicon oxide film 505 is formed. Then, in the peripheral circuit formation region, the silicon oxide film 505 and the buried oxide film 501 are connected, and the island-shaped element active region 530 which is insulated from the surrounding single crystal silicon semiconductor layer 502 and electrically independent is completed. Note that the corner portion 542 of the silicon oxide film 505 is rounded by the cleaning process of the SOI substrate 5.

Here, SO 2 is obtained by the above-mentioned bonding method.
Instead of forming the I-structure substrate 5, after performing the above-described steps up to FIG. 12D using a normal silicon semiconductor substrate, for example, as disclosed in JP-A-7-201773. Alternatively, oxygen ions may be implanted by so-called SIMOX to form a buried oxide film so as to be connected to the silicon oxide film 505 to form a structure substantially the same as the structure shown in FIG.

Next, as shown in FIG. 12E, the surface of the single crystal silicon semiconductor layer 502 is thermally oxidized to a thickness of 40 nm.
An about m shield gate insulating film 507 is formed. At this time, the insulating film 507 is also formed on the exposed surface of the peripheral circuit formation region.
Is formed.

Next, as shown in FIG.
Polycrystalline silicon film 508 having a thickness of about 100 nm
Then, phosphorus is thermally diffused to lower the resistance of the polycrystalline silicon film 508. Next, a silicon oxide film 509 having a thickness of about 300 nm is formed on the entire surface by the CVD method (this will later become a cap insulating film of the shield plate electrode).

Next, as shown in FIG. 13B, using the patterned photoresist film (not shown) as a mask, the silicon oxide film 509 and the polycrystalline silicon film 50 are formed.
8 is selectively etched away to form a shield plate electrode 508 and a cap insulating film 509.

Next, as shown in FIG. 13C, a silicon oxide film 510 having a thickness of about 200 nm is deposited on the entire surface by the CVD method, and the silicon oxide film 510 is etched back by anisotropic etching. As a result, a sidewall insulating film 510 made of the silicon oxide film is formed on the side surfaces of the field shield electrode 508 and the cap insulating film 509. At this time, the shield / gate insulating film 507 is removed from the element active regions in both the peripheral circuit formation region and the memory cell formation region. Through the above steps, a field shield element isolation structure 531 (consisting of the shield gate insulating film 507, the shield gate electrode 508, the cap oxide film 509, and the sidewall insulating film 510) is formed in the memory cell formation region.

Here, the surface of the field shield element isolation structure 531 and the single crystal silicon semiconductor layer 502 and the silicon oxide film 505 in the peripheral circuit formation region are formed by the concave portions C formed in the single crystal silicon semiconductor layer 502 in advance. The surfaces will be formed at approximately the same hierarchical level.

By setting the shield plate electrode 508 of the field shield element isolation structure 531 to a predetermined potential,
The element can be separated by fixing the potential of the lower single-crystal silicon semiconductor layer 502. Thus, element active regions 532 and 533 are determined in the memory cell formation region. As described above, in the memory cell forming region, the element active regions 532 and 533 are defined by the field shield element separating structure 531, so that the element isolation is performed without dividing the single crystal silicon semiconductor layer 502 in the memory cell forming region. Will be.

Therefore, when a predetermined voltage is applied to single crystal silicon semiconductor layer 502 in the memory cell type region, single crystal silicon semiconductor layer 5 in the memory cell type region
02, the electric field is formed in the entire region.

On the other hand, in the peripheral circuit formation region, since the region from the side surface to the bottom surface of element active region 530 is covered by silicon oxide film 505 and buried oxide film 501, the single crystal silicon semiconductor layer in the memory cell formation region The electric field applied to 502 does not extend.

Next, as shown in FIG. 14A, the surface of the exposed single crystal silicon semiconductor layer 502 is subjected to thermal oxidation to form a gate insulating film 511 having a thickness of about 15 nm. Next, on this gate insulating film 511, a film thickness of 200
forming a polycrystalline silicon film of about nm by a CVD method,
The resistance is lowered by thermally diffusing the phosphorus into this. Next, a photoresist having a predetermined pattern is provided on the polycrystalline silicon film, and the polycrystalline silicon film is etched into a predetermined pattern using the photoresist as a mask to form a gate electrode 512.

Next, as shown in FIG. 14B, after forming a resist pattern 540 covering the element active region 533, the gate electrode 512, the field element isolation structure (shield gate insulating film 507, shield plate electrode 50
8, the cap oxide film 509 and the side wall insulating film 510), the silicon oxide film 505 and the resist pattern 540 on the element active region 533 are used as a mask, for example, arsenic is implanted at an energy of 60 keV and a dose is 5 × 10 ¹⁵ cm.
^-2 ion implantation, heat treatment, and gate electrode 512
Impurity diffusion layers 5 serving as source / drain diffusion layers on both sides of
13 is formed.

As shown in FIG. 14C, in a memory cell forming region, an access transistor of a DRAM memory capacitor is constituted by these gate insulating film 511, gate electrode 512 and impurity diffusion layer 513.

Similarly, also in the peripheral circuit forming region, the gate insulating film 511, the gate electrode 512, the impurity diffusion layer 5
13, for example, one MOS of a CMOS inverter
A transistor is configured. In the peripheral circuit formation region, since each element active region is electrically independent, the formed MOS transistor is equivalent to a so-called mesa transistor.

Subsequently, after the other region is covered with a photoresist (not shown) so that only the element active region 533 is exposed, ion implantation is performed. Here, the same conductivity type as that of the single crystal silicon semiconductor layer 502 of the SOI structure substrate 5, that is, p-type impurities is ion-implanted at a high concentration. And
By performing the heat treatment, the p-type impurity diffusion layer 5 is added to the single crystal silicon semiconductor layer 502 in the element active region 533.
34 are formed.

FIG. 15 is a plan view of FIG. In FIG. 15, reference numeral 505 denotes a silicon oxide film having a trench-type element isolation structure, and reference numeral 531 denotes a field shield element isolation structure. Further, 512 is a gate electrode, 513 is an impurity diffusion layer, and 534 is a p-type impurity diffusion layer.

As shown in FIG. 15, a plurality of element active regions 532 are formed in the memory cell formation region by the above-described steps. Then, an access transistor is formed in each element active region 532 in the memory cell formation region. Similarly, a plurality of element active regions 530 are formed in the peripheral circuit formation region.

Here, for example, the CMO is
In the case of forming an S inverter, these adjacent element active regions 530 are previously formed to have a reverse conductivity type, and
In the step of ion implantation shown in FIG. 4B, the impurity diffusion layer may be formed by performing ion implantation twice so that each element active region 530 has the opposite conductivity type.

Thereafter, for example, a lower electrode, a dielectric film, and an upper electrode of a memory capacitor (not shown) are formed in a memory cell formation region. At this time, the lower electrode is connected to the impurity diffusion layer 513 on the left side of the element active region 532 in the memory cell formation region shown in FIG. And an access transistor and a lower electrode, a dielectric film,
One unit of memory cell is constituted by the memory capacitor including the upper electrode.

Next, as shown in FIG. 14C, a silicon oxide film 514 as an interlayer insulating film is deposited on the entire surface by the CVD method.

Since the surface of the field shield element isolation structure 531 and the surfaces of the single crystal silicon semiconductor layer 502 and the silicon oxide film 505 in the peripheral circuit forming region are formed at substantially the same hierarchical level, the silicon formed thereover is formed. The surface of oxide film 514 is also formed on substantially the same plane.

Then, contact holes 526a, 526 reaching impurity diffusion layer 513 and p-type impurity diffusion layer 534 are formed.
b is opened in the silicon oxide film 514. Then, an A1 film is deposited on the entire surface by sputtering, and the contact hole 526 is formed.
a, 526b. Then, similarly to the first embodiment, the A1 film is processed into a wiring pattern by a fine processing technique, and an Al wiring 527a reaching the impurity diffusion layer 513 and an Al electrode 527b reaching the p-type impurity diffusion layer 534 are formed.

As shown in FIG. 14C, since the surface of silicon oxide film 514 is formed at substantially the same hierarchical position in the peripheral circuit region and the memory cell forming region, Al wiring 527a may also be formed horizontally. it can. This allows
A across the memory cell formation area and the peripheral circuit formation area
Even when the l wiring 527a is formed, it can be formed on a flat surface, so that the Al wiring 527a
Problems such as disconnection can be suppressed.

Further, A reaches p-type impurity diffusion layer 534.
The 1-electrode 527b is used for the purpose of applying a predetermined voltage to the single-crystal silicon semiconductor layer 502 in the memory cell formation region, as in the first embodiment. That is, as described above, in the memory cell forming region, the element active regions 531 and 5
32 are defined, the single crystal silicon semiconductor layer 502
Are formed integrally over the entire area of the memory cell formation region without being partitioned. Therefore, by applying a predetermined voltage to the Al electrode 527b reaching the p-type impurity diffusion layer 534, all the element active regions 5 in the memory cell formation region
32 can generate a constant electric field.

Thus, the threshold value of the transistor in the memory cell formation region can be kept constant, and a semiconductor device with improved leakage characteristics can be formed.

Thereafter, a silicon oxide film 516 as a second interlayer insulating film is formed on the silicon oxide film 514 by the CVD method, and the Al wiring 527a and the Al electrode 527b are formed.
Is embedded to complete the semiconductor device according to the fourth embodiment.

In the third embodiment, the region shown on the right side in FIGS. 11 to 14 is a peripheral circuit region, and the region shown on the left side is a memory cell region of a DRAM, for example. From the viewpoint of reducing the area of the device, the device isolation region formed by the trench-type device isolation structure is more suitable for a CMOS circuit formed in the peripheral circuit region than the device isolation region formed by the field shield method. This is because it is more suitable for the memory cell region than the element isolation region by the pattern element isolation structure.

Then, in the memory cell formation region,
By applying a predetermined voltage to the single-crystal silicon semiconductor layer 502 of the SOI structure substrate 5, a substrate bias can be applied to the entire region of the plurality of element active regions 532 in the memory cell formation region.

More specifically, p-type impurity diffusion layer 534
By applying a substrate potential (substrate bias) of, for example, −2.0 V to the Al electrode 527 b reaching the substrate electrode, the substrate bias is simultaneously applied to the single crystal silicon semiconductor layer 502 over the entire memory cell formation region through the p-type impurity diffusion layer 534. Can be applied.

Moreover, the substrate bias does not reach the electrically independent element active region 530 in the peripheral circuit formation region. Therefore, it is possible to provide a structure that does not adversely affect the threshold value of the MOS transistor in the peripheral circuit formation region without forming the triple well structure. Thus, it is possible to prevent the threshold value of the MOS transistor in the peripheral circuit formation region from being increased by the substrate bias effect. Therefore, it is possible to reliably apply a substrate bias to the memory cell formation region while maintaining a good drive current of the MOS transistor in the peripheral circuit formation region and enabling high-speed operation.

Further, the semiconductor device of the third embodiment is
The OI structure substrate 5 has two regions having different surface heights. Therefore, even if an element having a high height is arranged in a region where the surface of the SOI structure substrate 5 is lower, the step on the surface of the interlayer insulating film on the element can be reduced in the entire region of the SOI structure substrate 5.

According to the third embodiment, the first region in which the element isolation region is formed by the trench type element isolation structure and the second region in which the element isolation region is formed by the field shield method.
Since the steps on the surface of the interlayer insulating film covering the region can be reduced, wiring can be easily formed on the semiconductor substrate, and a highly reliable semiconductor device can be manufactured.

Further, since the first region is suitable for a CMOS circuit and the second region has an excellent element isolation capability, a memory cell region having a high degree of integration and a peripheral circuit region having a CMOS structure are required. In addition, the wiring can be easily formed on the semiconductor substrate, and the reliability is high.

Further, by arranging a device having a higher height in a region where the surface of the semiconductor substrate is lower, a step on the surface of the interlayer insulating film on the device can be reduced in the entire region of the semiconductor substrate. Wiring can be easily formed on the interlayer insulating film, and reliability can be improved.

According to the above manufacturing steps, the region for forming the field shield element isolation structure is formed at a lower position than the region for forming the silicon oxide film for buried insulating film element isolation. It is important to contribute to Further, the silicon oxide film 505 as a buried insulating film at the boundary between the memory formation region and the peripheral circuit formation region has a forward tapered shape, which further contributes to the averaging.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS. 11 (a) to 12 (b), FIGS. 16 to 18, and FIG.

FIG. 16 to FIG. 18 are manufacturing steps showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
FIG. 19 corresponds to the plan view of FIG.
FIG. 18B is a cross-sectional view taken along line AA ′ of FIG. In these figures, the region shown on the right side is a peripheral circuit formation region, and the region shown on the left side is a memory cell formation region of a DRAM, for example. Further, a region surrounded by the device isolation structure in the right region and the left region is a device active region.

In the memory cell formation region, for example, a plurality of D
A RAM memory capacitor is formed, and a CMOS inverter is formed in a peripheral circuit formation region.
6 to 18 show only one access transistor of the DRAM memory capacitor in the memory cell formation region, and C in the peripheral circuit formation region.
Only one MOS transistor of the MOS inverter is shown.

In the fourth embodiment, first, after the steps of FIGS. 11A and 12B shown in the third embodiment, FIG.
As shown in FIG. 6A, the peripheral circuit formation region is covered with a photoresist film 506 except for a boundary region with the memory cell formation region (this point is different from the third embodiment), and wet etching is performed. Is applied. This wet etching is performed using hydrofluoric acid until the surface of the P-type silicon substrate in the memory cell formation region is exposed. This allows
A buried oxide film 505 having a trench-type element isolation structure is formed around the element active region in the peripheral circuit formation region.
Next, the photoresist film 506 is removed, the silicon nitride film 517 is removed by etching using hot phosphoric acid, and then the silicon oxide film 503 is removed by etching using hydrofluoric acid.

As a result, a trench type element isolation structure composed of the silicon oxide film 505 is formed. Then, in the peripheral circuit formation region, the silicon oxide film 505 and the buried oxide film 501 are connected, and the island-shaped element active region 530 which is insulated from the surrounding single crystal silicon semiconductor layer 502 and electrically independent is completed.

The subsequent steps are almost the same as those in the third embodiment. That is, as shown in FIG.
A shield gate oxide film 507 having a thickness of about 40 nm is formed on the surface of a P-type silicon substrate 501.

Next, as shown in FIG.
The polycrystalline silicon film 5 having a thickness of about 100 nm
08 is formed, and phosphorus is thermally diffused therein to reduce the resistance.
Next, a silicon oxide film 509 having a thickness of about 300 nm
Is formed on the entire surface by a CVD method.

Next, as shown in FIG. 17B, a silicon oxide film 50 is formed using a photoresist film (not shown).
9 and the polycrystalline silicon film 508 are selectively removed by etching to form a field shield electrode 508 and a cap insulating film 509.

Thereafter, as shown in FIG.
A sidewall insulating film 510 made of a silicon oxide film is formed in the same manner as in the embodiment. At this time, the shield gate insulating film 507 is removed from the element active regions in both the peripheral circuit formation region and the memory cell formation region. Through the above steps, the field shield element isolation structure 531 (shield gate insulating film 507, shield plate electrode 50
8, a cap oxide film 509 and a side wall insulating film 510) are formed in the memory cell formation region.

Here, the surface of the field shield element isolation structure 531 and the single crystal silicon semiconductor layer 502 and the silicon oxide film 505 in the peripheral circuit formation region are formed by the concave portions C formed in the single crystal silicon semiconductor layer 502 in advance. The surfaces will be formed at approximately the same hierarchical level.

By setting the shield plate electrode 508 of the field shield element isolation structure 531 to a predetermined potential,
The element can be separated by fixing the potential of the lower single-crystal silicon semiconductor layer 502. Thus, element active regions 532 and 533 are determined in the memory cell formation region. As described above, in the memory cell forming region, the element active regions 532 and 533 are defined by the field shield element separating structure 531, so that the element isolation is performed without dividing the single crystal silicon semiconductor layer 502 in the memory cell forming region. Will be.

Therefore, when a predetermined voltage is applied to single crystal silicon semiconductor layer 502 in the memory cell type region, single crystal silicon semiconductor layer 5
02, the electric field is formed in the entire region.

On the other hand, in the peripheral circuit formation region, since the region from the side surface to the bottom surface of element active region 530 is covered with silicon oxide film 505 and buried oxide film 501, the single crystal silicon semiconductor layer in the memory cell formation region is formed. The electric field applied to 502 does not extend.

Next, as shown in FIG. 18A, a gate insulating film 511 is formed, and a gate electrode 512 is formed thereon. Further, source / drain diffusion layers 513 are formed by ion implantation. At the time of this ion implantation, the element active region 533 is covered with a resist pattern 541. And
After forming the source / drain diffusion layers 513, the resist pattern 541 is removed.

In the memory cell formation region, an access transistor of a DRAM memory cell capacitor is constituted by these gate insulating film 511, gate electrode 512, and impurity diffusion layer 513.

Similarly, in the peripheral circuit forming region, the gate insulating film 511, the gate electrode 512, the impurity diffusion layer 5
13, for example, one MOS of a CMOS inverter
A transistor is configured. In the peripheral circuit formation region, since each element active region is electrically independent, the formed MOS transistor is equivalent to a so-called mesa transistor.

Subsequently, after the other region is covered with a photoresist (not shown) so that only the element active region 533 is exposed, ion implantation is performed. Here, the same conductivity type as that of the single crystal silicon semiconductor layer 502 of the SOI structure substrate 5, that is, p-type impurities is ion-implanted at a high concentration. And
By performing the heat treatment, the p-type impurity diffusion layer 5 is added to the single crystal silicon semiconductor layer 502 in the element active region 533.
34 are formed.

FIG. 19 is a plan view of FIG. In FIG. 19, reference numeral 505 denotes a silicon oxide film having a trench element isolation structure, and reference numeral 53 denotes a field shield element isolation structure. 512 is a gate electrode, 5
13 is an impurity diffusion layer, and 534 is a p-type impurity diffusion layer.

As shown in FIG. 19, a plurality of element active regions 532 are formed in the memory cell forming region by the above-described steps. Then, an access transistor is formed in each element active region 532 in the memory cell formation region. Similarly, a plurality of element active regions 530 are formed in the peripheral circuit formation region.

It is to be noted that, for example, CMOS
In the case of forming an inverter, these adjacent element active regions 530 are previously formed to have a reverse conductivity type, and
In the step of ion implantation shown in (b), the impurity diffusion layer may be formed by performing ion implantation twice so that each element active region 530 has the opposite conductivity type.

Thereafter, a lower electrode, a dielectric film, and an upper electrode of a memory capacitor (not shown) are formed in a memory cell formation region, for example. At this time, the lower electrode is connected to the impurity diffusion layer 513 on the left side of the element active region 532 in the memory cell formation region shown in FIG. And an access transistor and a lower electrode, a dielectric film,
One unit of memory cell is constituted by the memory capacitor including the upper electrode.

Next, as shown in FIG. 18C, a silicon oxide film 514 as an interlayer insulating film is deposited on the entire surface by the CVD method.

Since the surface of the field shield element isolation structure 531 and the surfaces of the single crystal silicon semiconductor layer 502 and the silicon oxide film 505 in the peripheral circuit formation region are formed at substantially the same hierarchical level, the silicon formed thereover is formed. The surface of oxide film 514 is also formed on substantially the same plane.

Then, contact holes 526a, 526 reaching impurity diffusion layer 513 and p-type impurity diffusion layer 534 are formed.
b is opened in the silicon oxide film 514. Then, an A1 film is deposited on the entire surface by sputtering, and the contact hole 526 is formed.
a, 526b. Then, similarly to the first embodiment, the A1 film is processed into a wiring pattern by a fine processing technique, and an Al wiring 527a reaching the impurity diffusion layer 513 and an Al electrode 527b reaching the p-type impurity diffusion layer 534 are formed.

As shown in FIG. 18C, since the surface of silicon oxide film 514 is formed at substantially the same hierarchical position in the peripheral circuit region and the memory cell forming region, Al wiring 527a may also be formed horizontally. it can. This allows
A across the memory cell formation area and the peripheral circuit formation area
Even when the l wiring 527a is formed, it can be formed on a flat surface, so that the Al wiring 527a
Problems such as disconnection can be suppressed.

Also, A reaching p-type impurity diffusion layer 534
The l-electrode 527b is used for applying a predetermined voltage to the single-crystal silicon semiconductor layer 512 in the memory cell formation region, as in the first embodiment. That is, as described above, in the memory cell forming region, the element active regions 531 and 5
32 are defined, the single crystal silicon semiconductor layer 502
Are formed integrally over the entire area of the memory cell formation region without being partitioned. Therefore, by applying a predetermined voltage to the Al electrode 527b reaching the p-type impurity diffusion layer 534, all the element active regions 5 in the memory cell formation region
32 can generate a constant electric field.

[0210] Thus, the threshold value of the transistor in the memory cell formation region can be kept constant, and a semiconductor device with improved leakage characteristics can be formed.

Thereafter, a silicon oxide film 516 as a second interlayer insulating film is formed on the silicon oxide film 514 by the CVD method, and the Al wiring 527a and the Al electrode 527b are formed.
Is embedded to complete the semiconductor device according to the fourth embodiment.

In the fourth embodiment, FIGS.
16B and FIG. 16 to FIG. 18, the area shown on the right side is a peripheral circuit area, and the area shown on the left side is, for example, a memory cell area of a DRAM. This is from the viewpoint of reducing the area of the element isolation region. Therefore, the element isolation region formed by the trench element isolation structure is more suitable for a CMOS circuit formed in the peripheral circuit region than the element isolation region formed by the field shield method, and the element isolation region formed by the field shield method has an element formed by the trench element isolation structure. This is because it is more suitable for the memory cell region than the isolation region.

In the memory cell formation region,
By applying a predetermined voltage to the single-crystal silicon semiconductor layer 502 of the SOI structure substrate 5, a substrate bias can be applied to the entire region of the plurality of element active regions 532 in the memory cell formation region.

More specifically, p-type impurity diffusion layer 534
A substrate potential (substrate bias) of, for example, −2.0 V is applied to the Al electrode 527 b that reaches the upper surface of the single crystal silicon semiconductor layer 502 in the memory cell forming region through the p-type impurity diffusion layer 534. Can be applied.

In addition, this substrate bias does not reach electrically independent element active region 530 in the peripheral circuit formation region. Therefore, it is possible to provide a structure that does not adversely affect the threshold value of the MOS transistor in the peripheral circuit formation region without forming the triple well structure. Thus, it is possible to prevent the threshold value of the MOS transistor in the peripheral circuit formation region from being increased by the substrate bias effect. Therefore, it is possible to reliably apply a substrate bias to the memory cell formation region while maintaining a good drive current of the MOS transistor in the peripheral circuit formation region and enabling high-speed operation.

Further, the semiconductor device according to the fifth embodiment has an S
The OI structure substrate 5 has two regions having different surface heights. Therefore, even if an element having a high height is arranged in a region where the surface of the SOI structure substrate 5 is lower, the step on the surface of the interlayer insulating film on the element can be reduced in the entire region of the SOI structure substrate 5.

According to the fourth embodiment, the first region in which the element isolation region is formed by the trench type element isolation structure and the second region in which the element isolation region is formed by the field shield method.
Since the steps on the surface of the interlayer insulating film covering the region can be reduced, wiring can be easily formed on the semiconductor substrate, and a highly reliable semiconductor device can be manufactured.

Further, since the first region is suitable for a CMOS circuit and the second region has excellent element isolation capability, a memory cell region having a high degree of integration and a peripheral circuit region having a CMOS structure can be used. In addition, the wiring can be easily formed on the semiconductor substrate, and the reliability is high.

Further, by arranging a device having a higher height in a region where the surface of the semiconductor substrate is lower, a step on the surface of the interlayer insulating film on the device can be reduced in the entire region of the semiconductor substrate. Wiring can be easily formed on the interlayer insulating film, and reliability can be improved.

Also in the fourth embodiment, the region for forming the field element isolation structure is formed lower than the region for forming the silicon oxide film for the buried insulating film element isolation. It is important to donate.

At the boundary between the peripheral circuit formation region and the memory cell formation region, the space factor can be improved because the field shield device isolation structure also serves as the device isolation structure of both regions.

Incidentally, similarly to the first embodiment, the second to fourth
Also in the embodiment, the DRA is formed in the memory cell formation region.
Memory cells other than the M memory capacitors may be formed. For example, a nonvolatile memory such as an EEPROM may be formed. Further, these volatile or non-volatile memories may be multivalued memories.

Also, as described in the first embodiment,
Also in the second to fourth embodiments, an element other than the memory cell may be formed in a region where element isolation has been achieved by the field shield element isolation structure. For example, in the region shown as the memory cell formation region in the second to fourth embodiments,
By forming another peripheral circuit having a transistor, a MOS in a region where an element is isolated by a trench-type element isolation structure formed so as to reach a buried oxide film is formed.
It is possible to coexist by changing the threshold value of the transistor and the threshold value of the MOS transistor in a region where element isolation has been achieved by the field shield element isolation structure.

For example, FIG. 20 shows an overall configuration diagram of a semiconductor device including an SOI structure substrate having a buried insulating layer. As described above, the semiconductor device is partitioned into four blocks, and blocks 1 and 2 are configured as memory cell formation regions, and blocks 3 and 4 are configured as peripheral circuit formation regions. As described in the first to fourth embodiments, it is preferable that the element isolation in the memory cell formation region (block 1 and block 2) be performed by the field shield element isolation structure. The element isolation of the block 3 in the peripheral circuit formation region is performed by the field shield element isolation structure, and the element isolation of the block 4 is performed by the element isolation structure reaching the buried insulating layer.

As a result, in the block 3 partitioned by the field shield element isolation structure, variation in the threshold value of the transistor is minimized, and in the block 4 in which each element active region is independent, the operation speed of the transistor is reduced. It can be raised to a high performance area.

In this case, the element isolation structure for partitioning the blocks 1 to 4 has an SO structure so that no electric field is transmitted between the blocks.
Each block is electrically independent as an element isolation structure reaching the buried insulating layer of the I structure substrate.

In the first to fourth embodiments,
A method has been described in which the substrate potential is applied to the memory cell formation region to stabilize the transistor in the memory cell formation region by setting the threshold value to a high value. A guard ring effect can be provided for an electric field from the peripheral circuit formation region.

For example, as shown in FIG. 21, a plurality of element active regions in a block 4 which is a peripheral circuit forming region are formed as electrically independent regions as shown in the first to fourth embodiments. Constitute. Then, an element active region 150 for providing a guard ring effect is formed so as to surround the block 4. By applying a predetermined potential to the element active region 150, the block 4 can be guarded from the other blocks 1 to 3, and can be made an electrically independent region.

In this case, too, naturally, block 1
4 and the element isolation structure 151 surrounding the block 4 have an element isolation structure reaching the buried insulating layer of the SOI structure substrate so that an electric field is not transmitted between the blocks.

The partition between the peripheral circuit formation region and the memory cell formation region is, as shown in block 1 of FIG.
Form an element isolation structure that reaches the buried insulating layer inside,
It may be divided into electrically independent blocks 1a and 1b. Also in this case, both of the blocks 1a and 1b may be used as a peripheral circuit formation region.

[0231]

According to the present invention, it is possible to provide a highly reliable semiconductor device by eliminating obstacles due to the difference in height of the element isolation structure, and to provide an element capable of simultaneously applying a substrate potential. It is possible to form an active region and an element active region electrically independent of the substrate potential.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a schematic plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 8 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 10 is a schematic plan view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 13 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 14 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 15 is a schematic plan view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 17 is a schematic sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 18 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 19 is a schematic plan view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 20 is a schematic plan view showing an example of the overall configuration of the semiconductor device of the present invention.

FIG. 21 is a schematic plan view showing an example of the overall configuration of the semiconductor device of the present invention.

[Explanation of symbols]

10, 100, 200, 300, 500 Single-crystal silicon semiconductor substrate part 11, 101, 201, 301, 501 Buried oxide film 27a, 227a, 327a, 527a Al wiring 27b, 227b, 327b, 527b Al electrode 30, 32, 33 , 150, 230, 232, 233,
330, 332, 333, 530, 532, 533 Device active region 31, 231, 331, 531 Field shield device isolation structure 34, 234, 334, 534 P-type impurity diffusion layer 40, 242, 540, 541 Resist pattern 108, 208, 308, 508 Polycrystalline silicon film (shield plate electrode) 151 Element isolation structure 202, 302, 502 Single crystal silicon semiconductor layer 203, 205, 206, 303, 305, 306, 5
03, 505, 506 silicon oxide film 204, 304, 504 silicon nitride film 207, 307, 507 shield gate oxide film 209, 309, 509 silicon oxide film (cap insulating film) 210, 310, 510 sidewall oxide film 211, 311 511 Gate oxide film 212, 312, 512 Gate electrode 213, 313, 513 Impurity diffusion layer (source / drain diffusion layer)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/10 481 H01L 21/76 D 29/786 29/78 621

Claims (16)

[Claims] 1. A semiconductor device having a semiconductor layer formed on a semiconductor substrate via an insulating layer, comprising: a first region having a first element active region defined by a first element isolation structure; A second region having a second device active region defined by a second device isolation structure provided with a separation electrode. The semiconductor layer of the second device active region has a thickness of the second device active region. A semiconductor device, wherein a predetermined potential is applied to an entire region of the semiconductor layer which is formed thinner than the thickness of the semiconductor layer in the first element active region and is continuous with the second element active region. 2. An impurity diffusion layer formed in the semiconductor layer in the second region, and an electrode connected to the impurity diffusion layer, wherein the substrate potential is supplied from the electrode via the impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein the voltage is applied. 3. The semiconductor device according to claim 1, wherein the impurity diffusion layer is formed near a boundary between the first region and the second region. 4. The semiconductor device according to claim 1, wherein a plurality of memory cells are formed in the second region, and a peripheral circuit is formed in the first region. 13. The semiconductor device according to claim 1. 5. A logic circuit according to claim 1, wherein a logic circuit is formed in each of said first and second regions.
The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein said first region and said second region are separated by said first element isolation structure. 7. The semiconductor according to claim 1, wherein each of the first region and the second region is surrounded by the first element isolation structure. apparatus. 8. The semiconductor device according to claim 1, wherein said first element isolation structure is made of an insulating film. 9. The semiconductor device according to claim 1, wherein said first element isolation structure is made of an insulator filling a groove formed in said semiconductor layer. 10. The element isolation structure according to claim 1, wherein the first element isolation structure includes a conductive film formed in a groove formed in the semiconductor layer via an insulating film.
10. The semiconductor device according to any one of items 9 to 9. 11. The device according to claim 1, wherein the first element isolation structure and the second element isolation structure are in contact with each other at a portion adjacent to the first region and the second region. 1
0. The semiconductor device according to claim 1. 12. The first device isolation structure according to claim 1, wherein
12. The semiconductor device according to claim 1, wherein a region adjacent to the second region is tapered toward the second region. 13. The semiconductor device according to claim 1, wherein a part of the second element isolation structure is continuously superimposed on the semiconductor layer in the first region. 13. The semiconductor device according to claim 1. 14. The semiconductor device according to claim 1, wherein a bottom region of said first element isolation structure is formed so as to be in contact with said insulating layer. 15. A step formed on a surface of a semiconductor layer provided on a semiconductor substrate with an insulating layer interposed therebetween, wherein a first region in which a surface of the semiconductor layer is located above the stepped portion and the first region, A method for manufacturing a semiconductor device comprising a semiconductor substrate having a second region in which a surface of a semiconductor layer is located in a lower layer, wherein a first element isolation structure reaching the semiconductor layer is provided in the first region. Forming a first element active region to form a first element active region; and forming, in the second region, a field shield element isolation structure having a surface located at substantially the same hierarchical level as the surface of the first element isolation structure. A method for manufacturing a semiconductor device, comprising: a second step of forming; and a third step of forming an electrode connected to the semiconductor layer in the second region. 16. The method according to claim 15, wherein the first element isolation structure is formed of an insulating film.